[thirdparty/u-boot.git] / include / sdhci.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */
#ifndef __SDHCI_HW_H
#define __SDHCI_HW_H

#include <linux/bitops.h>
#include <linux/types.h>
#include <asm/io.h>
#include <mmc.h>
#include <asm/gpio.h>

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		BIT(0)
#define  SDHCI_TRNS_BLK_CNT_EN	BIT(1)
#define  SDHCI_TRNS_ACMD12	BIT(2)
#define  SDHCI_TRNS_READ	BIT(4)
#define  SDHCI_TRNS_MULTI	BIT(5)

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20
#define  SDHCI_CMD_ABORTCMD	0xC0

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	BIT(0)
#define  SDHCI_DATA_INHIBIT	BIT(1)
#define  SDHCI_DAT_ACTIVE	BIT(2)
#define  SDHCI_DOING_WRITE	BIT(8)
#define  SDHCI_DOING_READ	BIT(9)
#define  SDHCI_SPACE_AVAILABLE	BIT(10)
#define  SDHCI_DATA_AVAILABLE	BIT(11)
#define  SDHCI_CARD_PRESENT	BIT(16)
#define  SDHCI_CARD_STATE_STABLE	BIT(17)
#define  SDHCI_CARD_DETECT_PIN_LEVEL	BIT(18)
#define  SDHCI_WRITE_PROTECT	BIT(19)
#define  SDHCI_DATA_LVL_MASK	0x00F00000
#define   SDHCI_DATA_0_LVL_MASK BIT(20)

#define SDHCI_HOST_CONTROL	0x28
#define  SDHCI_CTRL_LED		BIT(0)
#define  SDHCI_CTRL_4BITBUS	BIT(1)
#define  SDHCI_CTRL_HISPD	BIT(2)
#define  SDHCI_CTRL_DMA_MASK	0x18
#define   SDHCI_CTRL_SDMA	0x00
#define   SDHCI_CTRL_ADMA1	0x08
#define   SDHCI_CTRL_ADMA32	0x10
#define   SDHCI_CTRL_ADMA64	0x18
#define  SDHCI_CTRL_8BITBUS	BIT(5)
#define  SDHCI_CTRL_CD_TEST_INS	BIT(6)
#define  SDHCI_CTRL_CD_TEST	BIT(7)

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B
#define  SDHCI_WAKE_ON_INT	BIT(0)
#define  SDHCI_WAKE_ON_INSERT	BIT(1)
#define  SDHCI_WAKE_ON_REMOVE	BIT(2)

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_DIVIDER_HI_SHIFT	6
#define  SDHCI_DIV_MASK	0xFF
#define  SDHCI_DIV_MASK_LEN	8
#define  SDHCI_DIV_HI_MASK	0x300
#define  SDHCI_PROG_CLOCK_MODE  BIT(5)
#define  SDHCI_CLOCK_CARD_EN	BIT(2)
#define  SDHCI_CLOCK_INT_STABLE	BIT(1)
#define  SDHCI_CLOCK_INT_EN	BIT(0)

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	BIT(0)
#define  SDHCI_INT_DATA_END	BIT(1)
#define  SDHCI_INT_DMA_END	BIT(3)
#define  SDHCI_INT_SPACE_AVAIL	BIT(4)
#define  SDHCI_INT_DATA_AVAIL	BIT(5)
#define  SDHCI_INT_CARD_INSERT	BIT(6)
#define  SDHCI_INT_CARD_REMOVE	BIT(7)
#define  SDHCI_INT_CARD_INT	BIT(8)
#define  SDHCI_INT_ERROR	BIT(15)
#define  SDHCI_INT_TIMEOUT	BIT(16)
#define  SDHCI_INT_CRC		BIT(17)
#define  SDHCI_INT_END_BIT	BIT(18)
#define  SDHCI_INT_INDEX	BIT(19)
#define  SDHCI_INT_DATA_TIMEOUT	BIT(20)
#define  SDHCI_INT_DATA_CRC	BIT(21)
#define  SDHCI_INT_DATA_END_BIT	BIT(22)
#define  SDHCI_INT_BUS_POWER	BIT(23)
#define  SDHCI_INT_ACMD12ERR	BIT(24)
#define  SDHCI_INT_ADMA_ERROR	BIT(25)

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK	((unsigned int)-1)

#define SDHCI_ACMD12_ERR	0x3C

#define SDHCI_HOST_CONTROL2	0x3E
#define  SDHCI_CTRL_UHS_MASK	0x0007
#define  SDHCI_CTRL_UHS_SDR12	0x0000
#define  SDHCI_CTRL_UHS_SDR25	0x0001
#define  SDHCI_CTRL_UHS_SDR50	0x0002
#define  SDHCI_CTRL_UHS_SDR104	0x0003
#define  SDHCI_CTRL_UHS_DDR50	0x0004
#define  SDHCI_CTRL_HS400	0x0005 /* Non-standard */
#define  SDHCI_CTRL_VDD_180	0x0008
#define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
#define  SDHCI_CTRL_DRV_TYPE_B	0x0000
#define  SDHCI_CTRL_DRV_TYPE_A	0x0010
#define  SDHCI_CTRL_DRV_TYPE_C	0x0020
#define  SDHCI_CTRL_DRV_TYPE_D	0x0030
#define  SDHCI_CTRL_EXEC_TUNING	0x0040
#define  SDHCI_CTRL_TUNED_CLK	0x0080
#define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_8BIT	BIT(18)
#define  SDHCI_CAN_DO_ADMA2	BIT(19)
#define  SDHCI_CAN_DO_ADMA1	BIT(20)
#define  SDHCI_CAN_DO_HISPD	BIT(21)
#define  SDHCI_CAN_DO_SDMA	BIT(22)
#define  SDHCI_CAN_VDD_330	BIT(24)
#define  SDHCI_CAN_VDD_300	BIT(25)
#define  SDHCI_CAN_VDD_180	BIT(26)
#define  SDHCI_CAN_64BIT	BIT(28)

#define SDHCI_CAPABILITIES_1	0x44
#define  SDHCI_SUPPORT_SDR50	0x00000001
#define  SDHCI_SUPPORT_SDR104	0x00000002
#define  SDHCI_SUPPORT_DDR50	0x00000004
#define  SDHCI_SUPPORT_HS400	BIT(31)
#define  SDHCI_USE_SDR50_TUNING	0x00002000

#define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
#define  SDHCI_CLOCK_MUL_SHIFT	16

#define SDHCI_MAX_CURRENT	0x48

/* 4C-4F reserved for more max current */

#define SDHCI_SET_ACMD12_ERROR	0x50
#define SDHCI_SET_INT_ERROR	0x52

#define SDHCI_ADMA_ERROR	0x54

/* 55-57 reserved */

#define SDHCI_ADMA_ADDRESS	0x58
#define SDHCI_ADMA_ADDRESS_HI	0x5c

/* 60-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0
#define   SDHCI_SPEC_100	0
#define   SDHCI_SPEC_200	1
#define   SDHCI_SPEC_300	2

#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)

/*
 * End of controller registers.
 */

#define SDHCI_MAX_DIV_SPEC_200	256
#define SDHCI_MAX_DIV_SPEC_300	2046

/*
 * quirks
 */
#define SDHCI_QUIRK_32BIT_DMA_ADDR	(1 << 0)
#define SDHCI_QUIRK_REG32_RW		(1 << 1)
#define SDHCI_QUIRK_BROKEN_R1B		(1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT	(1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE	(1 << 4)
/*
 * SDHCI_QUIRK_BROKEN_HISPD_MODE
 * the hardware cannot operate correctly in high-speed mode,
 * this quirk forces the sdhci host-controller to non high-speed mode
 */
#define SDHCI_QUIRK_BROKEN_HISPD_MODE	BIT(5)
#define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
#define SDHCI_QUIRK_USE_WIDE8		(1 << 8)
#define SDHCI_QUIRK_NO_1_8_V		(1 << 9)
#define SDHCI_QUIRK_SUPPORT_SINGLE	(1 << 10)
/* Capability register bit-63 indicates HS400 support */
#define SDHCI_QUIRK_CAPS_BIT63_FOR_HS400	BIT(11)

/* to make gcc happy */
struct sdhci_host;

/*
 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 */
#define SDHCI_DEFAULT_BOUNDARY_SIZE	(512 * 1024)
#define SDHCI_DEFAULT_BOUNDARY_ARG	(7)
struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	u32	(*read_l)(struct sdhci_host *host, int reg);
	u16	(*read_w)(struct sdhci_host *host, int reg);
	u8	(*read_b)(struct sdhci_host *host, int reg);
	void	(*write_l)(struct sdhci_host *host, u32 val, int reg);
	void	(*write_w)(struct sdhci_host *host, u16 val, int reg);
	void	(*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif
	int	(*get_cd)(struct sdhci_host *host);
	void	(*set_control_reg)(struct sdhci_host *host);
	int	(*set_ios_post)(struct sdhci_host *host);
	void	(*set_clock)(struct sdhci_host *host, u32 div);
	int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
	int (*set_delay)(struct sdhci_host *host);
	/* Callback function to set DLL clock configuration */
	int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
	int	(*deferred_probe)(struct sdhci_host *host);

	/**
	 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
	 *
	 * This is called after setting the card speed and mode to
	 * HS400 ES, and should set any host-specific configuration
	 * necessary for it.
	 *
	 * @host: SDHCI host structure
	 * Return: 0 if successful, -ve on error
	 */
	int	(*set_enhanced_strobe)(struct sdhci_host *host);
};

#define ADMA_MAX_LEN	65532
#ifdef CONFIG_DMA_ADDR_T_64BIT
#define ADMA_DESC_LEN	16
#else
#define ADMA_DESC_LEN	8
#endif
#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
			       MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN

#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)

/* Decriptor table defines */
#define ADMA_DESC_ATTR_VALID		BIT(0)
#define ADMA_DESC_ATTR_END		BIT(1)
#define ADMA_DESC_ATTR_INT		BIT(2)
#define ADMA_DESC_ATTR_ACT1		BIT(4)
#define ADMA_DESC_ATTR_ACT2		BIT(5)

#define ADMA_DESC_TRANSFER_DATA		ADMA_DESC_ATTR_ACT2
#define ADMA_DESC_LINK_DESC	(ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)

struct sdhci_adma_desc {
	u8 attr;
	u8 reserved;
	u16 len;
	u32 addr_lo;
#ifdef CONFIG_DMA_ADDR_T_64BIT
	u32 addr_hi;
#endif
} __packed;

struct sdhci_host {
	const char *name;
	void *ioaddr;
	unsigned int quirks;
	unsigned int host_caps;
	unsigned int version;
	unsigned int max_clk;   /* Maximum Base Clock frequency */
	unsigned int clk_mul;   /* Clock Multiplier value */
	unsigned int clock;
	struct mmc *mmc;
	const struct sdhci_ops *ops;
	int index;

	int bus_width;
	struct gpio_desc pwr_gpio;	/* Power GPIO */
	struct gpio_desc cd_gpio;		/* Card Detect GPIO */

	uint	voltages;

	struct mmc_config cfg;
	void *align_buffer;
	bool force_align_buffer;
	dma_addr_t start_addr;
	int flags;
#define USE_SDMA	(0x1 << 0)
#define USE_ADMA	(0x1 << 1)
#define USE_ADMA64	(0x1 << 2)
#define USE_DMA		(USE_SDMA | USE_ADMA | USE_ADMA64)
	dma_addr_t adma_addr;
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
	struct sdhci_adma_desc *adma_desc_table;
#endif
};

#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	if (unlikely(host->ops->write_l))
		host->ops->write_l(host, val, reg);
	else
		writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	if (unlikely(host->ops->write_w))
		host->ops->write_w(host, val, reg);
	else
		writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	if (unlikely(host->ops->write_b))
		host->ops->write_b(host, val, reg);
	else
		writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_l))
		return host->ops->read_l(host, reg);
	else
		return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_w))
		return host->ops->read_w(host, reg);
	else
		return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_b))
		return host->ops->read_b(host, reg);
	else
		return readb(host->ioaddr + reg);
}

#else

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	writeb(val, host->ioaddr + reg);
}
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	return readb(host->ioaddr + reg);
}
#endif

#ifdef CONFIG_BLK
/**
 * sdhci_setup_cfg() - Set up the configuration for DWMMC
 *
 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
 *
 * This should be called from your MMC driver's probe() method once you have
 * the information required.
 *
 * Generally your driver will have a platform data structure which holds both
 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
 * For example:
 *
 * struct msm_sdhc_plat {
 *	struct mmc_config cfg;
 *	struct mmc mmc;
 * };
 *
 * ...
 *
 * Inside U_BOOT_DRIVER():
 *	.plat_auto	= sizeof(struct msm_sdhc_plat),
 *
 * To access platform data:
 *	struct msm_sdhc_plat *plat = dev_get_plat(dev);
 *
 * See msm_sdhci.c for an example.
 *
 * @cfg:	Configuration structure to fill in (generally &plat->mmc)
 * @host:	SDHCI host structure
 * @f_max:	Maximum supported clock frequency in HZ (0 for default)
 * @f_min:	Minimum supported clock frequency in HZ (0 for default)
 */
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
		    u32 f_max, u32 f_min);

/**
 * sdhci_bind() - Set up a new MMC block device
 *
 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
 * It should be called from your driver's bind() method.
 *
 * See msm_sdhci.c for an example.
 *
 * @dev:	Device to set up
 * @mmc:	Pointer to mmc structure (normally &plat->mmc)
 * @cfg:	Empty configuration structure (generally &plat->cfg). This is
 *		normally all zeroes at this point. The only purpose of passing
 *		this in is to set mmc->cfg to it.
 * Return: 0 if OK, -ve if the block device could not be created
 */
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
#else

/**
 * add_sdhci() - Add a new SDHCI interface
 *
 * This is used when you are not using CONFIG_BLK. Convert your driver over!
 *
 * @host:	SDHCI host structure
 * @f_max:	Maximum supported clock frequency in HZ (0 for default)
 * @f_min:	Minimum supported clock frequency in HZ (0 for default)
 * Return: 0 if OK, -ve on error
 */
int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
#endif /* !CONFIG_BLK */

void sdhci_set_uhs_timing(struct sdhci_host *host);
#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
int sdhci_set_clock(struct mmc *mmc, unsigned int clock);

/**
 * sdhci_set_control_reg - Set control registers
 *
 * This is used set up control registers for voltage level and UHS speed
 * mode.
 *
 * @host: SDHCI host structure
 */
void sdhci_set_control_reg(struct sdhci_host *host);
extern const struct dm_mmc_ops sdhci_ops;
#else
#endif

struct sdhci_adma_desc *sdhci_adma_init(void);
void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
			      struct mmc_data *data, dma_addr_t addr);

#endif /* __SDHCI_HW_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
af62a557 LW	2	/*
	3	* Copyright 2011, Marvell Semiconductor Inc.
	4	* Lei Wen <leiwen@marvell.com>
	5	*
af62a557 LW	6	* Back ported to the 8xx platform (from the 8260 platform) by
	7	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	8	*/
	9	#ifndef __SDHCI_HW_H
	10	#define __SDHCI_HW_H
	11
cd93d625	12	#include <linux/bitops.h>
f5df6aa1	13	#include <linux/types.h>
af62a557	14	#include <asm/io.h>
6cf1b17c	15	#include <mmc.h>
0347960b	16	#include <asm/gpio.h>
6cf1b17c	17
af62a557 LW	18	/*
	19	* Controller registers
	20	*/
	21
	22	#define SDHCI_DMA_ADDRESS 0x00
	23
	24	#define SDHCI_BLOCK_SIZE 0x04
	25	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
	26
	27	#define SDHCI_BLOCK_COUNT 0x06
	28
	29	#define SDHCI_ARGUMENT 0x08
	30
	31	#define SDHCI_TRANSFER_MODE 0x0C
91914581 JC	32	#define SDHCI_TRNS_DMA BIT(0)
	33	#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
	34	#define SDHCI_TRNS_ACMD12 BIT(2)
	35	#define SDHCI_TRNS_READ BIT(4)
	36	#define SDHCI_TRNS_MULTI BIT(5)
af62a557 LW	37
	38	#define SDHCI_COMMAND 0x0E
	39	#define SDHCI_CMD_RESP_MASK 0x03
	40	#define SDHCI_CMD_CRC 0x08
	41	#define SDHCI_CMD_INDEX 0x10
	42	#define SDHCI_CMD_DATA 0x20
	43	#define SDHCI_CMD_ABORTCMD 0xC0
	44
	45	#define SDHCI_CMD_RESP_NONE 0x00
	46	#define SDHCI_CMD_RESP_LONG 0x01
	47	#define SDHCI_CMD_RESP_SHORT 0x02
	48	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	49
	50	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
	51	#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
	52
	53	#define SDHCI_RESPONSE 0x10
	54
	55	#define SDHCI_BUFFER 0x20
	56
	57	#define SDHCI_PRESENT_STATE 0x24
91914581 JC	58	#define SDHCI_CMD_INHIBIT BIT(0)
91914581 JC	59	#define SDHCI_DATA_INHIBIT BIT(1)
21c84bb1	60	#define SDHCI_DAT_ACTIVE BIT(2)
91914581 JC	61	#define SDHCI_DOING_WRITE BIT(8)
	62	#define SDHCI_DOING_READ BIT(9)
	63	#define SDHCI_SPACE_AVAILABLE BIT(10)
	64	#define SDHCI_DATA_AVAILABLE BIT(11)
	65	#define SDHCI_CARD_PRESENT BIT(16)
	66	#define SDHCI_CARD_STATE_STABLE BIT(17)
	67	#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
	68	#define SDHCI_WRITE_PROTECT BIT(19)
40e6f524 SC	69	#define SDHCI_DATA_LVL_MASK 0x00F00000
40e6f524 SC	70	#define SDHCI_DATA_0_LVL_MASK BIT(20)
af62a557 LW	71
af62a557 LW	72	#define SDHCI_HOST_CONTROL 0x28
91914581 JC	73	#define SDHCI_CTRL_LED BIT(0)
	74	#define SDHCI_CTRL_4BITBUS BIT(1)
	75	#define SDHCI_CTRL_HISPD BIT(2)
af62a557 LW	76	#define SDHCI_CTRL_DMA_MASK 0x18
	77	#define SDHCI_CTRL_SDMA 0x00
	78	#define SDHCI_CTRL_ADMA1 0x08
	79	#define SDHCI_CTRL_ADMA32 0x10
	80	#define SDHCI_CTRL_ADMA64 0x18
91914581 JC	81	#define SDHCI_CTRL_8BITBUS BIT(5)
	82	#define SDHCI_CTRL_CD_TEST_INS BIT(6)
	83	#define SDHCI_CTRL_CD_TEST BIT(7)
af62a557 LW	84
	85	#define SDHCI_POWER_CONTROL 0x29
	86	#define SDHCI_POWER_ON 0x01
	87	#define SDHCI_POWER_180 0x0A
	88	#define SDHCI_POWER_300 0x0C
	89	#define SDHCI_POWER_330 0x0E
	90
	91	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	92
	93	#define SDHCI_WAKE_UP_CONTROL 0x2B
91914581 JC	94	#define SDHCI_WAKE_ON_INT BIT(0)
	95	#define SDHCI_WAKE_ON_INSERT BIT(1)
	96	#define SDHCI_WAKE_ON_REMOVE BIT(2)
af62a557 LW	97
	98	#define SDHCI_CLOCK_CONTROL 0x2C
	99	#define SDHCI_DIVIDER_SHIFT 8
	100	#define SDHCI_DIVIDER_HI_SHIFT 6
	101	#define SDHCI_DIV_MASK 0xFF
	102	#define SDHCI_DIV_MASK_LEN 8
	103	#define SDHCI_DIV_HI_MASK 0x300
91914581 JC	104	#define SDHCI_PROG_CLOCK_MODE BIT(5)
	105	#define SDHCI_CLOCK_CARD_EN BIT(2)
	106	#define SDHCI_CLOCK_INT_STABLE BIT(1)
	107	#define SDHCI_CLOCK_INT_EN BIT(0)
af62a557 LW	108
	109	#define SDHCI_TIMEOUT_CONTROL 0x2E
	110
	111	#define SDHCI_SOFTWARE_RESET 0x2F
	112	#define SDHCI_RESET_ALL 0x01
	113	#define SDHCI_RESET_CMD 0x02
	114	#define SDHCI_RESET_DATA 0x04
	115
	116	#define SDHCI_INT_STATUS 0x30
	117	#define SDHCI_INT_ENABLE 0x34
	118	#define SDHCI_SIGNAL_ENABLE 0x38
91914581 JC	119	#define SDHCI_INT_RESPONSE BIT(0)
	120	#define SDHCI_INT_DATA_END BIT(1)
	121	#define SDHCI_INT_DMA_END BIT(3)
	122	#define SDHCI_INT_SPACE_AVAIL BIT(4)
	123	#define SDHCI_INT_DATA_AVAIL BIT(5)
	124	#define SDHCI_INT_CARD_INSERT BIT(6)
	125	#define SDHCI_INT_CARD_REMOVE BIT(7)
	126	#define SDHCI_INT_CARD_INT BIT(8)
	127	#define SDHCI_INT_ERROR BIT(15)
	128	#define SDHCI_INT_TIMEOUT BIT(16)
	129	#define SDHCI_INT_CRC BIT(17)
	130	#define SDHCI_INT_END_BIT BIT(18)
	131	#define SDHCI_INT_INDEX BIT(19)
	132	#define SDHCI_INT_DATA_TIMEOUT BIT(20)
	133	#define SDHCI_INT_DATA_CRC BIT(21)
	134	#define SDHCI_INT_DATA_END_BIT BIT(22)
	135	#define SDHCI_INT_BUS_POWER BIT(23)
	136	#define SDHCI_INT_ACMD12ERR BIT(24)
	137	#define SDHCI_INT_ADMA_ERROR BIT(25)
af62a557 LW	138
	139	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	140	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	141
	142	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	143	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	144	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
	145	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
	146	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
	147	SDHCI_INT_DATA_END_BIT \| SDHCI_INT_ADMA_ERROR)
	148	#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
	149
	150	#define SDHCI_ACMD12_ERR 0x3C
	151
d1c0a220 FA	152	#define SDHCI_HOST_CONTROL2 0x3E
	153	#define SDHCI_CTRL_UHS_MASK 0x0007
	154	#define SDHCI_CTRL_UHS_SDR12 0x0000
	155	#define SDHCI_CTRL_UHS_SDR25 0x0001
	156	#define SDHCI_CTRL_UHS_SDR50 0x0002
	157	#define SDHCI_CTRL_UHS_SDR104 0x0003
	158	#define SDHCI_CTRL_UHS_DDR50 0x0004
	159	#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
	160	#define SDHCI_CTRL_VDD_180 0x0008
	161	#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
	162	#define SDHCI_CTRL_DRV_TYPE_B 0x0000
	163	#define SDHCI_CTRL_DRV_TYPE_A 0x0010
	164	#define SDHCI_CTRL_DRV_TYPE_C 0x0020
	165	#define SDHCI_CTRL_DRV_TYPE_D 0x0030
	166	#define SDHCI_CTRL_EXEC_TUNING 0x0040
	167	#define SDHCI_CTRL_TUNED_CLK 0x0080
	168	#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
af62a557 LW	169
	170	#define SDHCI_CAPABILITIES 0x40
	171	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	172	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	173	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
	174	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
	175	#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
	176	#define SDHCI_CLOCK_BASE_SHIFT 8
	177	#define SDHCI_MAX_BLOCK_MASK 0x00030000
	178	#define SDHCI_MAX_BLOCK_SHIFT 16
91914581 JC	179	#define SDHCI_CAN_DO_8BIT BIT(18)
	180	#define SDHCI_CAN_DO_ADMA2 BIT(19)
	181	#define SDHCI_CAN_DO_ADMA1 BIT(20)
	182	#define SDHCI_CAN_DO_HISPD BIT(21)
	183	#define SDHCI_CAN_DO_SDMA BIT(22)
	184	#define SDHCI_CAN_VDD_330 BIT(24)
	185	#define SDHCI_CAN_VDD_300 BIT(25)
	186	#define SDHCI_CAN_VDD_180 BIT(26)
	187	#define SDHCI_CAN_64BIT BIT(28)
af62a557 LW	188
af62a557 LW	189	#define SDHCI_CAPABILITIES_1 0x44
b8e25ef1 SDPP	190	#define SDHCI_SUPPORT_SDR50 0x00000001
	191	#define SDHCI_SUPPORT_SDR104 0x00000002
	192	#define SDHCI_SUPPORT_DDR50 0x00000004
386f5d36	193	#define SDHCI_SUPPORT_HS400 BIT(31)
b8e25ef1 SDPP	194	#define SDHCI_USE_SDR50_TUNING 0x00002000
b8e25ef1 SDPP	195
a0d0d86f WY	196	#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
a0d0d86f WY	197	#define SDHCI_CLOCK_MUL_SHIFT 16
af62a557 LW	198
	199	#define SDHCI_MAX_CURRENT 0x48
	200
	201	/* 4C-4F reserved for more max current */
	202
	203	#define SDHCI_SET_ACMD12_ERROR 0x50
	204	#define SDHCI_SET_INT_ERROR 0x52
	205
	206	#define SDHCI_ADMA_ERROR 0x54
	207
	208	/* 55-57 reserved */
	209
	210	#define SDHCI_ADMA_ADDRESS 0x58
37cb626d	211	#define SDHCI_ADMA_ADDRESS_HI 0x5c
af62a557 LW	212
	213	/* 60-FB reserved */
	214
	215	#define SDHCI_SLOT_INT_STATUS 0xFC
	216
	217	#define SDHCI_HOST_VERSION 0xFE
	218	#define SDHCI_VENDOR_VER_MASK 0xFF00
	219	#define SDHCI_VENDOR_VER_SHIFT 8
	220	#define SDHCI_SPEC_VER_MASK 0x00FF
	221	#define SDHCI_SPEC_VER_SHIFT 0
	222	#define SDHCI_SPEC_100 0
	223	#define SDHCI_SPEC_200 1
	224	#define SDHCI_SPEC_300 2
	225
113e5dfc JC	226	#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
113e5dfc JC	227
af62a557 LW	228	/*
	229	* End of controller registers.
	230	*/
	231
	232	#define SDHCI_MAX_DIV_SPEC_200 256
	233	#define SDHCI_MAX_DIV_SPEC_300 2046
	234
	235	/*
	236	* quirks
	237	*/
	238	#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
5af9a569	239	#define SDHCI_QUIRK_REG32_RW (1 << 1)
3a638320	240	#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
236bfecf JC	241	#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
236bfecf JC	242	#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
88a57125 HS	243	/*
	244	* SDHCI_QUIRK_BROKEN_HISPD_MODE
	245	* the hardware cannot operate correctly in high-speed mode,
	246	* this quirk forces the sdhci host-controller to non high-speed mode
	247	*/
	248	#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
13243f2e	249	#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
113e5dfc	250	#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
7a49a16e	251	#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
2b0dd417	252	#define SDHCI_QUIRK_SUPPORT_SINGLE (1 << 10)
386f5d36 ARS	253	/* Capability register bit-63 indicates HS400 support */
386f5d36 ARS	254	#define SDHCI_QUIRK_CAPS_BIT63_FOR_HS400 BIT(11)
af62a557	255
0d2f15f9 LW	256	/* to make gcc happy */
	257	struct sdhci_host;
	258
af62a557 LW	259	/*
	260	* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
	261	*/
	262	#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
	263	#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
	264	struct sdhci_ops {
	265	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
62226b68 JC	266	u32 (read_l)(struct sdhci_host host, int reg);
	267	u16 (read_w)(struct sdhci_host host, int reg);
	268	u8 (read_b)(struct sdhci_host host, int reg);
	269	void (write_l)(struct sdhci_host host, u32 val, int reg);
	270	void (write_w)(struct sdhci_host host, u16 val, int reg);
	271	void (write_b)(struct sdhci_host host, u8 val, int reg);
af62a557	272	#endif
62226b68 JC	273	int (get_cd)(struct sdhci_host host);
62226b68 JC	274	void (set_control_reg)(struct sdhci_host host);
a8185c50	275	int (set_ios_post)(struct sdhci_host host);
62226b68	276	void (set_clock)(struct sdhci_host host, u32 div);
2fc3ed5d	277	int (platform_execute_tuning)(struct mmc host, u8 opcode);
16b593be	278	int (set_delay)(struct sdhci_host host);
6f5bb991 ARS	279	/* Callback function to set DLL clock configuration */
6f5bb991 ARS	280	int (config_dll)(struct sdhci_host host, u32 clock, bool enable);
cb884347	281	int (deferred_probe)(struct sdhci_host host);
2a1d7c63 ANY	282
	283	/**
	284	* set_enhanced_strobe() - Set HS400 Enhanced Strobe config
	285	*
	286	* This is called after setting the card speed and mode to
	287	* HS400 ES, and should set any host-specific configuration
	288	* necessary for it.
	289	*
	290	* @host: SDHCI host structure
	291	* Return: 0 if successful, -ve on error
	292	*/
	293	int (set_enhanced_strobe)(struct sdhci_host host);
af62a557 LW	294	};
af62a557 LW	295
37cb626d FA	296	#define ADMA_MAX_LEN 65532
	297	#ifdef CONFIG_DMA_ADDR_T_64BIT
	298	#define ADMA_DESC_LEN 16
	299	#else
	300	#define ADMA_DESC_LEN 8
	301	#endif
	302	#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
	303	MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
	304
	305	#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
	306
	307	/* Decriptor table defines */
	308	#define ADMA_DESC_ATTR_VALID BIT(0)
	309	#define ADMA_DESC_ATTR_END BIT(1)
	310	#define ADMA_DESC_ATTR_INT BIT(2)
	311	#define ADMA_DESC_ATTR_ACT1 BIT(4)
	312	#define ADMA_DESC_ATTR_ACT2 BIT(5)
	313
	314	#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
	315	#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 \| ADMA_DESC_ATTR_ACT2)
	316
	317	struct sdhci_adma_desc {
	318	u8 attr;
	319	u8 reserved;
	320	u16 len;
	321	u32 addr_lo;
	322	#ifdef CONFIG_DMA_ADDR_T_64BIT
	323	u32 addr_hi;
	324	#endif
	325	} __packed;
4d6a773b	326
af62a557	327	struct sdhci_host {
cacd1d2f	328	const char *name;
af62a557 LW	329	void *ioaddr;
af62a557 LW	330	unsigned int quirks;
236bfecf	331	unsigned int host_caps;
af62a557	332	unsigned int version;
6d0e34bf	333	unsigned int max_clk; /* Maximum Base Clock frequency */
6dffdbc3	334	unsigned int clk_mul; /* Clock Multiplier value */
af62a557	335	unsigned int clock;
6cf1b17c	336	struct mmc *mmc;
af62a557	337	const struct sdhci_ops *ops;
b09ed6e4	338	int index;
236bfecf	339
3577fe8b	340	int bus_width;
0347960b SG	341	struct gpio_desc pwr_gpio; /* Power GPIO */
0347960b SG	342	struct gpio_desc cd_gpio; /* Card Detect GPIO */
3577fe8b	343
236bfecf	344	uint voltages;
93bfd616 PA	345
93bfd616 PA	346	struct mmc_config cfg;
c8cc18b7	347	void *align_buffer;
f5df6aa1	348	bool force_align_buffer;
6d6af205 FA	349	dma_addr_t start_addr;
	350	int flags;
	351	#define USE_SDMA (0x1 << 0)
37cb626d FA	352	#define USE_ADMA (0x1 << 1)
	353	#define USE_ADMA64 (0x1 << 2)
	354	#define USE_DMA (USE_SDMA \| USE_ADMA \| USE_ADMA64)
	355	dma_addr_t adma_addr;
	356	#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
	357	struct sdhci_adma_desc *adma_desc_table;
37cb626d	358	#endif
af62a557 LW	359	};
	360
	361	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	362
	363	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	364	{
	365	if (unlikely(host->ops->write_l))
	366	host->ops->write_l(host, val, reg);
	367	else
	368	writel(val, host->ioaddr + reg);
	369	}
	370
	371	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	372	{
	373	if (unlikely(host->ops->write_w))
	374	host->ops->write_w(host, val, reg);
	375	else
	376	writew(val, host->ioaddr + reg);
	377	}
	378
	379	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	380	{
	381	if (unlikely(host->ops->write_b))
	382	host->ops->write_b(host, val, reg);
	383	else
	384	writeb(val, host->ioaddr + reg);
	385	}
	386
	387	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	388	{
	389	if (unlikely(host->ops->read_l))
	390	return host->ops->read_l(host, reg);
	391	else
	392	return readl(host->ioaddr + reg);
	393	}
	394
	395	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	396	{
	397	if (unlikely(host->ops->read_w))
	398	return host->ops->read_w(host, reg);
	399	else
	400	return readw(host->ioaddr + reg);
	401	}
	402
	403	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	404	{
	405	if (unlikely(host->ops->read_b))
	406	return host->ops->read_b(host, reg);
	407	else
	408	return readb(host->ioaddr + reg);
	409	}
	410
	411	#else
	412
	413	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	414	{
	415	writel(val, host->ioaddr + reg);
	416	}
	417
	418	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	419	{
	420	writew(val, host->ioaddr + reg);
	421	}
	422
423	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
424	{
425	writeb(val, host->ioaddr + reg);
426	}
427	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
428	{
429	return readl(host->ioaddr + reg);
430	}
431
432	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
433	{
434	return readw(host->ioaddr + reg);
435	}
436
437	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
438	{
439	return readb(host->ioaddr + reg);
440	}
441	#endif
442
ef1e4eda SG	443	#ifdef CONFIG_BLK
	444	/**
	445	* sdhci_setup_cfg() - Set up the configuration for DWMMC
	446	*
	447	* This is used to set up an SDHCI device when you are using CONFIG_BLK.
	448	*
	449	* This should be called from your MMC driver's probe() method once you have
	450	* the information required.
	451	*
	452	* Generally your driver will have a platform data structure which holds both
	453	* the configuration (struct mmc_config) and the MMC device info (struct mmc).
	454	* For example:
	455	*
	456	* struct msm_sdhc_plat {
	457	* struct mmc_config cfg;
	458	* struct mmc mmc;
	459	* };
	460	*
	461	* ...
	462	*
	463	* Inside U_BOOT_DRIVER():
caa4daa2	464	* .plat_auto = sizeof(struct msm_sdhc_plat),
ef1e4eda SG	465	*
ef1e4eda SG	466	* To access platform data:
c69cda25	467	* struct msm_sdhc_plat *plat = dev_get_plat(dev);
ef1e4eda SG	468	*
	469	* See msm_sdhci.c for an example.
	470	*
	471	* @cfg: Configuration structure to fill in (generally &plat->mmc)
14bed52d	472	* @host: SDHCI host structure
6d0e34bf SH	473	* @f_max: Maximum supported clock frequency in HZ (0 for default)
6d0e34bf SH	474	* @f_min: Minimum supported clock frequency in HZ (0 for default)
ef1e4eda	475	*/
14bed52d	476	int sdhci_setup_cfg(struct mmc_config cfg, struct sdhci_host host,
6d0e34bf	477	u32 f_max, u32 f_min);
ef1e4eda SG	478
	479	/**
	480	* sdhci_bind() - Set up a new MMC block device
	481	*
	482	* This is used to set up an SDHCI block device when you are using CONFIG_BLK.
	483	* It should be called from your driver's bind() method.
	484	*
	485	* See msm_sdhci.c for an example.
	486	*
	487	* @dev: Device to set up
	488	* @mmc: Pointer to mmc structure (normally &plat->mmc)
	489	* @cfg: Empty configuration structure (generally &plat->cfg). This is
	490	* normally all zeroes at this point. The only purpose of passing
	491	* this in is to set mmc->cfg to it.
185f812c	492	* Return: 0 if OK, -ve if the block device could not be created
ef1e4eda SG	493	*/
	494	int sdhci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg);
	495	#else
	496
	497	/**
	498	* add_sdhci() - Add a new SDHCI interface
	499	*
	500	* This is used when you are not using CONFIG_BLK. Convert your driver over!
	501	*
	502	* @host: SDHCI host structure
6d0e34bf SH	503	* @f_max: Maximum supported clock frequency in HZ (0 for default)
6d0e34bf SH	504	* @f_min: Minimum supported clock frequency in HZ (0 for default)
185f812c	505	* Return: 0 if OK, -ve on error
ef1e4eda	506	*/
6d0e34bf	507	int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
ef1e4eda SG	508	#endif /* !CONFIG_BLK */
ef1e4eda SG	509
d1c0a220	510	void sdhci_set_uhs_timing(struct sdhci_host *host);
e7881d85	511	#ifdef CONFIG_DM_MMC
ef1e4eda SG	512	/* Export the operations to drivers */
ef1e4eda SG	513	int sdhci_probe(struct udevice *dev);
3966c7d0	514	int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
43392b55 FA	515
	516	/**
	517	* sdhci_set_control_reg - Set control registers
	518	*
	519	* This is used set up control registers for voltage level and UHS speed
	520	* mode.
	521	*
	522	* @host: SDHCI host structure
	523	*/
	524	void sdhci_set_control_reg(struct sdhci_host *host);
ef1e4eda SG	525	extern const struct dm_mmc_ops sdhci_ops;
	526	#else
	527	#endif
	528
4d6a773b MW	529	struct sdhci_adma_desc *sdhci_adma_init(void);
	530	void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
	531	struct mmc_data *data, dma_addr_t addr);
	532
af62a557	533	#endif /* __SDHCI_HW_H */