[thirdparty/u-boot.git] / include / sdhci.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */
#ifndef __SDHCI_HW_H
#define __SDHCI_HW_H

#include <asm/io.h>
#include <mmc.h>
#include <asm/gpio.h>

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		BIT(0)
#define  SDHCI_TRNS_BLK_CNT_EN	BIT(1)
#define  SDHCI_TRNS_ACMD12	BIT(2)
#define  SDHCI_TRNS_READ	BIT(4)
#define  SDHCI_TRNS_MULTI	BIT(5)

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20
#define  SDHCI_CMD_ABORTCMD	0xC0

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	BIT(0)
#define  SDHCI_DATA_INHIBIT	BIT(1)
#define  SDHCI_DOING_WRITE	BIT(8)
#define  SDHCI_DOING_READ	BIT(9)
#define  SDHCI_SPACE_AVAILABLE	BIT(10)
#define  SDHCI_DATA_AVAILABLE	BIT(11)
#define  SDHCI_CARD_PRESENT	BIT(16)
#define  SDHCI_CARD_STATE_STABLE	BIT(17)
#define  SDHCI_CARD_DETECT_PIN_LEVEL	BIT(18)
#define  SDHCI_WRITE_PROTECT	BIT(19)

#define SDHCI_HOST_CONTROL	0x28
#define  SDHCI_CTRL_LED		BIT(0)
#define  SDHCI_CTRL_4BITBUS	BIT(1)
#define  SDHCI_CTRL_HISPD	BIT(2)
#define  SDHCI_CTRL_DMA_MASK	0x18
#define   SDHCI_CTRL_SDMA	0x00
#define   SDHCI_CTRL_ADMA1	0x08
#define   SDHCI_CTRL_ADMA32	0x10
#define   SDHCI_CTRL_ADMA64	0x18
#define  SDHCI_CTRL_8BITBUS	BIT(5)
#define  SDHCI_CTRL_CD_TEST_INS	BIT(6)
#define  SDHCI_CTRL_CD_TEST	BIT(7)

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B
#define  SDHCI_WAKE_ON_INT	BIT(0)
#define  SDHCI_WAKE_ON_INSERT	BIT(1)
#define  SDHCI_WAKE_ON_REMOVE	BIT(2)

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_DIVIDER_HI_SHIFT	6
#define  SDHCI_DIV_MASK	0xFF
#define  SDHCI_DIV_MASK_LEN	8
#define  SDHCI_DIV_HI_MASK	0x300
#define  SDHCI_PROG_CLOCK_MODE  BIT(5)
#define  SDHCI_CLOCK_CARD_EN	BIT(2)
#define  SDHCI_CLOCK_INT_STABLE	BIT(1)
#define  SDHCI_CLOCK_INT_EN	BIT(0)

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	BIT(0)
#define  SDHCI_INT_DATA_END	BIT(1)
#define  SDHCI_INT_DMA_END	BIT(3)
#define  SDHCI_INT_SPACE_AVAIL	BIT(4)
#define  SDHCI_INT_DATA_AVAIL	BIT(5)
#define  SDHCI_INT_CARD_INSERT	BIT(6)
#define  SDHCI_INT_CARD_REMOVE	BIT(7)
#define  SDHCI_INT_CARD_INT	BIT(8)
#define  SDHCI_INT_ERROR	BIT(15)
#define  SDHCI_INT_TIMEOUT	BIT(16)
#define  SDHCI_INT_CRC		BIT(17)
#define  SDHCI_INT_END_BIT	BIT(18)
#define  SDHCI_INT_INDEX	BIT(19)
#define  SDHCI_INT_DATA_TIMEOUT	BIT(20)
#define  SDHCI_INT_DATA_CRC	BIT(21)
#define  SDHCI_INT_DATA_END_BIT	BIT(22)
#define  SDHCI_INT_BUS_POWER	BIT(23)
#define  SDHCI_INT_ACMD12ERR	BIT(24)
#define  SDHCI_INT_ADMA_ERROR	BIT(25)

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK	((unsigned int)-1)

#define SDHCI_ACMD12_ERR	0x3C

/* 3E-3F reserved */

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_8BIT	BIT(18)
#define  SDHCI_CAN_DO_ADMA2	BIT(19)
#define  SDHCI_CAN_DO_ADMA1	BIT(20)
#define  SDHCI_CAN_DO_HISPD	BIT(21)
#define  SDHCI_CAN_DO_SDMA	BIT(22)
#define  SDHCI_CAN_VDD_330	BIT(24)
#define  SDHCI_CAN_VDD_300	BIT(25)
#define  SDHCI_CAN_VDD_180	BIT(26)
#define  SDHCI_CAN_64BIT	BIT(28)

#define SDHCI_CAPABILITIES_1	0x44
#define  SDHCI_SUPPORT_SDR50	0x00000001
#define  SDHCI_SUPPORT_SDR104	0x00000002
#define  SDHCI_SUPPORT_DDR50	0x00000004
#define  SDHCI_USE_SDR50_TUNING	0x00002000

#define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
#define  SDHCI_CLOCK_MUL_SHIFT	16

#define SDHCI_MAX_CURRENT	0x48

/* 4C-4F reserved for more max current */

#define SDHCI_SET_ACMD12_ERROR	0x50
#define SDHCI_SET_INT_ERROR	0x52

#define SDHCI_ADMA_ERROR	0x54

/* 55-57 reserved */

#define SDHCI_ADMA_ADDRESS	0x58
#define SDHCI_ADMA_ADDRESS_HI	0x5c

/* 60-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0
#define   SDHCI_SPEC_100	0
#define   SDHCI_SPEC_200	1
#define   SDHCI_SPEC_300	2

#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)

/*
 * End of controller registers.
 */

#define SDHCI_MAX_DIV_SPEC_200	256
#define SDHCI_MAX_DIV_SPEC_300	2046

/*
 * quirks
 */
#define SDHCI_QUIRK_32BIT_DMA_ADDR	(1 << 0)
#define SDHCI_QUIRK_REG32_RW		(1 << 1)
#define SDHCI_QUIRK_BROKEN_R1B		(1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT	(1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE	(1 << 4)
/*
 * SDHCI_QUIRK_BROKEN_HISPD_MODE
 * the hardware cannot operate correctly in high-speed mode,
 * this quirk forces the sdhci host-controller to non high-speed mode
 */
#define SDHCI_QUIRK_BROKEN_HISPD_MODE	BIT(5)
#define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
#define SDHCI_QUIRK_USE_WIDE8		(1 << 8)
#define SDHCI_QUIRK_NO_1_8_V		(1 << 9)

/* to make gcc happy */
struct sdhci_host;

/*
 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 */
#define SDHCI_DEFAULT_BOUNDARY_SIZE	(512 * 1024)
#define SDHCI_DEFAULT_BOUNDARY_ARG	(7)
struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	u32	(*read_l)(struct sdhci_host *host, int reg);
	u16	(*read_w)(struct sdhci_host *host, int reg);
	u8	(*read_b)(struct sdhci_host *host, int reg);
	void	(*write_l)(struct sdhci_host *host, u32 val, int reg);
	void	(*write_w)(struct sdhci_host *host, u16 val, int reg);
	void	(*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif
	int	(*get_cd)(struct sdhci_host *host);
	void	(*set_control_reg)(struct sdhci_host *host);
	void	(*set_ios_post)(struct sdhci_host *host);
	void	(*set_clock)(struct sdhci_host *host, u32 div);
	int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
	void (*set_delay)(struct sdhci_host *host);
};

#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
#define ADMA_MAX_LEN	65532
#ifdef CONFIG_DMA_ADDR_T_64BIT
#define ADMA_DESC_LEN	16
#else
#define ADMA_DESC_LEN	8
#endif
#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
			       MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN

#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)

/* Decriptor table defines */
#define ADMA_DESC_ATTR_VALID		BIT(0)
#define ADMA_DESC_ATTR_END		BIT(1)
#define ADMA_DESC_ATTR_INT		BIT(2)
#define ADMA_DESC_ATTR_ACT1		BIT(4)
#define ADMA_DESC_ATTR_ACT2		BIT(5)

#define ADMA_DESC_TRANSFER_DATA		ADMA_DESC_ATTR_ACT2
#define ADMA_DESC_LINK_DESC	(ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)

struct sdhci_adma_desc {
	u8 attr;
	u8 reserved;
	u16 len;
	u32 addr_lo;
#ifdef CONFIG_DMA_ADDR_T_64BIT
	u32 addr_hi;
#endif
} __packed;
#endif
struct sdhci_host {
	const char *name;
	void *ioaddr;
	unsigned int quirks;
	unsigned int host_caps;
	unsigned int version;
	unsigned int max_clk;   /* Maximum Base Clock frequency */
	unsigned int clk_mul;   /* Clock Multiplier value */
	unsigned int clock;
	struct mmc *mmc;
	const struct sdhci_ops *ops;
	int index;

	int bus_width;
	struct gpio_desc pwr_gpio;	/* Power GPIO */
	struct gpio_desc cd_gpio;		/* Card Detect GPIO */

	uint	voltages;

	struct mmc_config cfg;
	dma_addr_t start_addr;
	int flags;
#define USE_SDMA	(0x1 << 0)
#define USE_ADMA	(0x1 << 1)
#define USE_ADMA64	(0x1 << 2)
#define USE_DMA		(USE_SDMA | USE_ADMA | USE_ADMA64)
	dma_addr_t adma_addr;
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
	struct sdhci_adma_desc *adma_desc_table;
	uint desc_slot;
#endif
};

#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	if (unlikely(host->ops->write_l))
		host->ops->write_l(host, val, reg);
	else
		writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	if (unlikely(host->ops->write_w))
		host->ops->write_w(host, val, reg);
	else
		writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	if (unlikely(host->ops->write_b))
		host->ops->write_b(host, val, reg);
	else
		writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_l))
		return host->ops->read_l(host, reg);
	else
		return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_w))
		return host->ops->read_w(host, reg);
	else
		return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_b))
		return host->ops->read_b(host, reg);
	else
		return readb(host->ioaddr + reg);
}

#else

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	writeb(val, host->ioaddr + reg);
}
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	return readb(host->ioaddr + reg);
}
#endif

#ifdef CONFIG_BLK
/**
 * sdhci_setup_cfg() - Set up the configuration for DWMMC
 *
 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
 *
 * This should be called from your MMC driver's probe() method once you have
 * the information required.
 *
 * Generally your driver will have a platform data structure which holds both
 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
 * For example:
 *
 * struct msm_sdhc_plat {
 *	struct mmc_config cfg;
 *	struct mmc mmc;
 * };
 *
 * ...
 *
 * Inside U_BOOT_DRIVER():
 *	.platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
 *
 * To access platform data:
 *	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
 *
 * See msm_sdhci.c for an example.
 *
 * @cfg:	Configuration structure to fill in (generally &plat->mmc)
 * @host:	SDHCI host structure
 * @f_max:	Maximum supported clock frequency in HZ (0 for default)
 * @f_min:	Minimum supported clock frequency in HZ (0 for default)
 */
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
		    u32 f_max, u32 f_min);

/**
 * sdhci_bind() - Set up a new MMC block device
 *
 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
 * It should be called from your driver's bind() method.
 *
 * See msm_sdhci.c for an example.
 *
 * @dev:	Device to set up
 * @mmc:	Pointer to mmc structure (normally &plat->mmc)
 * @cfg:	Empty configuration structure (generally &plat->cfg). This is
 *		normally all zeroes at this point. The only purpose of passing
 *		this in is to set mmc->cfg to it.
 * @return 0 if OK, -ve if the block device could not be created
 */
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
#else

/**
 * add_sdhci() - Add a new SDHCI interface
 *
 * This is used when you are not using CONFIG_BLK. Convert your driver over!
 *
 * @host:	SDHCI host structure
 * @f_max:	Maximum supported clock frequency in HZ (0 for default)
 * @f_min:	Minimum supported clock frequency in HZ (0 for default)
 * @return 0 if OK, -ve on error
 */
int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
#endif /* !CONFIG_BLK */

#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
extern const struct dm_mmc_ops sdhci_ops;
#else
#endif

#endif /* __SDHCI_HW_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
af62a557 LW	2	/*
	3	* Copyright 2011, Marvell Semiconductor Inc.
	4	* Lei Wen <leiwen@marvell.com>
	5	*
af62a557 LW	6	* Back ported to the 8xx platform (from the 8260 platform) by
	7	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	8	*/
	9	#ifndef __SDHCI_HW_H
	10	#define __SDHCI_HW_H
	11
	12	#include <asm/io.h>
6cf1b17c	13	#include <mmc.h>
0347960b	14	#include <asm/gpio.h>
6cf1b17c	15
af62a557 LW	16	/*
	17	* Controller registers
	18	*/
	19
	20	#define SDHCI_DMA_ADDRESS 0x00
	21
	22	#define SDHCI_BLOCK_SIZE 0x04
	23	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
	24
	25	#define SDHCI_BLOCK_COUNT 0x06
	26
	27	#define SDHCI_ARGUMENT 0x08
	28
	29	#define SDHCI_TRANSFER_MODE 0x0C
91914581 JC	30	#define SDHCI_TRNS_DMA BIT(0)
	31	#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
	32	#define SDHCI_TRNS_ACMD12 BIT(2)
	33	#define SDHCI_TRNS_READ BIT(4)
	34	#define SDHCI_TRNS_MULTI BIT(5)
af62a557 LW	35
	36	#define SDHCI_COMMAND 0x0E
	37	#define SDHCI_CMD_RESP_MASK 0x03
	38	#define SDHCI_CMD_CRC 0x08
	39	#define SDHCI_CMD_INDEX 0x10
	40	#define SDHCI_CMD_DATA 0x20
	41	#define SDHCI_CMD_ABORTCMD 0xC0
	42
	43	#define SDHCI_CMD_RESP_NONE 0x00
	44	#define SDHCI_CMD_RESP_LONG 0x01
	45	#define SDHCI_CMD_RESP_SHORT 0x02
	46	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	47
	48	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
	49	#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
	50
	51	#define SDHCI_RESPONSE 0x10
	52
	53	#define SDHCI_BUFFER 0x20
	54
	55	#define SDHCI_PRESENT_STATE 0x24
91914581 JC	56	#define SDHCI_CMD_INHIBIT BIT(0)
	57	#define SDHCI_DATA_INHIBIT BIT(1)
	58	#define SDHCI_DOING_WRITE BIT(8)
	59	#define SDHCI_DOING_READ BIT(9)
	60	#define SDHCI_SPACE_AVAILABLE BIT(10)
	61	#define SDHCI_DATA_AVAILABLE BIT(11)
	62	#define SDHCI_CARD_PRESENT BIT(16)
	63	#define SDHCI_CARD_STATE_STABLE BIT(17)
	64	#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
	65	#define SDHCI_WRITE_PROTECT BIT(19)
af62a557 LW	66
af62a557 LW	67	#define SDHCI_HOST_CONTROL 0x28
91914581 JC	68	#define SDHCI_CTRL_LED BIT(0)
	69	#define SDHCI_CTRL_4BITBUS BIT(1)
	70	#define SDHCI_CTRL_HISPD BIT(2)
af62a557 LW	71	#define SDHCI_CTRL_DMA_MASK 0x18
	72	#define SDHCI_CTRL_SDMA 0x00
	73	#define SDHCI_CTRL_ADMA1 0x08
	74	#define SDHCI_CTRL_ADMA32 0x10
	75	#define SDHCI_CTRL_ADMA64 0x18
91914581 JC	76	#define SDHCI_CTRL_8BITBUS BIT(5)
	77	#define SDHCI_CTRL_CD_TEST_INS BIT(6)
	78	#define SDHCI_CTRL_CD_TEST BIT(7)
af62a557 LW	79
	80	#define SDHCI_POWER_CONTROL 0x29
	81	#define SDHCI_POWER_ON 0x01
	82	#define SDHCI_POWER_180 0x0A
	83	#define SDHCI_POWER_300 0x0C
	84	#define SDHCI_POWER_330 0x0E
	85
	86	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	87
	88	#define SDHCI_WAKE_UP_CONTROL 0x2B
91914581 JC	89	#define SDHCI_WAKE_ON_INT BIT(0)
	90	#define SDHCI_WAKE_ON_INSERT BIT(1)
	91	#define SDHCI_WAKE_ON_REMOVE BIT(2)
af62a557 LW	92
	93	#define SDHCI_CLOCK_CONTROL 0x2C
	94	#define SDHCI_DIVIDER_SHIFT 8
	95	#define SDHCI_DIVIDER_HI_SHIFT 6
	96	#define SDHCI_DIV_MASK 0xFF
	97	#define SDHCI_DIV_MASK_LEN 8
	98	#define SDHCI_DIV_HI_MASK 0x300
91914581 JC	99	#define SDHCI_PROG_CLOCK_MODE BIT(5)
	100	#define SDHCI_CLOCK_CARD_EN BIT(2)
	101	#define SDHCI_CLOCK_INT_STABLE BIT(1)
	102	#define SDHCI_CLOCK_INT_EN BIT(0)
af62a557 LW	103
	104	#define SDHCI_TIMEOUT_CONTROL 0x2E
	105
	106	#define SDHCI_SOFTWARE_RESET 0x2F
	107	#define SDHCI_RESET_ALL 0x01
	108	#define SDHCI_RESET_CMD 0x02
	109	#define SDHCI_RESET_DATA 0x04
	110
	111	#define SDHCI_INT_STATUS 0x30
	112	#define SDHCI_INT_ENABLE 0x34
	113	#define SDHCI_SIGNAL_ENABLE 0x38
91914581 JC	114	#define SDHCI_INT_RESPONSE BIT(0)
	115	#define SDHCI_INT_DATA_END BIT(1)
	116	#define SDHCI_INT_DMA_END BIT(3)
	117	#define SDHCI_INT_SPACE_AVAIL BIT(4)
	118	#define SDHCI_INT_DATA_AVAIL BIT(5)
	119	#define SDHCI_INT_CARD_INSERT BIT(6)
	120	#define SDHCI_INT_CARD_REMOVE BIT(7)
	121	#define SDHCI_INT_CARD_INT BIT(8)
	122	#define SDHCI_INT_ERROR BIT(15)
	123	#define SDHCI_INT_TIMEOUT BIT(16)
	124	#define SDHCI_INT_CRC BIT(17)
	125	#define SDHCI_INT_END_BIT BIT(18)
	126	#define SDHCI_INT_INDEX BIT(19)
	127	#define SDHCI_INT_DATA_TIMEOUT BIT(20)
	128	#define SDHCI_INT_DATA_CRC BIT(21)
	129	#define SDHCI_INT_DATA_END_BIT BIT(22)
	130	#define SDHCI_INT_BUS_POWER BIT(23)
	131	#define SDHCI_INT_ACMD12ERR BIT(24)
	132	#define SDHCI_INT_ADMA_ERROR BIT(25)
af62a557 LW	133
	134	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	135	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	136
	137	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	138	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	139	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
	140	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
	141	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
	142	SDHCI_INT_DATA_END_BIT \| SDHCI_INT_ADMA_ERROR)
	143	#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
	144
	145	#define SDHCI_ACMD12_ERR 0x3C
	146
	147	/* 3E-3F reserved */
	148
	149	#define SDHCI_CAPABILITIES 0x40
	150	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	151	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	152	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
	153	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
	154	#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
	155	#define SDHCI_CLOCK_BASE_SHIFT 8
	156	#define SDHCI_MAX_BLOCK_MASK 0x00030000
	157	#define SDHCI_MAX_BLOCK_SHIFT 16
91914581 JC	158	#define SDHCI_CAN_DO_8BIT BIT(18)
	159	#define SDHCI_CAN_DO_ADMA2 BIT(19)
	160	#define SDHCI_CAN_DO_ADMA1 BIT(20)
	161	#define SDHCI_CAN_DO_HISPD BIT(21)
	162	#define SDHCI_CAN_DO_SDMA BIT(22)
	163	#define SDHCI_CAN_VDD_330 BIT(24)
	164	#define SDHCI_CAN_VDD_300 BIT(25)
	165	#define SDHCI_CAN_VDD_180 BIT(26)
	166	#define SDHCI_CAN_64BIT BIT(28)
af62a557 LW	167
af62a557 LW	168	#define SDHCI_CAPABILITIES_1 0x44
b8e25ef1 SDPP	169	#define SDHCI_SUPPORT_SDR50 0x00000001
	170	#define SDHCI_SUPPORT_SDR104 0x00000002
	171	#define SDHCI_SUPPORT_DDR50 0x00000004
	172	#define SDHCI_USE_SDR50_TUNING 0x00002000
	173
a0d0d86f WY	174	#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
a0d0d86f WY	175	#define SDHCI_CLOCK_MUL_SHIFT 16
af62a557 LW	176
	177	#define SDHCI_MAX_CURRENT 0x48
	178
	179	/* 4C-4F reserved for more max current */
	180
	181	#define SDHCI_SET_ACMD12_ERROR 0x50
	182	#define SDHCI_SET_INT_ERROR 0x52
	183
	184	#define SDHCI_ADMA_ERROR 0x54
	185
	186	/* 55-57 reserved */
	187
	188	#define SDHCI_ADMA_ADDRESS 0x58
37cb626d	189	#define SDHCI_ADMA_ADDRESS_HI 0x5c
af62a557 LW	190
	191	/* 60-FB reserved */
	192
	193	#define SDHCI_SLOT_INT_STATUS 0xFC
	194
	195	#define SDHCI_HOST_VERSION 0xFE
	196	#define SDHCI_VENDOR_VER_MASK 0xFF00
	197	#define SDHCI_VENDOR_VER_SHIFT 8
	198	#define SDHCI_SPEC_VER_MASK 0x00FF
	199	#define SDHCI_SPEC_VER_SHIFT 0
	200	#define SDHCI_SPEC_100 0
	201	#define SDHCI_SPEC_200 1
	202	#define SDHCI_SPEC_300 2
	203
113e5dfc JC	204	#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
113e5dfc JC	205
af62a557 LW	206	/*
	207	* End of controller registers.
	208	*/
	209
	210	#define SDHCI_MAX_DIV_SPEC_200 256
	211	#define SDHCI_MAX_DIV_SPEC_300 2046
	212
	213	/*
	214	* quirks
	215	*/
	216	#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
5af9a569	217	#define SDHCI_QUIRK_REG32_RW (1 << 1)
3a638320	218	#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
236bfecf JC	219	#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
236bfecf JC	220	#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
88a57125 HS	221	/*
	222	* SDHCI_QUIRK_BROKEN_HISPD_MODE
	223	* the hardware cannot operate correctly in high-speed mode,
	224	* this quirk forces the sdhci host-controller to non high-speed mode
	225	*/
	226	#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
13243f2e	227	#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
113e5dfc	228	#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
b8e25ef1	229	#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
af62a557	230
0d2f15f9 LW	231	/* to make gcc happy */
	232	struct sdhci_host;
	233
af62a557 LW	234	/*
	235	* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
	236	*/
	237	#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
	238	#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
	239	struct sdhci_ops {
	240	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
62226b68 JC	241	u32 (read_l)(struct sdhci_host host, int reg);
	242	u16 (read_w)(struct sdhci_host host, int reg);
	243	u8 (read_b)(struct sdhci_host host, int reg);
	244	void (write_l)(struct sdhci_host host, u32 val, int reg);
	245	void (write_w)(struct sdhci_host host, u16 val, int reg);
	246	void (write_b)(struct sdhci_host host, u8 val, int reg);
af62a557	247	#endif
62226b68 JC	248	int (get_cd)(struct sdhci_host host);
62226b68 JC	249	void (set_control_reg)(struct sdhci_host host);
210841c6	250	void (set_ios_post)(struct sdhci_host host);
62226b68	251	void (set_clock)(struct sdhci_host host, u32 div);
2fc3ed5d SDPP	252	int (platform_execute_tuning)(struct mmc host, u8 opcode);
2fc3ed5d SDPP	253	void (set_delay)(struct sdhci_host host);
af62a557 LW	254	};
af62a557 LW	255
37cb626d FA	256	#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
	257	#define ADMA_MAX_LEN 65532
	258	#ifdef CONFIG_DMA_ADDR_T_64BIT
	259	#define ADMA_DESC_LEN 16
	260	#else
	261	#define ADMA_DESC_LEN 8
	262	#endif
	263	#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
	264	MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
	265
	266	#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
	267
	268	/* Decriptor table defines */
	269	#define ADMA_DESC_ATTR_VALID BIT(0)
	270	#define ADMA_DESC_ATTR_END BIT(1)
	271	#define ADMA_DESC_ATTR_INT BIT(2)
	272	#define ADMA_DESC_ATTR_ACT1 BIT(4)
	273	#define ADMA_DESC_ATTR_ACT2 BIT(5)
	274
	275	#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
	276	#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 \| ADMA_DESC_ATTR_ACT2)
	277
	278	struct sdhci_adma_desc {
	279	u8 attr;
	280	u8 reserved;
	281	u16 len;
	282	u32 addr_lo;
	283	#ifdef CONFIG_DMA_ADDR_T_64BIT
	284	u32 addr_hi;
	285	#endif
	286	} __packed;
	287	#endif
af62a557	288	struct sdhci_host {
cacd1d2f	289	const char *name;
af62a557 LW	290	void *ioaddr;
af62a557 LW	291	unsigned int quirks;
236bfecf	292	unsigned int host_caps;
af62a557	293	unsigned int version;
6d0e34bf	294	unsigned int max_clk; /* Maximum Base Clock frequency */
6dffdbc3	295	unsigned int clk_mul; /* Clock Multiplier value */
af62a557	296	unsigned int clock;
6cf1b17c	297	struct mmc *mmc;
af62a557	298	const struct sdhci_ops *ops;
b09ed6e4	299	int index;
236bfecf	300
3577fe8b	301	int bus_width;
0347960b SG	302	struct gpio_desc pwr_gpio; /* Power GPIO */
0347960b SG	303	struct gpio_desc cd_gpio; /* Card Detect GPIO */
3577fe8b	304
236bfecf	305	uint voltages;
93bfd616 PA	306
93bfd616 PA	307	struct mmc_config cfg;
6d6af205 FA	308	dma_addr_t start_addr;
	309	int flags;
	310	#define USE_SDMA (0x1 << 0)
37cb626d FA	311	#define USE_ADMA (0x1 << 1)
	312	#define USE_ADMA64 (0x1 << 2)
	313	#define USE_DMA (USE_SDMA \| USE_ADMA \| USE_ADMA64)
	314	dma_addr_t adma_addr;
	315	#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
	316	struct sdhci_adma_desc *adma_desc_table;
	317	uint desc_slot;
	318	#endif
af62a557 LW	319	};
	320
	321	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	322
	323	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	324	{
	325	if (unlikely(host->ops->write_l))
	326	host->ops->write_l(host, val, reg);
	327	else
	328	writel(val, host->ioaddr + reg);
	329	}
	330
	331	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	332	{
	333	if (unlikely(host->ops->write_w))
	334	host->ops->write_w(host, val, reg);
	335	else
	336	writew(val, host->ioaddr + reg);
	337	}
	338
	339	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	340	{
	341	if (unlikely(host->ops->write_b))
	342	host->ops->write_b(host, val, reg);
	343	else
	344	writeb(val, host->ioaddr + reg);
	345	}
	346
	347	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	348	{
	349	if (unlikely(host->ops->read_l))
	350	return host->ops->read_l(host, reg);
	351	else
	352	return readl(host->ioaddr + reg);
	353	}
	354
	355	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	356	{
	357	if (unlikely(host->ops->read_w))
	358	return host->ops->read_w(host, reg);
	359	else
	360	return readw(host->ioaddr + reg);
	361	}
	362
	363	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	364	{
	365	if (unlikely(host->ops->read_b))
	366	return host->ops->read_b(host, reg);
	367	else
	368	return readb(host->ioaddr + reg);
	369	}
	370
	371	#else
	372
	373	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	374	{
	375	writel(val, host->ioaddr + reg);
	376	}
	377
	378	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	379	{
	380	writew(val, host->ioaddr + reg);
	381	}
	382
383	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
384	{
385	writeb(val, host->ioaddr + reg);
386	}
387	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
388	{
389	return readl(host->ioaddr + reg);
390	}
391
392	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
393	{
394	return readw(host->ioaddr + reg);
395	}
396
397	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
398	{
399	return readb(host->ioaddr + reg);
400	}
401	#endif
402
ef1e4eda SG	403	#ifdef CONFIG_BLK
	404	/**
	405	* sdhci_setup_cfg() - Set up the configuration for DWMMC
	406	*
	407	* This is used to set up an SDHCI device when you are using CONFIG_BLK.
	408	*
	409	* This should be called from your MMC driver's probe() method once you have
	410	* the information required.
	411	*
	412	* Generally your driver will have a platform data structure which holds both
	413	* the configuration (struct mmc_config) and the MMC device info (struct mmc).
	414	* For example:
	415	*
	416	* struct msm_sdhc_plat {
	417	* struct mmc_config cfg;
	418	* struct mmc mmc;
	419	* };
	420	*
	421	* ...
	422	*
	423	* Inside U_BOOT_DRIVER():
	424	* .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
	425	*
	426	* To access platform data:
	427	* struct msm_sdhc_plat *plat = dev_get_platdata(dev);
	428	*
	429	* See msm_sdhci.c for an example.
	430	*
	431	* @cfg: Configuration structure to fill in (generally &plat->mmc)
14bed52d	432	* @host: SDHCI host structure
6d0e34bf SH	433	* @f_max: Maximum supported clock frequency in HZ (0 for default)
6d0e34bf SH	434	* @f_min: Minimum supported clock frequency in HZ (0 for default)
ef1e4eda	435	*/
14bed52d	436	int sdhci_setup_cfg(struct mmc_config cfg, struct sdhci_host host,
6d0e34bf	437	u32 f_max, u32 f_min);
ef1e4eda SG	438
	439	/**
	440	* sdhci_bind() - Set up a new MMC block device
	441	*
	442	* This is used to set up an SDHCI block device when you are using CONFIG_BLK.
	443	* It should be called from your driver's bind() method.
	444	*
	445	* See msm_sdhci.c for an example.
	446	*
	447	* @dev: Device to set up
	448	* @mmc: Pointer to mmc structure (normally &plat->mmc)
	449	* @cfg: Empty configuration structure (generally &plat->cfg). This is
	450	* normally all zeroes at this point. The only purpose of passing
	451	* this in is to set mmc->cfg to it.
	452	* @return 0 if OK, -ve if the block device could not be created
	453	*/
	454	int sdhci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg);
	455	#else
	456
	457	/**
	458	* add_sdhci() - Add a new SDHCI interface
	459	*
	460	* This is used when you are not using CONFIG_BLK. Convert your driver over!
	461	*
	462	* @host: SDHCI host structure
6d0e34bf SH	463	* @f_max: Maximum supported clock frequency in HZ (0 for default)
6d0e34bf SH	464	* @f_min: Minimum supported clock frequency in HZ (0 for default)
ef1e4eda SG	465	* @return 0 if OK, -ve on error
ef1e4eda SG	466	*/
6d0e34bf	467	int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
ef1e4eda SG	468	#endif /* !CONFIG_BLK */
ef1e4eda SG	469
e7881d85	470	#ifdef CONFIG_DM_MMC
ef1e4eda SG	471	/* Export the operations to drivers */
	472	int sdhci_probe(struct udevice *dev);
	473	extern const struct dm_mmc_ops sdhci_ops;
	474	#else
	475	#endif
	476
af62a557	477	#endif /* __SDHCI_HW_H */