projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 067f54c6 MF |
2 | /* |
| 3 | * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> | |
| 4 | * | |
| 5 | * SJA1000 register layout for basic CAN mode | |
| 067f54c6 MF |
6 | */ |
| 7 | ||
| 8 | #ifndef _SJA1000_H_ | |
| 9 | #define _SJA1000_H_ | |
| 10 | ||
| 11 | /* | |
| 12 | * SJA1000 register layout in basic can mode | |
| 13 | */ | |
| 14 | struct sja1000_basic_s { | |
| 15 | u8 cr; | |
| 16 | u8 cmr; | |
| 17 | u8 sr; | |
| 18 | u8 ir; | |
| 19 | u8 ac; | |
| 20 | u8 am; | |
| 21 | u8 btr0; | |
| 22 | u8 btr1; | |
| 23 | u8 oc; | |
| 24 | u8 txb[10]; | |
| 25 | u8 rxb[10]; | |
| 26 | u8 unused; | |
| 27 | u8 cdr; | |
| 28 | }; | |
| 29 | ||
| 30 | /* control register */ | |
| 31 | #define CR_RR 0x01 | |
| 32 | ||
| 33 | /* output control register */ | |
| 34 | #define OC_MODE0 0x01 | |
| 35 | #define OC_MODE1 0x02 | |
| 36 | #define OC_POL0 0x04 | |
| 37 | #define OC_TN0 0x08 | |
| 38 | #define OC_TP0 0x10 | |
| 39 | #define OC_POL1 0x20 | |
| 40 | #define OC_TN1 0x40 | |
| 41 | #define OC_TP1 0x80 | |
| 42 | ||
| 43 | #endif |