]>
Commit | Line | Data |
---|---|---|
c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | #ifndef _SPARTAN2_H_ | |
9 | #define _SPARTAN2_H_ | |
10 | ||
11 | #include <xilinx.h> | |
12 | ||
c609719b WD |
13 | /* Slave Parallel Implementation function table */ |
14 | typedef struct { | |
2df9d5c4 MS |
15 | xilinx_pre_fn pre; |
16 | xilinx_pgm_fn pgm; | |
17 | xilinx_init_fn init; | |
18 | xilinx_err_fn err; | |
19 | xilinx_done_fn done; | |
20 | xilinx_clk_fn clk; | |
21 | xilinx_cs_fn cs; | |
22 | xilinx_wr_fn wr; | |
23 | xilinx_rdata_fn rdata; | |
24 | xilinx_wdata_fn wdata; | |
25 | xilinx_busy_fn busy; | |
26 | xilinx_abort_fn abort; | |
27 | xilinx_post_fn post; | |
b625b9ae | 28 | } xilinx_spartan2_slave_parallel_fns; |
c609719b WD |
29 | |
30 | /* Slave Serial Implementation function table */ | |
31 | typedef struct { | |
2df9d5c4 MS |
32 | xilinx_pre_fn pre; |
33 | xilinx_pgm_fn pgm; | |
34 | xilinx_clk_fn clk; | |
35 | xilinx_init_fn init; | |
36 | xilinx_done_fn done; | |
37 | xilinx_wr_fn wr; | |
38 | xilinx_post_fn post; | |
b625b9ae | 39 | } xilinx_spartan2_slave_serial_fns; |
c609719b | 40 | |
4e9acc16 | 41 | #if defined(CONFIG_FPGA_SPARTAN2) |
14cfc4f3 | 42 | extern struct xilinx_fpga_op spartan2_op; |
4e9acc16 MS |
43 | # define FPGA_SPARTAN2_OPS &spartan2_op |
44 | #else | |
45 | # define FPGA_SPARTAN2_OPS NULL | |
46 | #endif | |
14cfc4f3 | 47 | |
c609719b WD |
48 | /* Device Image Sizes |
49 | *********************************************************************/ | |
50 | /* Spartan-II (2.5V) */ | |
53677ef1 WD |
51 | #define XILINX_XC2S15_SIZE 197728/8 |
52 | #define XILINX_XC2S30_SIZE 336800/8 | |
53 | #define XILINX_XC2S50_SIZE 559232/8 | |
54 | #define XILINX_XC2S100_SIZE 781248/8 | |
55 | #define XILINX_XC2S150_SIZE 1040128/8 | |
56 | #define XILINX_XC2S200_SIZE 1335872/8 | |
c609719b | 57 | |
9dd611b8 WD |
58 | /* Spartan-IIE (1.8V) */ |
59 | #define XILINX_XC2S50E_SIZE 630048/8 | |
60 | #define XILINX_XC2S100E_SIZE 863840/8 | |
61 | #define XILINX_XC2S150E_SIZE 1134496/8 | |
62 | #define XILINX_XC2S200E_SIZE 1442016/8 | |
63 | #define XILINX_XC2S300E_SIZE 1875648/8 | |
64 | ||
c609719b WD |
65 | /* Descriptor Macros |
66 | *********************************************************************/ | |
67 | /* Spartan-II devices */ | |
68 | #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
69 | { xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ |
70 | FPGA_SPARTAN2_OPS } | |
c609719b WD |
71 | |
72 | #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
73 | { xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ |
74 | FPGA_SPARTAN2_OPS } | |
c609719b WD |
75 | |
76 | #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
77 | { xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ |
78 | FPGA_SPARTAN2_OPS } | |
c609719b WD |
79 | |
80 | #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
81 | { xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ |
82 | FPGA_SPARTAN2_OPS } | |
c609719b WD |
83 | |
84 | #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
85 | { xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ |
86 | FPGA_SPARTAN2_OPS } | |
c609719b | 87 | |
3bff4ffa | 88 | #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ |
4e9acc16 MS |
89 | { xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ |
90 | FPGA_SPARTAN2_OPS } | |
3bff4ffa | 91 | |
9dd611b8 | 92 | #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ |
4e9acc16 MS |
93 | { xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ |
94 | FPGA_SPARTAN2_OPS } | |
9dd611b8 WD |
95 | |
96 | #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
97 | { xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ |
98 | FPGA_SPARTAN2_OPS } | |
9dd611b8 WD |
99 | |
100 | #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
101 | { xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ |
102 | FPGA_SPARTAN2_OPS } | |
9dd611b8 WD |
103 | |
104 | #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
105 | { xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ |
106 | FPGA_SPARTAN2_OPS } | |
9dd611b8 WD |
107 | |
108 | #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ | |
4e9acc16 MS |
109 | { xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ |
110 | FPGA_SPARTAN2_OPS } | |
9dd611b8 | 111 | |
c609719b | 112 | #endif /* _SPARTAN2_H_ */ |