[thirdparty/u-boot.git] / include / spartan3.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 */

#ifndef _SPARTAN3_H_
#define _SPARTAN3_H_

#include <xilinx.h>

/* Slave Parallel Implementation function table */
typedef struct {
	xilinx_pre_fn	pre;
	xilinx_pgm_fn	pgm;
	xilinx_init_fn	init;
	xilinx_err_fn	err;
	xilinx_done_fn	done;
	xilinx_clk_fn	clk;
	xilinx_cs_fn	cs;
	xilinx_wr_fn	wr;
	xilinx_rdata_fn	rdata;
	xilinx_wdata_fn	wdata;
	xilinx_busy_fn	busy;
	xilinx_abort_fn	abort;
	xilinx_post_fn	post;
} xilinx_spartan3_slave_parallel_fns;

/* Slave Serial Implementation function table */
typedef struct {
	xilinx_pre_fn	pre;
	xilinx_pgm_fn	pgm;
	xilinx_clk_fn	clk;
	xilinx_init_fn	init;
	xilinx_done_fn	done;
	xilinx_wr_fn	wr;
	xilinx_post_fn	post;
	xilinx_bwr_fn	bwr; /* block write function */
	xilinx_abort_fn abort;
} xilinx_spartan3_slave_serial_fns;

#if defined(CONFIG_FPGA_SPARTAN3)
extern struct xilinx_fpga_op spartan3_op;
# define FPGA_SPARTAN3_OPS	&spartan3_op
#else
# define FPGA_SPARTAN3_OPS	NULL
#endif

/* Device Image Sizes
 *********************************************************************/
/* Spartan-III (1.2V) */
#define XILINX_XC3S50_SIZE	439264/8
#define XILINX_XC3S200_SIZE	1047616/8
#define XILINX_XC3S400_SIZE	1699136/8
#define XILINX_XC3S1000_SIZE	3223488/8
#define XILINX_XC3S1500_SIZE	5214784/8
#define XILINX_XC3S2000_SIZE	7673024/8
#define XILINX_XC3S4000_SIZE	11316864/8
#define XILINX_XC3S5000_SIZE	13271936/8

/* Spartan-3E (v3.4) */
#define	XILINX_XC3S100E_SIZE	581344/8
#define	XILINX_XC3S250E_SIZE	1353728/8
#define	XILINX_XC3S500E_SIZE	2270208/8
#define	XILINX_XC3S1200E_SIZE	3841184/8
#define	XILINX_XC3S1600E_SIZE	5969696/8

/*
 * Spartan-6 : the Spartan-6 family can be programmed
 * exactly as the Spartan-3
 */
#define XILINK_XC6SLX4_SIZE	(3713568/8)

/* Descriptor Macros
 *********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
	FPGA_SPARTAN3_OPS }

#endif /* _SPARTAN3_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
875c7893 WD	2	/*
	3	* (C) Copyright 2002
	4	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
875c7893 WD	5	*/
	6
	7	#ifndef _SPARTAN3_H_
	8	#define _SPARTAN3_H_
	9
	10	#include <xilinx.h>
	11
875c7893 WD	12	/* Slave Parallel Implementation function table */
875c7893 WD	13	typedef struct {
2df9d5c4 MS	14	xilinx_pre_fn pre;
	15	xilinx_pgm_fn pgm;
	16	xilinx_init_fn init;
	17	xilinx_err_fn err;
	18	xilinx_done_fn done;
	19	xilinx_clk_fn clk;
	20	xilinx_cs_fn cs;
	21	xilinx_wr_fn wr;
	22	xilinx_rdata_fn rdata;
	23	xilinx_wdata_fn wdata;
	24	xilinx_busy_fn busy;
	25	xilinx_abort_fn abort;
	26	xilinx_post_fn post;
2a6e3869	27	} xilinx_spartan3_slave_parallel_fns;
875c7893 WD	28
	29	/* Slave Serial Implementation function table */
	30	typedef struct {
2df9d5c4 MS	31	xilinx_pre_fn pre;
	32	xilinx_pgm_fn pgm;
	33	xilinx_clk_fn clk;
	34	xilinx_init_fn init;
	35	xilinx_done_fn done;
	36	xilinx_wr_fn wr;
	37	xilinx_post_fn post;
	38	xilinx_bwr_fn bwr; /* block write function */
	39	xilinx_abort_fn abort;
2a6e3869	40	} xilinx_spartan3_slave_serial_fns;
875c7893	41
a99a06cb	42	#if defined(CONFIG_FPGA_SPARTAN3)
14cfc4f3	43	extern struct xilinx_fpga_op spartan3_op;
a99a06cb MS	44	# define FPGA_SPARTAN3_OPS &spartan3_op
	45	#else
	46	# define FPGA_SPARTAN3_OPS NULL
	47	#endif
14cfc4f3	48
875c7893 WD	49	/* Device Image Sizes
	50	*********************************************************************/
	51	/* Spartan-III (1.2V) */
53677ef1 WD	52	#define XILINX_XC3S50_SIZE 439264/8
	53	#define XILINX_XC3S200_SIZE 1047616/8
	54	#define XILINX_XC3S400_SIZE 1699136/8
	55	#define XILINX_XC3S1000_SIZE 3223488/8
	56	#define XILINX_XC3S1500_SIZE 5214784/8
	57	#define XILINX_XC3S2000_SIZE 7673024/8
	58	#define XILINX_XC3S4000_SIZE 11316864/8
	59	#define XILINX_XC3S5000_SIZE 13271936/8
875c7893	60
923efd28 BA	61	/* Spartan-3E (v3.4) */
	62	#define XILINX_XC3S100E_SIZE 581344/8
	63	#define XILINX_XC3S250E_SIZE 1353728/8
	64	#define XILINX_XC3S500E_SIZE 2270208/8
	65	#define XILINX_XC3S1200E_SIZE 3841184/8
	66	#define XILINX_XC3S1600E_SIZE 5969696/8
	67
28cdc1c8 SB	68	/*
	69	* Spartan-6 : the Spartan-6 family can be programmed
	70	* exactly as the Spartan-3
	71	*/
	72	#define XILINK_XC6SLX4_SIZE (3713568/8)
	73
875c7893 WD	74	/* Descriptor Macros
875c7893 WD	75	*********************************************************************/
3bff4ffa	76	/* Spartan-III devices */
875c7893	77	#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
a99a06cb MS	78	{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
a99a06cb MS	79	FPGA_SPARTAN3_OPS }
875c7893 WD	80
875c7893 WD	81	#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
a99a06cb MS	82	{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
a99a06cb MS	83	FPGA_SPARTAN3_OPS }
875c7893 WD	84
875c7893 WD	85	#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
a99a06cb MS	86	{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
a99a06cb MS	87	FPGA_SPARTAN3_OPS }
875c7893 WD	88
875c7893 WD	89	#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
a99a06cb MS	90	{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
a99a06cb MS	91	FPGA_SPARTAN3_OPS }
875c7893 WD	92
875c7893 WD	93	#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
a99a06cb MS	94	{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
a99a06cb MS	95	FPGA_SPARTAN3_OPS }
875c7893 WD	96
875c7893 WD	97	#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
a99a06cb MS	98	{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
a99a06cb MS	99	FPGA_SPARTAN3_OPS }
875c7893 WD	100
875c7893 WD	101	#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
a99a06cb MS	102	{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
a99a06cb MS	103	FPGA_SPARTAN3_OPS }
875c7893 WD	104
875c7893 WD	105	#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
a99a06cb MS	106	{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
a99a06cb MS	107	FPGA_SPARTAN3_OPS }
875c7893	108
923efd28 BA	109	/* Spartan-3E devices */
923efd28 BA	110	#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
a99a06cb MS	111	{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
a99a06cb MS	112	FPGA_SPARTAN3_OPS }
923efd28 BA	113
923efd28 BA	114	#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
a99a06cb MS	115	{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
a99a06cb MS	116	FPGA_SPARTAN3_OPS }
923efd28 BA	117
923efd28 BA	118	#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
a99a06cb MS	119	{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
a99a06cb MS	120	FPGA_SPARTAN3_OPS }
923efd28 BA	121
923efd28 BA	122	#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
14cfc4f3	123	{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
a99a06cb	124	FPGA_SPARTAN3_OPS }
923efd28 BA	125
923efd28 BA	126	#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
14cfc4f3	127	{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
a99a06cb	128	FPGA_SPARTAN3_OPS }
923efd28	129
28cdc1c8	130	#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
a99a06cb MS	131	{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
a99a06cb MS	132	FPGA_SPARTAN3_OPS }
28cdc1c8	133
875c7893	134	#endif /* _SPARTAN3_H_ */