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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
fe1b4db0 IC |
2 | /* |
3 | * (C) Copyright 2007-2012 | |
4 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
5 | * Tom Cubie <tangliang@allwinnertech.com> | |
20b78c55 AP |
6 | * |
7 | * Definitions that are shared between the Allwinner pinctrl and GPIO drivers, | |
8 | * also used by some non-DM SPL code directly. | |
fe1b4db0 IC |
9 | */ |
10 | ||
11 | #ifndef _SUNXI_GPIO_H | |
12 | #define _SUNXI_GPIO_H | |
13 | ||
14 | #include <linux/types.h> | |
1da48c99 AP |
15 | |
16 | #if defined(CONFIG_MACH_SUN9I) | |
17 | #define SUNXI_PIO_BASE 0x06000800 | |
18 | #define SUNXI_R_PIO_BASE 0x08002c00 | |
19 | #elif defined(CONFIG_SUN50I_GEN_H6) | |
20 | #define SUNXI_PIO_BASE 0x0300b000 | |
21 | #define SUNXI_R_PIO_BASE 0x07022000 | |
4a9e89a3 AP |
22 | #elif defined(CONFIG_SUNXI_GEN_NCAT2) |
23 | #define SUNXI_PIO_BASE 0x02000000 | |
24 | #define SUNXI_R_PIO_BASE 0x07022000 | |
1da48c99 AP |
25 | #else |
26 | #define SUNXI_PIO_BASE 0x01c20800 | |
27 | #define SUNXI_R_PIO_BASE 0x01f02c00 | |
28 | #endif | |
fe1b4db0 IC |
29 | |
30 | /* | |
31 | * sunxi has 9 banks of gpio, they are: | |
32 | * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 | |
33 | * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 | |
34 | * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 | |
35 | */ | |
36 | ||
37 | #define SUNXI_GPIO_A 0 | |
38 | #define SUNXI_GPIO_B 1 | |
39 | #define SUNXI_GPIO_C 2 | |
40 | #define SUNXI_GPIO_D 3 | |
41 | #define SUNXI_GPIO_E 4 | |
42 | #define SUNXI_GPIO_F 5 | |
43 | #define SUNXI_GPIO_G 6 | |
44 | #define SUNXI_GPIO_H 7 | |
45 | #define SUNXI_GPIO_I 8 | |
e373aad3 | 46 | |
e373aad3 HG |
47 | /* |
48 | * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) | |
49 | * at a different register offset. | |
50 | * | |
51 | * sun6i has 2 banks: | |
52 | * PL0 - PL8 | PM0 - PM7 | |
53 | * | |
54 | * sun8i has 1 bank: | |
55 | * PL0 - PL11 | |
d35488c7 HG |
56 | * |
57 | * sun9i has 3 banks: | |
58 | * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 | |
e373aad3 HG |
59 | */ |
60 | #define SUNXI_GPIO_L 11 | |
61 | #define SUNXI_GPIO_M 12 | |
d35488c7 | 62 | #define SUNXI_GPIO_N 13 |
e373aad3 | 63 | |
5f19c930 IZ |
64 | #define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 |
65 | #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 | |
66 | ||
8fe8ff34 | 67 | #define SUNXI_GPIOS_PER_BANK 32 |
fe1b4db0 IC |
68 | |
69 | #define SUNXI_GPIO_NEXT(__gpio) \ | |
8fe8ff34 | 70 | ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) |
fe1b4db0 IC |
71 | |
72 | enum sunxi_gpio_number { | |
73 | SUNXI_GPIO_A_START = 0, | |
74 | SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), | |
75 | SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), | |
76 | SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), | |
77 | SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), | |
78 | SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), | |
79 | SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), | |
80 | SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), | |
81 | SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), | |
e373aad3 HG |
82 | SUNXI_GPIO_L_START = 352, |
83 | SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), | |
d35488c7 | 84 | SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), |
6c727e09 | 85 | SUNXI_GPIO_AXP0_START = 1024, |
fe1b4db0 IC |
86 | }; |
87 | ||
88 | /* SUNXI GPIO number definitions */ | |
89 | #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) | |
90 | #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) | |
91 | #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) | |
92 | #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) | |
93 | #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) | |
94 | #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) | |
95 | #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) | |
96 | #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) | |
97 | #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) | |
e373aad3 HG |
98 | #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) |
99 | #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) | |
d35488c7 | 100 | #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) |
fe1b4db0 | 101 | |
6c727e09 HG |
102 | #define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) |
103 | ||
fe1b4db0 IC |
104 | /* GPIO pin function config */ |
105 | #define SUNXI_GPIO_INPUT 0 | |
106 | #define SUNXI_GPIO_OUTPUT 1 | |
107 | ||
1c27b7dc | 108 | #define SUN8I_H3_GPA_UART0 2 |
482c1ccd | 109 | #define SUN8I_H3_GPA_UART2 2 |
fe1b4db0 | 110 | |
421c98d7 | 111 | #define SUN4I_GPB_PWM 2 |
6c739c5d PK |
112 | #define SUN4I_GPB_TWI0 2 |
113 | #define SUN4I_GPB_TWI1 2 | |
114 | #define SUN5I_GPB_TWI1 2 | |
8c51c652 | 115 | #define SUN8I_V3S_GPB_TWI0 2 |
487b3277 PK |
116 | #define SUN4I_GPB_UART0 2 |
117 | #define SUN5I_GPB_UART0 2 | |
5cd83b11 | 118 | #define SUN8I_GPB_UART2 2 |
e506889c | 119 | #define SUN8I_A33_GPB_UART0 3 |
d5a3357f | 120 | #define SUN8I_A83T_GPB_UART0 2 |
c199489f | 121 | #define SUN8I_V3S_GPB_UART0 3 |
d96ebc46 | 122 | #define SUN50I_GPB_UART0 4 |
fe1b4db0 | 123 | |
ad008299 | 124 | #define SUNXI_GPC_NAND 2 |
19e99fb4 | 125 | #define SUNXI_GPC_SPI0 3 |
487b3277 | 126 | #define SUNXI_GPC_SDC2 3 |
8deacca9 | 127 | #define SUN6I_GPC_SDC3 4 |
19e99fb4 | 128 | #define SUN50I_GPC_SPI0 4 |
0dcdaff8 | 129 | #define SUNIV_GPC_SPI0 2 |
fe1b4db0 | 130 | |
487b3277 PK |
131 | #define SUNXI_GPD_LCD0 2 |
132 | #define SUNXI_GPD_LVDS0 3 | |
fe1b4db0 | 133 | |
5d35f0f2 | 134 | #define SUNIV_GPE_UART0 5 |
8deacca9 | 135 | |
487b3277 PK |
136 | #define SUNXI_GPF_SDC0 2 |
137 | #define SUNXI_GPF_UART0 4 | |
138 | #define SUN8I_GPF_UART0 3 | |
fe1b4db0 | 139 | |
8deacca9 | 140 | #define SUN4I_GPG_SDC1 4 |
487b3277 | 141 | #define SUN5I_GPG_SDC1 2 |
8deacca9 PK |
142 | #define SUN6I_GPG_SDC1 2 |
143 | #define SUN8I_GPG_SDC1 2 | |
7f4e294b | 144 | #define SUN8I_GPG_UART1 2 |
487b3277 | 145 | #define SUN5I_GPG_UART1 4 |
2dae800f | 146 | |
421c98d7 HG |
147 | #define SUN6I_GPH_PWM 2 |
148 | #define SUN8I_GPH_PWM 2 | |
8deacca9 | 149 | #define SUN4I_GPH_SDC1 5 |
6c739c5d PK |
150 | #define SUN6I_GPH_TWI0 2 |
151 | #define SUN8I_GPH_TWI0 2 | |
da1ae590 | 152 | #define SUN50I_GPH_TWI0 2 |
6c739c5d PK |
153 | #define SUN6I_GPH_TWI1 2 |
154 | #define SUN8I_GPH_TWI1 2 | |
da1ae590 | 155 | #define SUN50I_GPH_TWI1 2 |
487b3277 | 156 | #define SUN6I_GPH_UART0 2 |
1871a8ca | 157 | #define SUN9I_GPH_UART0 2 |
7f51a402 | 158 | #define SUN50I_H6_GPH_UART0 2 |
c13d98b7 | 159 | #define SUN50I_H616_GPH_UART0 2 |
fe1b4db0 | 160 | |
8deacca9 | 161 | #define SUNXI_GPI_SDC3 2 |
fe1b4db0 | 162 | |
ce881076 HG |
163 | #define SUN6I_GPL0_R_P2WI_SCK 3 |
164 | #define SUN6I_GPL1_R_P2WI_SDA 3 | |
3b10e6eb | 165 | |
487b3277 | 166 | #define SUN8I_GPL_R_RSB 2 |
9d082687 JW |
167 | #define SUN8I_H3_GPL_R_TWI 2 |
168 | #define SUN8I_A23_GPL_R_TWI 3 | |
487b3277 | 169 | #define SUN8I_GPL_R_UART 2 |
31a4ac4d | 170 | #define SUN50I_GPL_R_TWI 2 |
d0b07c15 | 171 | #define SUN50I_H616_GPL_R_TWI 3 |
c757a50b | 172 | |
487b3277 | 173 | #define SUN9I_GPN_R_RSB 3 |
d35488c7 | 174 | |
452369cd AP |
175 | #ifdef CONFIG_SUNXI_NEW_PINCTRL |
176 | #define SUNXI_PINCTRL_BANK_SIZE 0x30 | |
177 | #define SUNXI_GPIO_DISABLE 0xf | |
178 | #else | |
179 | #define SUNXI_PINCTRL_BANK_SIZE 0x24 | |
180 | #define SUNXI_GPIO_DISABLE 0x7 | |
181 | #endif | |
182 | ||
fe1b4db0 IC |
183 | /* GPIO pin pull-up/down config */ |
184 | #define SUNXI_GPIO_PULL_DISABLE 0 | |
185 | #define SUNXI_GPIO_PULL_UP 1 | |
186 | #define SUNXI_GPIO_PULL_DOWN 2 | |
187 | ||
f7c7ab63 | 188 | /* Virtual AXP0 GPIOs */ |
f9b7a04b | 189 | #define SUNXI_GPIO_AXP0_PREFIX "AXP0-" |
f9b7a04b HG |
190 | #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 |
191 | #define SUNXI_GPIO_AXP0_GPIO_COUNT 6 | |
f7c7ab63 | 192 | |
b799eabc | 193 | struct sunxi_gpio_plat { |
30097ee3 | 194 | void *regs; |
b799eabc SH |
195 | char bank_name[3]; |
196 | }; | |
197 | ||
20b78c55 | 198 | /* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */ |
30097ee3 | 199 | void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); |
bf38891a | 200 | void sunxi_gpio_set_cfgpin(u32 pin, u32 val); |
30097ee3 | 201 | int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); |
fe1b4db0 | 202 | int sunxi_gpio_get_cfgpin(u32 pin); |
ac5397a2 | 203 | void sunxi_gpio_set_drv(u32 pin, u32 val); |
30097ee3 | 204 | void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); |
ac5397a2 | 205 | void sunxi_gpio_set_pull(u32 pin, u32 val); |
30097ee3 | 206 | void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); |
abce2c62 | 207 | int sunxi_name_to_gpio(const char *name); |
fe1b4db0 | 208 | |
2fcf033d HG |
209 | #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO |
210 | int axp_gpio_init(void); | |
211 | #else | |
212 | static inline int axp_gpio_init(void) { return 0; } | |
213 | #endif | |
214 | ||
fe1b4db0 | 215 | #endif /* _SUNXI_GPIO_H */ |