[thirdparty/u-boot.git] / include / synopsys / dwcddr21mctl.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2011 Andes Technology Corp
 * Macpaul Lin <macpaul@andestech.com>
 */

/*
 * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
 */
#ifndef __DWCDDR21MCTL_H
#define __DWCDDR21MCTL_H

#ifndef __ASSEMBLY__
struct dwcddr21mctl {
	unsigned int	ccr;		/* Controller Configuration */
	unsigned int	dcr;		/* DRAM Configuration */
	unsigned int	iocr;		/* I/O Configuration */
	unsigned int	csr;		/* Controller Status */
	unsigned int	drr;		/* DRAM refresh */
	unsigned int	tpr0;		/* SDRAM Timing Parameters 0 */
	unsigned int	tpr1;		/* SDRAM Timing Parameters 1 */
	unsigned int	tpr2;		/* SDRAM Timing Parameters 2 */
	unsigned int	gdllcr;		/* Global DLL Control */
	unsigned int	dllcr[10];	/* DLL Control */
	unsigned int	rslr[4];	/* Rank System Lantency */
	unsigned int	rdgr[4];	/* Rank DQS Gating */
	unsigned int	dqtr[9];	/* DQ Timing */
	unsigned int	dqstr;		/* DQS Timing */
	unsigned int	dqsbtr;		/* DQS_b Timing */
	unsigned int	odtcr;		/* ODT Configuration */
	unsigned int	dtr[2];		/* Data Training */
	unsigned int	dtar;		/* Data Training Address */
	unsigned int	rsved[82];	/* Reserved */
	unsigned int	mr;		/* Mode Register */
	unsigned int	emr;		/* Extended Mode Register */
	unsigned int	emr2;		/* Extended Mode Register 2 */
	unsigned int	emr3;		/* Extended Mode Register 3 */
	unsigned int	hpcr[32];	/* Host Port Configurarion */
	unsigned int	pqcr[8];	/* Priority Queue Configuration */
	unsigned int	mmgcr;		/* Memory Manager General Config */
};
#endif /* __ASSEMBLY__ */

/*
 * Control Configuration Register
 */
#define DWCDDR21MCTL_CCR_ECCEN(x)	((x) << 0)
#define DWCDDR21MCTL_CCR_NOMRWR(x)	((x) << 1)
#define DWCDDR21MCTL_CCR_HOSTEN(x)	((x) << 2)
#define DWCDDR21MCTL_CCR_XBISC(x)	((x) << 3)
#define DWCDDR21MCTL_CCR_NOAPD(x)	((x) << 4)
#define DWCDDR21MCTL_CCR_RRB(x)		((x) << 13)
#define DWCDDR21MCTL_CCR_DQSCFG(x)	((x) << 14)
#define DWCDDR21MCTL_CCR_DFTLM(x)	(((x) & 0x3) << 15)
#define DWCDDR21MCTL_CCR_DFTCMP(x)	((x) << 17)
#define DWCDDR21MCTL_CCR_FLUSH(x)	((x) << 27)
#define DWCDDR21MCTL_CCR_ITMRST(x)	((x) << 28)
#define DWCDDR21MCTL_CCR_IB(x)		((x) << 29)
#define DWCDDR21MCTL_CCR_DTT(x)		((x) << 30)
#define DWCDDR21MCTL_CCR_IT(x)		((x) << 31)

/*
 * DRAM Configuration Register
 */
#define DWCDDR21MCTL_DCR_DDRMD(x)	((x) << 0)
#define DWCDDR21MCTL_DCR_DIO(x)		(((x) & 0x3) << 1)
#define DWCDDR21MCTL_DCR_DSIZE(x)	(((x) & 0x7) << 3)
#define DWCDDR21MCTL_DCR_SIO(x)		(((x) & 0x7) << 6)
#define DWCDDR21MCTL_DCR_PIO(x)		((x) << 9)
#define DWCDDR21MCTL_DCR_RANKS(x)	(((x) & 0x3) << 10)
#define DWCDDR21MCTL_DCR_RNKALL(x)	((x) << 12)
#define DWCDDR21MCTL_DCR_AMAP(x)	(((x) & 0x3) << 13)
#define DWCDDR21MCTL_DCR_RANK(x)	(((x) & 0x3) << 25)
#define DWCDDR21MCTL_DCR_CMD(x)		(((x) & 0xf) << 27)
#define DWCDDR21MCTL_DCR_EXE(x)		((x) << 31)

/*
 * I/O Configuration Register
 */
#define DWCDDR21MCTL_IOCR_RTT(x)	(((x) & 0xf) << 0)
#define DWCDDR21MCTL_IOCR_DS(x)		(((x) & 0xf) << 4)
#define DWCDDR21MCTL_IOCR_TESTEN(x)	((x) << 0x8)
#define DWCDDR21MCTL_IOCR_RTTOH(x)	(((x) & 0x7) << 26)
#define DWCDDR21MCTL_IOCR_RTTOE(x)	((x) << 29)
#define DWCDDR21MCTL_IOCR_DQRTT(x)	((x) << 30)
#define DWCDDR21MCTL_IOCR_DQSRTT(x)	((x) << 31)

/*
 * Controller Status Register
 */
#define DWCDDR21MCTL_CSR_DRIFT(x)	(((x) & 0x3ff) << 0)
#define DWCDDR21MCTL_CSR_DFTERR(x)	((x) << 18)
#define DWCDDR21MCTL_CSR_ECCERR(x)	((x) << 19)
#define DWCDDR21MCTL_CSR_DTERR(x)	((x) << 20)
#define DWCDDR21MCTL_CSR_DTIERR(x)	((x) << 21)
#define DWCDDR21MCTL_CSR_ECCSEC(x)	((x) << 22)

/*
 * DRAM Refresh Register
 */
#define DWCDDR21MCTL_DRR_TRFC(x)	(((x) & 0xff) << 0)
#define DWCDDR21MCTL_DRR_TRFPRD(x)	(((x) & 0xffff) << 8)
#define DWCDDR21MCTL_DRR_RFBURST(x)	(((x) & 0xf) << 24)
#define DWCDDR21MCTL_DRR_RD(x)		((x) << 31)

/*
 * SDRAM Timing Parameters Register 0
 */
#define DWCDDR21MCTL_TPR0_TMRD(x)	(((x) & 0x3) << 0)
#define DWCDDR21MCTL_TPR0_TRTP(x)	(((x) & 0x7) << 2)
#define DWCDDR21MCTL_TPR0_TWTR(x)	(((x) & 0x7) << 5)
#define DWCDDR21MCTL_TPR0_TRP(x)	(((x) & 0xf) << 8)
#define DWCDDR21MCTL_TPR0_TRCD(x)	(((x) & 0xf) << 12)
#define DWCDDR21MCTL_TPR0_TRAS(x)	(((x) & 0x1f) << 16)
#define DWCDDR21MCTL_TPR0_TRRD(x)	(((x) & 0xf) << 21)
#define DWCDDR21MCTL_TPR0_TRC(x)	(((x) & 0x3f) << 25)
#define DWCDDR21MCTL_TPR0_TCCD(x)	((x) << 31)

/*
 * SDRAM Timing Parameters Register 1
 */
#define DWCDDR21MCTL_TPR1_TAOND(x)	(((x) & 0x3) << 0)
#define DWCDDR21MCTL_TPR1_TRTW(x)	((x) << 2)
#define DWCDDR21MCTL_TPR1_TFAW(x)	(((x) & 0x3f) << 3)
#define DWCDDR21MCTL_TPR1_TRNKRTR(x)	(((x) & 0x3) << 12)
#define DWCDDR21MCTL_TPR1_TRNKWTW(x)	(((x) & 0x3) << 14)
#define DWCDDR21MCTL_TPR1_XCL(x)	(((x) & 0xf) << 23)
#define DWCDDR21MCTL_TPR1_XWR(x)	(((x) & 0xf) << 27)
#define DWCDDR21MCTL_TPR1_XTP(x)	((x) << 31)

/*
 * SDRAM Timing Parameters Register 2
 */
#define DWCDDR21MCTL_TPR2_TXS(x)	(((x) & 0x3ff) << 0)
#define DWCDDR21MCTL_TPR2_TXP(x)	(((x) & 0x1f) << 10)
#define DWCDDR21MCTL_TPR2_TCKE(x)	(((x) & 0xf) << 15)

/*
 * Global DLL Control Register
 */
#define DWCDDR21MCTL_GDLLCR_DRES(x)	(((x) & 0x3) << 0)
#define DWCDDR21MCTL_GDLLCR_IPUMP(x)	(((x) & 0x7) << 2)
#define DWCDDR21MCTL_GDLLCR_TESTEN(x)	((x) << 5)
#define DWCDDR21MCTL_GDLLCR_DTC(x)	(((x) & 0x7) << 6)
#define DWCDDR21MCTL_GDLLCR_ATC(x)	(((x) & 0x3) << 9)
#define DWCDDR21MCTL_GDLLCR_TESTSW(x)	((x) << 11)
#define DWCDDR21MCTL_GDLLCR_MBIAS(x)	(((x) & 0xff) << 12)
#define DWCDDR21MCTL_GDLLCR_SBIAS(x)	(((x) & 0xff) << 20)
#define DWCDDR21MCTL_GDLLCR_LOCKDET(x)	((x) << 29)

/*
 * DLL Control Register 0-9
 */
#define DWCDDR21MCTL_DLLCR_SFBDLY(x)	(((x) & 0x7) << 0)
#define DWCDDR21MCTL_DLLCR_SFWDLY(x)	(((x) & 0x7) << 3)
#define DWCDDR21MCTL_DLLCR_MFBDLY(x)	(((x) & 0x7) << 6)
#define DWCDDR21MCTL_DLLCR_MFWDLY(x)	(((x) & 0x7) << 9)
#define DWCDDR21MCTL_DLLCR_SSTART(x)	(((x) & 0x3) << 12)
#define DWCDDR21MCTL_DLLCR_PHASE(x)	(((x) & 0xf) << 14)
#define DWCDDR21MCTL_DLLCR_ATESTEN(x)	((x) << 18)
#define DWCDDR21MCTL_DLLCR_DRSVD(x)	((x) << 19)
#define DWCDDR21MCTL_DLLCR_DD(x)	((x) << 31)

/*
 * Rank System Lantency Register
 */
#define DWCDDR21MCTL_RSLR_SL0(x)	(((x) & 0x7) << 0)
#define DWCDDR21MCTL_RSLR_SL1(x)	(((x) & 0x7) << 3)
#define DWCDDR21MCTL_RSLR_SL2(x)	(((x) & 0x7) << 6)
#define DWCDDR21MCTL_RSLR_SL3(x)	(((x) & 0x7) << 9)
#define DWCDDR21MCTL_RSLR_SL4(x)	(((x) & 0x7) << 12)
#define DWCDDR21MCTL_RSLR_SL5(x)	(((x) & 0x7) << 15)
#define DWCDDR21MCTL_RSLR_SL6(x)	(((x) & 0x7) << 18)
#define DWCDDR21MCTL_RSLR_SL7(x)	(((x) & 0x7) << 21)
#define DWCDDR21MCTL_RSLR_SL8(x)	(((x) & 0x7) << 24)

/*
 * Rank DQS Gating Register
 */
#define DWCDDR21MCTL_RDGR_DQSSEL0(x)	(((x) & 0x3) << 0)
#define DWCDDR21MCTL_RDGR_DQSSEL1(x)	(((x) & 0x3) << 2)
#define DWCDDR21MCTL_RDGR_DQSSEL2(x)	(((x) & 0x3) << 4)
#define DWCDDR21MCTL_RDGR_DQSSEL3(x)	(((x) & 0x3) << 6)
#define DWCDDR21MCTL_RDGR_DQSSEL4(x)	(((x) & 0x3) << 8)
#define DWCDDR21MCTL_RDGR_DQSSEL5(x)	(((x) & 0x3) << 10)
#define DWCDDR21MCTL_RDGR_DQSSEL6(x)	(((x) & 0x3) << 12)
#define DWCDDR21MCTL_RDGR_DQSSEL7(x)	(((x) & 0x3) << 14)
#define DWCDDR21MCTL_RDGR_DQSSEL8(x)	(((x) & 0x3) << 16)

/*
 * DQ Timing Register
 */
#define DWCDDR21MCTL_DQTR_DQDLY0(x)	(((x) & 0xf) << 0)
#define DWCDDR21MCTL_DQTR_DQDLY1(x)	(((x) & 0xf) << 4)
#define DWCDDR21MCTL_DQTR_DQDLY2(x)	(((x) & 0xf) << 8)
#define DWCDDR21MCTL_DQTR_DQDLY3(x)	(((x) & 0xf) << 12)
#define DWCDDR21MCTL_DQTR_DQDLY4(x)	(((x) & 0xf) << 16)
#define DWCDDR21MCTL_DQTR_DQDLY5(x)	(((x) & 0xf) << 20)
#define DWCDDR21MCTL_DQTR_DQDLY6(x)	(((x) & 0xf) << 24)
#define DWCDDR21MCTL_DQTR_DQDLY7(x)	(((x) & 0xf) << 28)

/*
 * DQS Timing Register
 */
#define DWCDDR21MCTL_DQSTR_DQSDLY0(x)	(((x) & 0x7) << 0)
#define DWCDDR21MCTL_DQSTR_DQSDLY1(x)	(((x) & 0x7) << 3)
#define DWCDDR21MCTL_DQSTR_DQSDLY2(x)	(((x) & 0x7) << 6)
#define DWCDDR21MCTL_DQSTR_DQSDLY3(x)	(((x) & 0x7) << 9)
#define DWCDDR21MCTL_DQSTR_DQSDLY4(x)	(((x) & 0x7) << 12)
#define DWCDDR21MCTL_DQSTR_DQSDLY5(x)	(((x) & 0x7) << 15)
#define DWCDDR21MCTL_DQSTR_DQSDLY6(x)	(((x) & 0x7) << 18)
#define DWCDDR21MCTL_DQSTR_DQSDLY7(x)	(((x) & 0x7) << 21)
#define DWCDDR21MCTL_DQSTR_DQSDLY8(x)	(((x) & 0x7) << 24)

/*
 * DQS_b (DQSBTR) Timing Register
 */
#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x)	(((x) & 0x7) << 0)
#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x)	(((x) & 0x7) << 3)
#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x)	(((x) & 0x7) << 6)
#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x)	(((x) & 0x7) << 9)
#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x)	(((x) & 0x7) << 12)
#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x)	(((x) & 0x7) << 15)
#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x)	(((x) & 0x7) << 18)
#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x)	(((x) & 0x7) << 21)
#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x)	(((x) & 0x7) << 24)

/*
 * ODT Configuration Register
 */
#define DWCDDR21MCTL_ODTCR_RDODT0(x)	(((x) & 0xf) << 0)
#define DWCDDR21MCTL_ODTCR_RDODT1(x)	(((x) & 0xf) << 4)
#define DWCDDR21MCTL_ODTCR_RDODT2(x)	(((x) & 0xf) << 8)
#define DWCDDR21MCTL_ODTCR_RDODT3(x)	(((x) & 0xf) << 12)
#define DWCDDR21MCTL_ODTCR_WDODT0(x)	(((x) & 0xf) << 16)
#define DWCDDR21MCTL_ODTCR_WDODT1(x)	(((x) & 0xf) << 20)
#define DWCDDR21MCTL_ODTCR_WDODT2(x)	(((x) & 0xf) << 24)
#define DWCDDR21MCTL_ODTCR_WDODT3(x)	(((x) & 0xf) << 28)

/*
 * Data Training Register
 */
#define DWCDDR21MCTL_DTR0_DTBYTE0(x)	(((x) & 0xff) << 0)	/* def: 0x11 */
#define DWCDDR21MCTL_DTR0_DTBYTE1(x)	(((x) & 0xff) << 8)	/* def: 0xee */
#define DWCDDR21MCTL_DTR0_DTBYTE2(x)	(((x) & 0xff) << 16)	/* def: 0x22 */
#define DWCDDR21MCTL_DTR0_DTBYTE3(x)	(((x) & 0xff) << 24)	/* def: 0xdd */

#define DWCDDR21MCTL_DTR1_DTBYTE4(x)	(((x) & 0xff) << 0)	/* def: 0x44 */
#define DWCDDR21MCTL_DTR1_DTBYTE5(x)	(((x) & 0xff) << 8)	/* def: 0xbb */
#define DWCDDR21MCTL_DTR1_DTBYTE6(x)	(((x) & 0xff) << 16)	/* def: 0x88 */
#define DWCDDR21MCTL_DTR1_DTBYTE7(x)	(((x) & 0xff) << 24)	/* def: 0x77 */

/*
 * Data Training Address Register
 */
#define DWCDDR21MCTL_DTAR_DTCOL(x)	(((x) & 0xfff) << 0)
#define DWCDDR21MCTL_DTAR_DTROW(x)	(((x) & 0xffff) << 12)
#define DWCDDR21MCTL_DTAR_DTBANK(x)	(((x) & 0x7) << 28)

/*
 * Mode Register
 */
#define DWCDDR21MCTL_MR_BL(x)		(((x) & 0x7) << 0)
#define DWCDDR21MCTL_MR_BT(x)		((x) << 3)
#define DWCDDR21MCTL_MR_CL(x)		(((x) & 0x7) << 4)
#define DWCDDR21MCTL_MR_TM(x)		((x) << 7)
#define DWCDDR21MCTL_MR_DR(x)		((x) << 8)
#define DWCDDR21MCTL_MR_WR(x)		(((x) & 0x7) << 9)
#define DWCDDR21MCTL_MR_PD(x)		((x) << 12)

/*
 * Extended Mode register
 */
#define DWCDDR21MCTL_EMR_DE(x)		((x) << 0)
#define DWCDDR21MCTL_EMR_ODS(x)		((x) << 1)
#define DWCDDR21MCTL_EMR_RTT2(x)	((x) << 2)
#define DWCDDR21MCTL_EMR_AL(x)		(((x) & 0x7) << 3)
#define DWCDDR21MCTL_EMR_RTT6(x)	((x) << 6)
#define DWCDDR21MCTL_EMR_OCD(x)		(((x) & 0x7) << 7)
#define DWCDDR21MCTL_EMR_DQS(x)		((x) << 10)
#define DWCDDR21MCTL_EMR_RDQS(x)	((x) << 11)
#define DWCDDR21MCTL_EMR_OE(x)		((x) << 12)

#define EMR_RTT2(x)			DWCDDR21MCTL_EMR_RTT2(x)
#define EMR_RTT6(x)			DWCDDR21MCTL_EMR_RTT6(x)

#define DWCDDR21MCTL_EMR_RTT_DISABLED	(EMR_RTT6(0) | EMR_RTT2(0))
#define DWCDDR21MCTL_EMR_RTT_75		(EMR_RTT6(0) | EMR_RTT2(1))
#define DWCDDR21MCTL_EMR_RTT_150	(EMR_RTT6(1) | EMR_RTT2(0))
#define DWCDDR21MCTL_EMR_RTT_50		(EMR_RTT6(1) | EMR_RTT2(1))

/*
 * Extended Mode register 2
 */
#define DWCDDR21MCTL_EMR2_PASR(x)	(((x) & 0x7) << 0)
#define DWCDDR21MCTL_EMR2_DCC(x)	((x) << 3)
#define DWCDDR21MCTL_EMR2_SRF(x)	((x) << 7)

/*
 * Extended Mode register 3: [15:0] reserved for JEDEC.
 */

/*
 * Host port Configuration register 0-31
 */
#define DWCDDR21MCTL_HPCR_HPBL(x)	(((x) & 0xf) << 0)

/*
 * Priority Queue Configuration register 0-7
 */
#define DWCDDR21MCTL_HPCR_TOUT(x)	(((x) & 0xf) << 0)
#define DWCDDR21MCTL_HPCR_TOUTX(x)	(((x) & 0x3) << 8)
#define DWCDDR21MCTL_HPCR_LPQS(x)	(((x) & 0x3) << 10)
#define DWCDDR21MCTL_HPCR_PQBL(x)	(((x) & 0xff) << 12)
#define DWCDDR21MCTL_HPCR_SWAIT(x)	(((x) & 0x1f) << 20)
#define DWCDDR21MCTL_HPCR_INTRPT(x)	(((x) & 0x7) << 25)
#define DWCDDR21MCTL_HPCR_APQS(x)	((x) << 28)

/*
 * Memory Manager General Configuration register
 */
#define DWCDDR21MCTL_MMGCR_UHPP(x)	(((x) & 0x3) << 0)

#endif	/* __DWCDDR21MCTL_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
2ba5b1d3 ML	2	/*
	3	* (C) Copyright 2011 Andes Technology Corp
	4	* Macpaul Lin <macpaul@andestech.com>
2ba5b1d3 ML	5	*/
	6
	7	/*
	8	* DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
	9	*/
	10	#ifndef __DWCDDR21MCTL_H
	11	#define __DWCDDR21MCTL_H
	12
	13	#ifndef __ASSEMBLY__
	14	struct dwcddr21mctl {
	15	unsigned int ccr; /* Controller Configuration */
	16	unsigned int dcr; /* DRAM Configuration */
	17	unsigned int iocr; /* I/O Configuration */
	18	unsigned int csr; /* Controller Status */
	19	unsigned int drr; /* DRAM refresh */
	20	unsigned int tpr0; /* SDRAM Timing Parameters 0 */
	21	unsigned int tpr1; /* SDRAM Timing Parameters 1 */
	22	unsigned int tpr2; /* SDRAM Timing Parameters 2 */
	23	unsigned int gdllcr; /* Global DLL Control */
	24	unsigned int dllcr[10]; /* DLL Control */
	25	unsigned int rslr[4]; /* Rank System Lantency */
	26	unsigned int rdgr[4]; /* Rank DQS Gating */
	27	unsigned int dqtr[9]; /* DQ Timing */
	28	unsigned int dqstr; /* DQS Timing */
	29	unsigned int dqsbtr; /* DQS_b Timing */
	30	unsigned int odtcr; /* ODT Configuration */
	31	unsigned int dtr[2]; /* Data Training */
	32	unsigned int dtar; /* Data Training Address */
	33	unsigned int rsved[82]; /* Reserved */
	34	unsigned int mr; /* Mode Register */
	35	unsigned int emr; /* Extended Mode Register */
	36	unsigned int emr2; /* Extended Mode Register 2 */
	37	unsigned int emr3; /* Extended Mode Register 3 */
	38	unsigned int hpcr[32]; /* Host Port Configurarion */
	39	unsigned int pqcr[8]; /* Priority Queue Configuration */
	40	unsigned int mmgcr; /* Memory Manager General Config */
	41	};
	42	#endif /* __ASSEMBLY__ */
	43
	44	/*
	45	* Control Configuration Register
	46	*/
	47	#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
	48	#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
	49	#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
	50	#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
	51	#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
	52	#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
	53	#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
	54	#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
	55	#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
	56	#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
	57	#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
	58	#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
	59	#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
	60	#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
	61
	62	/*
	63	* DRAM Configuration Register
	64	*/
	65	#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
	66	#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
	67	#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
	68	#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
69	#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
70	#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
71	#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
72	#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
73	#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
74	#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
75	#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
76
77	/*
78	* I/O Configuration Register
79	*/
80	#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
81	#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
82	#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
83	#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
84	#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
85	#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
86	#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
87
88	/*
89	* Controller Status Register
90	*/
91	#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
92	#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
93	#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
94	#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
95	#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
96	#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
97
98	/*
99	* DRAM Refresh Register
100	*/
101	#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
102	#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
103	#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
104	#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
105
106	/*
107	* SDRAM Timing Parameters Register 0
108	*/
109	#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
110	#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
111	#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
112	#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
113	#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
114	#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
115	#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
116	#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
117	#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
118
119	/*
120	* SDRAM Timing Parameters Register 1
121	*/
122	#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
123	#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
124	#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
125	#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
126	#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
127	#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
128	#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
129	#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
130
131	/*
132	* SDRAM Timing Parameters Register 2
133	*/
134	#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
135	#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
136	#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
137
138	/*
139	* Global DLL Control Register
140	*/
141	#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
142	#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
143	#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
144	#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
145	#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
146	#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
147	#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
148	#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
149	#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
150
151	/*
152	* DLL Control Register 0-9
153	*/
154	#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
155	#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
156	#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
157	#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
158	#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
159	#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
160	#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
161	#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
162	#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
163
164	/*
165	* Rank System Lantency Register
166	*/
167	#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
168	#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
169	#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
170	#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
171	#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
172	#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
173	#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
174	#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
175	#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
176
177	/*
178	* Rank DQS Gating Register
179	*/
180	#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
181	#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
182	#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
183	#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
184	#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
185	#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
186	#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
187	#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
188	#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
189
190	/*
191	* DQ Timing Register
192	*/
193	#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
194	#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
195	#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
196	#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
197	#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
198	#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
199	#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
200	#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
201
202	/*
203	* DQS Timing Register
204	*/
205	#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
206	#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
207	#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
208	#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
209	#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
210	#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
211	#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
212	#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
213	#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
214
215	/*
216	* DQS_b (DQSBTR) Timing Register
217	*/
218	#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
219	#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
220	#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
221	#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
222	#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
223	#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
224	#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
225	#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
226	#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
227
228	/*
229	* ODT Configuration Register
230	*/
231	#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
232	#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
233	#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
234	#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
235	#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
236	#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
237	#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
238	#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
239
240	/*
241	* Data Training Register
242	*/
243	#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
244	#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
245	#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
246	#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
247
248	#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
249	#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
250	#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
251	#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
252
253	/*
254	* Data Training Address Register
255	*/
256	#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
257	#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
258	#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
259
260	/*
261	* Mode Register
262	*/
263	#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
264	#define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
265	#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
266	#define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
267	#define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
268	#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
269	#define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
270
271	/*
272	* Extended Mode register
273	*/
274	#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
275	#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
276	#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
277	#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
278	#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
279	#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
280	#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
281	#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
282	#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
283
284	#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
285	#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
286
287	#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) \| EMR_RTT2(0))
288	#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) \| EMR_RTT2(1))
289	#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) \| EMR_RTT2(0))
290	#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) \| EMR_RTT2(1))
291
292	/*
293	* Extended Mode register 2
294	*/
295	#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
296	#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
297	#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
298
299	/*
300	* Extended Mode register 3: [15:0] reserved for JEDEC.
301	*/
302
303	/*
304	* Host port Configuration register 0-31
305	*/
306	#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
307
308	/*
309	* Priority Queue Configuration register 0-7
310	*/
311	#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
312	#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
313	#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
314	#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
315	#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
316	#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
317	#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
318
319	/*
320	* Memory Manager General Configuration register
321	*/
322	#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
323
324	#endif /* __DWCDDR21MCTL_H */