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ad96090a BS |
1 | #ifndef QEMU_ARCH_INIT_H |
2 | #define QEMU_ARCH_INIT_H | |
3 | ||
452fcdbc | 4 | #include "qapi-types.h" |
0c764a9d | 5 | #include "qemu/option.h" |
76b64a7a | 6 | |
ad96090a BS |
7 | enum { |
8 | QEMU_ARCH_ALL = -1, | |
7e3d5238 BK |
9 | QEMU_ARCH_ALPHA = (1 << 0), |
10 | QEMU_ARCH_ARM = (1 << 1), | |
11 | QEMU_ARCH_CRIS = (1 << 2), | |
12 | QEMU_ARCH_I386 = (1 << 3), | |
13 | QEMU_ARCH_M68K = (1 << 4), | |
14 | QEMU_ARCH_LM32 = (1 << 5), | |
15 | QEMU_ARCH_MICROBLAZE = (1 << 6), | |
16 | QEMU_ARCH_MIPS = (1 << 7), | |
17 | QEMU_ARCH_PPC = (1 << 8), | |
18 | QEMU_ARCH_S390X = (1 << 9), | |
19 | QEMU_ARCH_SH4 = (1 << 10), | |
20 | QEMU_ARCH_SPARC = (1 << 11), | |
21 | QEMU_ARCH_XTENSA = (1 << 12), | |
22 | QEMU_ARCH_OPENRISC = (1 << 13), | |
23 | QEMU_ARCH_UNICORE32 = (1 << 14), | |
24 | QEMU_ARCH_MOXIE = (1 << 15), | |
25 | QEMU_ARCH_TRICORE = (1 << 16), | |
e671711c | 26 | QEMU_ARCH_NIOS2 = (1 << 17), |
813dff13 | 27 | QEMU_ARCH_HPPA = (1 << 18), |
ad96090a BS |
28 | }; |
29 | ||
30 | extern const uint32_t arch_type; | |
31 | ||
ad96090a BS |
32 | int kvm_available(void); |
33 | int xen_available(void); | |
34 | ||
67d223be | 35 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp); |
e09484ef DH |
36 | CpuModelExpansionInfo *arch_query_cpu_model_expansion(CpuModelExpansionType type, |
37 | CpuModelInfo *mode, | |
38 | Error **errp); | |
0031e0d6 DH |
39 | CpuModelCompareInfo *arch_query_cpu_model_comparison(CpuModelInfo *modela, |
40 | CpuModelInfo *modelb, | |
41 | Error **errp); | |
b18b6043 DH |
42 | CpuModelBaselineInfo *arch_query_cpu_model_baseline(CpuModelInfo *modela, |
43 | CpuModelInfo *modelb, | |
44 | Error **errp); | |
76b64a7a | 45 | |
ad96090a | 46 | #endif |