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Commit | Line | Data |
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42d1f039 WD |
1 | /* |
2 | * tsec.h | |
3 | * | |
4 | * Driver for the Motorola Triple Speed Ethernet Controller | |
5 | * | |
6 | * This software may be used and distributed according to the | |
7 | * terms of the GNU Public License, Version 2, incorporated | |
8 | * herein by reference. | |
9 | * | |
aec84bf6 | 10 | * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc. |
42d1f039 WD |
11 | * (C) Copyright 2003, Motorola, Inc. |
12 | * maintained by Xianghua Xiao (x.xiao@motorola.com) | |
13 | * author Andy Fleming | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __TSEC_H | |
18 | #define __TSEC_H | |
19 | ||
20 | #include <net.h> | |
f046ccd1 | 21 | #include <config.h> |
063c1263 AF |
22 | #include <phy.h> |
23 | #include <asm/fsl_enet.h> | |
f046ccd1 | 24 | |
b9e186fc SG |
25 | #define TSEC_SIZE 0x01000 |
26 | #define TSEC_MDIO_OFFSET 0x01000 | |
f046ccd1 | 27 | |
40ac3d46 | 28 | #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) |
063c1263 | 29 | |
aec84bf6 CM |
30 | #define TSEC_GET_REGS(num, offset) \ |
31 | (struct tsec __iomem *)\ | |
32 | (TSEC_BASE_ADDR + (((num) - 1) * (offset))) | |
33 | ||
34 | #define TSEC_GET_REGS_BASE(num) \ | |
35 | TSEC_GET_REGS((num), TSEC_SIZE) | |
36 | ||
37 | #define TSEC_GET_MDIO_REGS(num, offset) \ | |
38 | (struct tsec_mii_mng __iomem *)\ | |
39 | (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset)) | |
40 | ||
41 | #define TSEC_GET_MDIO_REGS_BASE(num) \ | |
42 | TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET) | |
43 | ||
063c1263 AF |
44 | #define DEFAULT_MII_NAME "FSL_MDIO" |
45 | ||
75b9d4ae AF |
46 | #define STD_TSEC_INFO(num) \ |
47 | { \ | |
aec84bf6 CM |
48 | .regs = TSEC_GET_REGS_BASE(num), \ |
49 | .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \ | |
75b9d4ae AF |
50 | .devname = CONFIG_TSEC##num##_NAME, \ |
51 | .phyaddr = TSEC##num##_PHY_ADDR, \ | |
063c1263 AF |
52 | .flags = TSEC##num##_FLAGS, \ |
53 | .mii_devname = DEFAULT_MII_NAME \ | |
75b9d4ae AF |
54 | } |
55 | ||
56 | #define SET_STD_TSEC_INFO(x, num) \ | |
57 | { \ | |
aec84bf6 CM |
58 | x.regs = TSEC_GET_REGS_BASE(num); \ |
59 | x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \ | |
75b9d4ae AF |
60 | x.devname = CONFIG_TSEC##num##_NAME; \ |
61 | x.phyaddr = TSEC##num##_PHY_ADDR; \ | |
62 | x.flags = TSEC##num##_FLAGS;\ | |
063c1263 | 63 | x.mii_devname = DEFAULT_MII_NAME;\ |
75b9d4ae AF |
64 | } |
65 | ||
42d1f039 WD |
66 | #define MAC_ADDR_LEN 6 |
67 | ||
53677ef1 | 68 | /* #define TSEC_TIMEOUT 1000000 */ |
97d80fc3 | 69 | #define TSEC_TIMEOUT 1000 |
53677ef1 | 70 | #define TOUT_LOOP 1000000 |
42d1f039 | 71 | |
2abe361c AF |
72 | /* TBI register addresses */ |
73 | #define TBI_CR 0x00 | |
74 | #define TBI_SR 0x01 | |
75 | #define TBI_ANA 0x04 | |
76 | #define TBI_ANLPBPA 0x05 | |
77 | #define TBI_ANEX 0x06 | |
78 | #define TBI_TBICON 0x11 | |
79 | ||
80 | /* TBI MDIO register bit fields*/ | |
81 | #define TBICON_CLK_SELECT 0x0020 | |
82 | #define TBIANA_ASYMMETRIC_PAUSE 0x0100 | |
83 | #define TBIANA_SYMMETRIC_PAUSE 0x0080 | |
84 | #define TBIANA_HALF_DUPLEX 0x0040 | |
85 | #define TBIANA_FULL_DUPLEX 0x0020 | |
86 | #define TBICR_PHY_RESET 0x8000 | |
87 | #define TBICR_ANEG_ENABLE 0x1000 | |
88 | #define TBICR_RESTART_ANEG 0x0200 | |
89 | #define TBICR_FULL_DUPLEX 0x0100 | |
90 | #define TBICR_SPEED1_SET 0x0040 | |
91 | ||
92 | ||
42d1f039 WD |
93 | /* MAC register bits */ |
94 | #define MACCFG1_SOFT_RESET 0x80000000 | |
95 | #define MACCFG1_RESET_RX_MC 0x00080000 | |
96 | #define MACCFG1_RESET_TX_MC 0x00040000 | |
97 | #define MACCFG1_RESET_RX_FUN 0x00020000 | |
98 | #define MACCFG1_RESET_TX_FUN 0x00010000 | |
99 | #define MACCFG1_LOOPBACK 0x00000100 | |
100 | #define MACCFG1_RX_FLOW 0x00000020 | |
101 | #define MACCFG1_TX_FLOW 0x00000010 | |
102 | #define MACCFG1_SYNCD_RX_EN 0x00000008 | |
103 | #define MACCFG1_RX_EN 0x00000004 | |
104 | #define MACCFG1_SYNCD_TX_EN 0x00000002 | |
105 | #define MACCFG1_TX_EN 0x00000001 | |
106 | ||
107 | #define MACCFG2_INIT_SETTINGS 0x00007205 | |
108 | #define MACCFG2_FULL_DUPLEX 0x00000001 | |
53677ef1 | 109 | #define MACCFG2_IF 0x00000300 |
97d80fc3 | 110 | #define MACCFG2_GMII 0x00000200 |
53677ef1 | 111 | #define MACCFG2_MII 0x00000100 |
42d1f039 WD |
112 | |
113 | #define ECNTRL_INIT_SETTINGS 0x00001000 | |
53677ef1 | 114 | #define ECNTRL_TBI_MODE 0x00000020 |
063c1263 | 115 | #define ECNTRL_REDUCED_MODE 0x00000010 |
d9b94f28 | 116 | #define ECNTRL_R100 0x00000008 |
063c1263 | 117 | #define ECNTRL_REDUCED_MII_MODE 0x00000004 |
81f481ca | 118 | #define ECNTRL_SGMII_MODE 0x00000002 |
42d1f039 | 119 | |
6d0f6bcf JCPV |
120 | #ifndef CONFIG_SYS_TBIPA_VALUE |
121 | #define CONFIG_SYS_TBIPA_VALUE 0x1f | |
dcb84b72 | 122 | #endif |
42d1f039 WD |
123 | |
124 | #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN | |
125 | ||
126 | #define MINFLR_INIT_SETTINGS 0x00000040 | |
127 | ||
53677ef1 WD |
128 | #define DMACTRL_INIT_SETTINGS 0x000000c3 |
129 | #define DMACTRL_GRS 0x00000010 | |
130 | #define DMACTRL_GTS 0x00000008 | |
42d1f039 | 131 | |
53677ef1 WD |
132 | #define TSTAT_CLEAR_THALT 0x80000000 |
133 | #define RSTAT_CLEAR_RHALT 0x00800000 | |
42d1f039 | 134 | |
7abf0c58 | 135 | |
42d1f039 WD |
136 | #define IEVENT_INIT_CLEAR 0xffffffff |
137 | #define IEVENT_BABR 0x80000000 | |
138 | #define IEVENT_RXC 0x40000000 | |
139 | #define IEVENT_BSY 0x20000000 | |
140 | #define IEVENT_EBERR 0x10000000 | |
141 | #define IEVENT_MSRO 0x04000000 | |
142 | #define IEVENT_GTSC 0x02000000 | |
143 | #define IEVENT_BABT 0x01000000 | |
144 | #define IEVENT_TXC 0x00800000 | |
145 | #define IEVENT_TXE 0x00400000 | |
146 | #define IEVENT_TXB 0x00200000 | |
147 | #define IEVENT_TXF 0x00100000 | |
148 | #define IEVENT_IE 0x00080000 | |
149 | #define IEVENT_LC 0x00040000 | |
150 | #define IEVENT_CRL 0x00020000 | |
151 | #define IEVENT_XFUN 0x00010000 | |
152 | #define IEVENT_RXB0 0x00008000 | |
153 | #define IEVENT_GRSC 0x00000100 | |
154 | #define IEVENT_RXF0 0x00000080 | |
155 | ||
156 | #define IMASK_INIT_CLEAR 0x00000000 | |
157 | #define IMASK_TXEEN 0x00400000 | |
158 | #define IMASK_TXBEN 0x00200000 | |
53677ef1 | 159 | #define IMASK_TXFEN 0x00100000 |
42d1f039 WD |
160 | #define IMASK_RXFEN0 0x00000080 |
161 | ||
162 | ||
163 | /* Default Attribute fields */ | |
164 | #define ATTR_INIT_SETTINGS 0x000000c0 | |
165 | #define ATTRELI_INIT_SETTINGS 0x00000000 | |
166 | ||
167 | ||
168 | /* TxBD status field bits */ | |
169 | #define TXBD_READY 0x8000 | |
170 | #define TXBD_PADCRC 0x4000 | |
171 | #define TXBD_WRAP 0x2000 | |
172 | #define TXBD_INTERRUPT 0x1000 | |
173 | #define TXBD_LAST 0x0800 | |
174 | #define TXBD_CRC 0x0400 | |
175 | #define TXBD_DEF 0x0200 | |
176 | #define TXBD_HUGEFRAME 0x0080 | |
177 | #define TXBD_LATECOLLISION 0x0080 | |
178 | #define TXBD_RETRYLIMIT 0x0040 | |
179 | #define TXBD_RETRYCOUNTMASK 0x003c | |
180 | #define TXBD_UNDERRUN 0x0002 | |
53677ef1 | 181 | #define TXBD_STATS 0x03ff |
42d1f039 WD |
182 | |
183 | /* RxBD status field bits */ | |
184 | #define RXBD_EMPTY 0x8000 | |
185 | #define RXBD_RO1 0x4000 | |
186 | #define RXBD_WRAP 0x2000 | |
187 | #define RXBD_INTERRUPT 0x1000 | |
188 | #define RXBD_LAST 0x0800 | |
189 | #define RXBD_FIRST 0x0400 | |
190 | #define RXBD_MISS 0x0100 | |
191 | #define RXBD_BROADCAST 0x0080 | |
192 | #define RXBD_MULTICAST 0x0040 | |
193 | #define RXBD_LARGE 0x0020 | |
194 | #define RXBD_NONOCTET 0x0010 | |
195 | #define RXBD_SHORT 0x0008 | |
196 | #define RXBD_CRCERR 0x0004 | |
197 | #define RXBD_OVERRUN 0x0002 | |
198 | #define RXBD_TRUNCATED 0x0001 | |
199 | #define RXBD_STATS 0x003f | |
200 | ||
9c9141fd CM |
201 | struct txbd8 { |
202 | uint16_t status; /* Status Fields */ | |
203 | uint16_t length; /* Buffer length */ | |
204 | uint32_t bufptr; /* Buffer Pointer */ | |
205 | }; | |
206 | ||
207 | struct rxbd8 { | |
208 | uint16_t status; /* Status Fields */ | |
209 | uint16_t length; /* Buffer Length */ | |
210 | uint32_t bufptr; /* Buffer Pointer */ | |
211 | }; | |
42d1f039 | 212 | |
82ef75ca | 213 | struct tsec_rmon_mib { |
42d1f039 | 214 | /* Transmit and Receive Counters */ |
82ef75ca CM |
215 | u32 tr64; /* Tx/Rx 64-byte Frame Counter */ |
216 | u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */ | |
217 | u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */ | |
218 | u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */ | |
219 | u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */ | |
220 | u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */ | |
221 | u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */ | |
42d1f039 | 222 | /* Receive Counters */ |
82ef75ca CM |
223 | u32 rbyt; /* Receive Byte Counter */ |
224 | u32 rpkt; /* Receive Packet Counter */ | |
225 | u32 rfcs; /* Receive FCS Error Counter */ | |
226 | u32 rmca; /* Receive Multicast Packet (Counter) */ | |
227 | u32 rbca; /* Receive Broadcast Packet */ | |
228 | u32 rxcf; /* Receive Control Frame Packet */ | |
229 | u32 rxpf; /* Receive Pause Frame Packet */ | |
230 | u32 rxuo; /* Receive Unknown OP Code */ | |
231 | u32 raln; /* Receive Alignment Error */ | |
232 | u32 rflr; /* Receive Frame Length Error */ | |
233 | u32 rcde; /* Receive Code Error */ | |
234 | u32 rcse; /* Receive Carrier Sense Error */ | |
235 | u32 rund; /* Receive Undersize Packet */ | |
236 | u32 rovr; /* Receive Oversize Packet */ | |
237 | u32 rfrg; /* Receive Fragments */ | |
238 | u32 rjbr; /* Receive Jabber */ | |
239 | u32 rdrp; /* Receive Drop */ | |
42d1f039 | 240 | /* Transmit Counters */ |
82ef75ca CM |
241 | u32 tbyt; /* Transmit Byte Counter */ |
242 | u32 tpkt; /* Transmit Packet */ | |
243 | u32 tmca; /* Transmit Multicast Packet */ | |
244 | u32 tbca; /* Transmit Broadcast Packet */ | |
245 | u32 txpf; /* Transmit Pause Control Frame */ | |
246 | u32 tdfr; /* Transmit Deferral Packet */ | |
247 | u32 tedf; /* Transmit Excessive Deferral Packet */ | |
248 | u32 tscl; /* Transmit Single Collision Packet */ | |
42d1f039 | 249 | /* (0x2_n700) */ |
82ef75ca CM |
250 | u32 tmcl; /* Transmit Multiple Collision Packet */ |
251 | u32 tlcl; /* Transmit Late Collision Packet */ | |
252 | u32 txcl; /* Transmit Excessive Collision Packet */ | |
253 | u32 tncl; /* Transmit Total Collision */ | |
254 | ||
255 | u32 res2; | |
256 | ||
257 | u32 tdrp; /* Transmit Drop Frame */ | |
258 | u32 tjbr; /* Transmit Jabber Frame */ | |
259 | u32 tfcs; /* Transmit FCS Error */ | |
260 | u32 txcf; /* Transmit Control Frame */ | |
261 | u32 tovr; /* Transmit Oversize Frame */ | |
262 | u32 tund; /* Transmit Undersize Frame */ | |
263 | u32 tfrg; /* Transmit Fragments Frame */ | |
42d1f039 | 264 | /* General Registers */ |
82ef75ca CM |
265 | u32 car1; /* Carry Register One */ |
266 | u32 car2; /* Carry Register Two */ | |
267 | u32 cam1; /* Carry Register One Mask */ | |
268 | u32 cam2; /* Carry Register Two Mask */ | |
269 | }; | |
270 | ||
271 | struct tsec_hash_regs { | |
272 | u32 iaddr0; /* Individual Address Register 0 */ | |
273 | u32 iaddr1; /* Individual Address Register 1 */ | |
274 | u32 iaddr2; /* Individual Address Register 2 */ | |
275 | u32 iaddr3; /* Individual Address Register 3 */ | |
276 | u32 iaddr4; /* Individual Address Register 4 */ | |
277 | u32 iaddr5; /* Individual Address Register 5 */ | |
278 | u32 iaddr6; /* Individual Address Register 6 */ | |
279 | u32 iaddr7; /* Individual Address Register 7 */ | |
280 | u32 res1[24]; | |
281 | u32 gaddr0; /* Group Address Register 0 */ | |
282 | u32 gaddr1; /* Group Address Register 1 */ | |
283 | u32 gaddr2; /* Group Address Register 2 */ | |
284 | u32 gaddr3; /* Group Address Register 3 */ | |
285 | u32 gaddr4; /* Group Address Register 4 */ | |
286 | u32 gaddr5; /* Group Address Register 5 */ | |
287 | u32 gaddr6; /* Group Address Register 6 */ | |
288 | u32 gaddr7; /* Group Address Register 7 */ | |
289 | u32 res2[24]; | |
290 | }; | |
42d1f039 | 291 | |
aec84bf6 | 292 | struct tsec { |
42d1f039 | 293 | /* General Control and Status Registers (0x2_n000) */ |
82ef75ca | 294 | u32 res000[4]; |
42d1f039 | 295 | |
82ef75ca CM |
296 | u32 ievent; /* Interrupt Event */ |
297 | u32 imask; /* Interrupt Mask */ | |
298 | u32 edis; /* Error Disabled */ | |
299 | u32 res01c; | |
300 | u32 ecntrl; /* Ethernet Control */ | |
301 | u32 minflr; /* Minimum Frame Length */ | |
302 | u32 ptv; /* Pause Time Value */ | |
303 | u32 dmactrl; /* DMA Control */ | |
304 | u32 tbipa; /* TBI PHY Address */ | |
42d1f039 | 305 | |
82ef75ca CM |
306 | u32 res034[3]; |
307 | u32 res040[48]; | |
42d1f039 WD |
308 | |
309 | /* Transmit Control and Status Registers (0x2_n100) */ | |
82ef75ca CM |
310 | u32 tctrl; /* Transmit Control */ |
311 | u32 tstat; /* Transmit Status */ | |
312 | u32 res108; | |
313 | u32 tbdlen; /* Tx BD Data Length */ | |
314 | u32 res110[5]; | |
315 | u32 ctbptr; /* Current TxBD Pointer */ | |
316 | u32 res128[23]; | |
317 | u32 tbptr; /* TxBD Pointer */ | |
318 | u32 res188[30]; | |
42d1f039 | 319 | /* (0x2_n200) */ |
82ef75ca CM |
320 | u32 res200; |
321 | u32 tbase; /* TxBD Base Address */ | |
322 | u32 res208[42]; | |
323 | u32 ostbd; /* Out of Sequence TxBD */ | |
324 | u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ | |
325 | u32 res2b8[18]; | |
42d1f039 WD |
326 | |
327 | /* Receive Control and Status Registers (0x2_n300) */ | |
82ef75ca CM |
328 | u32 rctrl; /* Receive Control */ |
329 | u32 rstat; /* Receive Status */ | |
330 | u32 res308; | |
331 | u32 rbdlen; /* RxBD Data Length */ | |
332 | u32 res310[4]; | |
333 | u32 res320; | |
334 | u32 crbptr; /* Current Receive Buffer Pointer */ | |
335 | u32 res328[6]; | |
336 | u32 mrblr; /* Maximum Receive Buffer Length */ | |
337 | u32 res344[16]; | |
338 | u32 rbptr; /* RxBD Pointer */ | |
339 | u32 res388[30]; | |
42d1f039 | 340 | /* (0x2_n400) */ |
82ef75ca CM |
341 | u32 res400; |
342 | u32 rbase; /* RxBD Base Address */ | |
343 | u32 res408[62]; | |
42d1f039 WD |
344 | |
345 | /* MAC Registers (0x2_n500) */ | |
82ef75ca CM |
346 | u32 maccfg1; /* MAC Configuration #1 */ |
347 | u32 maccfg2; /* MAC Configuration #2 */ | |
348 | u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ | |
349 | u32 hafdup; /* Half-duplex */ | |
350 | u32 maxfrm; /* Maximum Frame */ | |
351 | u32 res514; | |
352 | u32 res518; | |
42d1f039 | 353 | |
82ef75ca | 354 | u32 res51c; |
42d1f039 | 355 | |
82ef75ca | 356 | u32 resmdio[6]; |
42d1f039 | 357 | |
82ef75ca | 358 | u32 res538; |
42d1f039 | 359 | |
82ef75ca CM |
360 | u32 ifstat; /* Interface Status */ |
361 | u32 macstnaddr1; /* Station Address, part 1 */ | |
362 | u32 macstnaddr2; /* Station Address, part 2 */ | |
363 | u32 res548[46]; | |
42d1f039 WD |
364 | |
365 | /* (0x2_n600) */ | |
82ef75ca | 366 | u32 res600[32]; |
42d1f039 WD |
367 | |
368 | /* RMON MIB Registers (0x2_n680-0x2_n73c) */ | |
82ef75ca CM |
369 | struct tsec_rmon_mib rmon; |
370 | u32 res740[48]; | |
42d1f039 WD |
371 | |
372 | /* Hash Function Registers (0x2_n800) */ | |
82ef75ca | 373 | struct tsec_hash_regs hash; |
42d1f039 | 374 | |
82ef75ca | 375 | u32 res900[128]; |
42d1f039 WD |
376 | |
377 | /* Pattern Registers (0x2_nb00) */ | |
82ef75ca CM |
378 | u32 resb00[62]; |
379 | u32 attr; /* Default Attribute Register */ | |
380 | u32 attreli; /* Default Attribute Extract Length and Index */ | |
42d1f039 WD |
381 | |
382 | /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ | |
82ef75ca | 383 | u32 resc00[256]; |
aec84bf6 | 384 | }; |
42d1f039 | 385 | |
063c1263 | 386 | #define TSEC_GIGABIT (1 << 0) |
d9b94f28 | 387 | |
063c1263 | 388 | /* These flags currently only have meaning if we're using the eTSEC */ |
5f6b1442 PT |
389 | #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ |
390 | #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ | |
d9b94f28 | 391 | |
97d80fc3 | 392 | struct tsec_private { |
aec84bf6 CM |
393 | struct tsec __iomem *regs; |
394 | struct tsec_mii_mng __iomem *phyregs_sgmii; | |
063c1263 AF |
395 | struct phy_device *phydev; |
396 | phy_interface_t interface; | |
397 | struct mii_dev *bus; | |
97d80fc3 | 398 | uint phyaddr; |
063c1263 | 399 | char mii_devname[16]; |
d9b94f28 | 400 | u32 flags; |
97d80fc3 WD |
401 | }; |
402 | ||
dd3d1f56 | 403 | struct tsec_info_struct { |
aec84bf6 CM |
404 | struct tsec __iomem *regs; |
405 | struct tsec_mii_mng __iomem *miiregs_sgmii; | |
75b9d4ae | 406 | char *devname; |
063c1263 AF |
407 | char *mii_devname; |
408 | phy_interface_t interface; | |
dd3d1f56 AF |
409 | unsigned int phyaddr; |
410 | u32 flags; | |
dd3d1f56 AF |
411 | }; |
412 | ||
75b9d4ae AF |
413 | int tsec_standard_init(bd_t *bis); |
414 | int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); | |
415 | ||
42d1f039 | 416 | #endif /* __TSEC_H */ |