[thirdparty/u-boot.git] / include / tsec.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  tsec.h
 *
 *  Driver for the Motorola Triple Speed Ethernet Controller
 *
 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
 * (C) Copyright 2003, Motorola, Inc.
 * maintained by Xianghua Xiao (x.xiao@motorola.com)
 * author Andy Fleming
 */

#ifndef __TSEC_H
#define __TSEC_H

#include <net.h>
#include <config.h>
#include <phy.h>

#define TSEC_MDIO_REGS_OFFSET	0x520

#define MAC_ADDR_LEN		6

/* #define TSEC_TIMEOUT	1000000 */
#define TSEC_TIMEOUT		1000
#define TOUT_LOOP		1000000

/* TBI register addresses */
#define TBI_CR			0x00
#define TBI_SR			0x01
#define TBI_ANA			0x04
#define TBI_ANLPBPA		0x05
#define TBI_ANEX		0x06
#define TBI_TBICON		0x11

/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT	0x0020
#define TBIANA_ASYMMETRIC_PAUSE	0x0100
#define TBIANA_SYMMETRIC_PAUSE	0x0080
#define TBIANA_HALF_DUPLEX	0x0040
#define TBIANA_FULL_DUPLEX	0x0020
#define TBICR_PHY_RESET		0x8000
#define TBICR_ANEG_ENABLE	0x1000
#define TBICR_RESTART_ANEG	0x0200
#define TBICR_FULL_DUPLEX	0x0100
#define TBICR_SPEED1_SET	0x0040

/* MAC register bits */
#define MACCFG1_SOFT_RESET	0x80000000
#define MACCFG1_RESET_RX_MC	0x00080000
#define MACCFG1_RESET_TX_MC	0x00040000
#define MACCFG1_RESET_RX_FUN	0x00020000
#define MACCFG1_RESET_TX_FUN	0x00010000
#define MACCFG1_LOOPBACK	0x00000100
#define MACCFG1_RX_FLOW		0x00000020
#define MACCFG1_TX_FLOW		0x00000010
#define MACCFG1_SYNCD_RX_EN	0x00000008
#define MACCFG1_RX_EN		0x00000004
#define MACCFG1_SYNCD_TX_EN	0x00000002
#define MACCFG1_TX_EN		0x00000001

#define MACCFG2_INIT_SETTINGS	0x00007205
#define MACCFG2_FULL_DUPLEX	0x00000001
#define MACCFG2_IF		0x00000300
#define MACCFG2_GMII		0x00000200
#define MACCFG2_MII		0x00000100

#define ECNTRL_INIT_SETTINGS	0x00001000
#define ECNTRL_TBI_MODE		0x00000020
#define ECNTRL_REDUCED_MODE	0x00000010
#define ECNTRL_R100		0x00000008
#define ECNTRL_REDUCED_MII_MODE	0x00000004
#define ECNTRL_SGMII_MODE	0x00000002

#define RCTRL_PROM		0x00000008

#ifndef CFG_SYS_TBIPA_VALUE
# define CFG_SYS_TBIPA_VALUE	0x1f
#endif

#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN

#define MINFLR_INIT_SETTINGS	0x00000040

#define DMACTRL_INIT_SETTINGS	0x000000c3
#define DMACTRL_GRS		0x00000010
#define DMACTRL_GTS		0x00000008
#define DMACTRL_LE		0x00008000

#define TSTAT_CLEAR_THALT	0x80000000
#define RSTAT_CLEAR_RHALT	0x00800000

#define IEVENT_INIT_CLEAR	0xffffffff
#define IEVENT_BABR		0x80000000
#define IEVENT_RXC		0x40000000
#define IEVENT_BSY		0x20000000
#define IEVENT_EBERR		0x10000000
#define IEVENT_MSRO		0x04000000
#define IEVENT_GTSC		0x02000000
#define IEVENT_BABT		0x01000000
#define IEVENT_TXC		0x00800000
#define IEVENT_TXE		0x00400000
#define IEVENT_TXB		0x00200000
#define IEVENT_TXF		0x00100000
#define IEVENT_IE		0x00080000
#define IEVENT_LC		0x00040000
#define IEVENT_CRL		0x00020000
#define IEVENT_XFUN		0x00010000
#define IEVENT_RXB0		0x00008000
#define IEVENT_GRSC		0x00000100
#define IEVENT_RXF0		0x00000080

#define IMASK_INIT_CLEAR	0x00000000
#define IMASK_TXEEN		0x00400000
#define IMASK_TXBEN		0x00200000
#define IMASK_TXFEN		0x00100000
#define IMASK_RXFEN0		0x00000080

/* Default Attribute fields */
#define ATTR_INIT_SETTINGS	0x000000c0
#define ATTRELI_INIT_SETTINGS	0x00000000

/* TxBD status field bits */
#define TXBD_READY		0x8000
#define TXBD_PADCRC		0x4000
#define TXBD_WRAP		0x2000
#define TXBD_INTERRUPT		0x1000
#define TXBD_LAST		0x0800
#define TXBD_CRC		0x0400
#define TXBD_DEF		0x0200
#define TXBD_HUGEFRAME		0x0080
#define TXBD_LATECOLLISION	0x0080
#define TXBD_RETRYLIMIT		0x0040
#define TXBD_RETRYCOUNTMASK	0x003c
#define TXBD_UNDERRUN		0x0002
#define TXBD_STATS		0x03ff

/* RxBD status field bits */
#define RXBD_EMPTY		0x8000
#define RXBD_RO1		0x4000
#define RXBD_WRAP		0x2000
#define RXBD_INTERRUPT		0x1000
#define RXBD_LAST		0x0800
#define RXBD_FIRST		0x0400
#define RXBD_MISS		0x0100
#define RXBD_BROADCAST		0x0080
#define RXBD_MULTICAST		0x0040
#define RXBD_LARGE		0x0020
#define RXBD_NONOCTET		0x0010
#define RXBD_SHORT		0x0008
#define RXBD_CRCERR		0x0004
#define RXBD_OVERRUN		0x0002
#define RXBD_TRUNCATED		0x0001
#define RXBD_STATS		0x003f

struct txbd8 {
	uint16_t status;	/* Status Fields */
	uint16_t length;	/* Buffer length */
	uint32_t bufptr;	/* Buffer Pointer */
};

struct rxbd8 {
	uint16_t status;	/* Status Fields */
	uint16_t length;	/* Buffer Length */
	uint32_t bufptr;	/* Buffer Pointer */
};

struct tsec_rmon_mib {
	/* Transmit and Receive Counters */
	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
	/* Receive Counters */
	u32	rbyt;		/* Receive Byte Counter */
	u32	rpkt;		/* Receive Packet Counter */
	u32	rfcs;		/* Receive FCS Error Counter */
	u32	rmca;		/* Receive Multicast Packet (Counter) */
	u32	rbca;		/* Receive Broadcast Packet */
	u32	rxcf;		/* Receive Control Frame Packet */
	u32	rxpf;		/* Receive Pause Frame Packet */
	u32	rxuo;		/* Receive Unknown OP Code */
	u32	raln;		/* Receive Alignment Error */
	u32	rflr;		/* Receive Frame Length Error */
	u32	rcde;		/* Receive Code Error */
	u32	rcse;		/* Receive Carrier Sense Error */
	u32	rund;		/* Receive Undersize Packet */
	u32	rovr;		/* Receive Oversize Packet */
	u32	rfrg;		/* Receive Fragments */
	u32	rjbr;		/* Receive Jabber */
	u32	rdrp;		/* Receive Drop */
	/* Transmit Counters */
	u32	tbyt;		/* Transmit Byte Counter */
	u32	tpkt;		/* Transmit Packet */
	u32	tmca;		/* Transmit Multicast Packet */
	u32	tbca;		/* Transmit Broadcast Packet */
	u32	txpf;		/* Transmit Pause Control Frame */
	u32	tdfr;		/* Transmit Deferral Packet */
	u32	tedf;		/* Transmit Excessive Deferral Packet */
	u32	tscl;		/* Transmit Single Collision Packet */
	/* (0x2_n700) */
	u32	tmcl;		/* Transmit Multiple Collision Packet */
	u32	tlcl;		/* Transmit Late Collision Packet */
	u32	txcl;		/* Transmit Excessive Collision Packet */
	u32	tncl;		/* Transmit Total Collision */

	u32	res2;

	u32	tdrp;		/* Transmit Drop Frame */
	u32	tjbr;		/* Transmit Jabber Frame */
	u32	tfcs;		/* Transmit FCS Error */
	u32	txcf;		/* Transmit Control Frame */
	u32	tovr;		/* Transmit Oversize Frame */
	u32	tund;		/* Transmit Undersize Frame */
	u32	tfrg;		/* Transmit Fragments Frame */
	/* General Registers */
	u32	car1;		/* Carry Register One */
	u32	car2;		/* Carry Register Two */
	u32	cam1;		/* Carry Register One Mask */
	u32	cam2;		/* Carry Register Two Mask */
};

struct tsec_hash_regs {
	u32	iaddr0;		/* Individual Address Register 0 */
	u32	iaddr1;		/* Individual Address Register 1 */
	u32	iaddr2;		/* Individual Address Register 2 */
	u32	iaddr3;		/* Individual Address Register 3 */
	u32	iaddr4;		/* Individual Address Register 4 */
	u32	iaddr5;		/* Individual Address Register 5 */
	u32	iaddr6;		/* Individual Address Register 6 */
	u32	iaddr7;		/* Individual Address Register 7 */
	u32	res1[24];
	u32	gaddr0;		/* Group Address Register 0 */
	u32	gaddr1;		/* Group Address Register 1 */
	u32	gaddr2;		/* Group Address Register 2 */
	u32	gaddr3;		/* Group Address Register 3 */
	u32	gaddr4;		/* Group Address Register 4 */
	u32	gaddr5;		/* Group Address Register 5 */
	u32	gaddr6;		/* Group Address Register 6 */
	u32	gaddr7;		/* Group Address Register 7 */
	u32	res2[24];
};

struct tsec {
	/* General Control and Status Registers (0x2_n000) */
	u32	res000[4];

	u32	ievent;		/* Interrupt Event */
	u32	imask;		/* Interrupt Mask */
	u32	edis;		/* Error Disabled */
	u32	res01c;
	u32	ecntrl;		/* Ethernet Control */
	u32	minflr;		/* Minimum Frame Length */
	u32	ptv;		/* Pause Time Value */
	u32	dmactrl;	/* DMA Control */
	u32	tbipa;		/* TBI PHY Address */

	u32	res034[3];
	u32	res040[48];

	/* Transmit Control and Status Registers (0x2_n100) */
	u32	tctrl;		/* Transmit Control */
	u32	tstat;		/* Transmit Status */
	u32	res108;
	u32	tbdlen;		/* Tx BD Data Length */
	u32	res110[5];
	u32	ctbptr;		/* Current TxBD Pointer */
	u32	res128[23];
	u32	tbptr;		/* TxBD Pointer */
	u32	res188[30];
	/* (0x2_n200) */
	u32	res200;
	u32	tbase;		/* TxBD Base Address */
	u32	res208[42];
	u32	ostbd;		/* Out of Sequence TxBD */
	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
	u32	res2b8[18];

	/* Receive Control and Status Registers (0x2_n300) */
	u32	rctrl;		/* Receive Control */
	u32	rstat;		/* Receive Status */
	u32	res308;
	u32	rbdlen;		/* RxBD Data Length */
	u32	res310[4];
	u32	res320;
	u32	crbptr;		/* Current Receive Buffer Pointer */
	u32	res328[6];
	u32	mrblr;		/* Maximum Receive Buffer Length */
	u32	res344[16];
	u32	rbptr;		/* RxBD Pointer */
	u32	res388[30];
	/* (0x2_n400) */
	u32	res400;
	u32	rbase;		/* RxBD Base Address */
	u32	res408[62];

	/* MAC Registers (0x2_n500) */
	u32	maccfg1;	/* MAC Configuration #1 */
	u32	maccfg2;	/* MAC Configuration #2 */
	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
	u32	hafdup;		/* Half-duplex */
	u32	maxfrm;		/* Maximum Frame */
	u32	res514;
	u32	res518;

	u32	res51c;

	u32	resmdio[6];

	u32	res538;

	u32	ifstat;		/* Interface Status */
	u32	macstnaddr1;	/* Station Address, part 1 */
	u32	macstnaddr2;	/* Station Address, part 2 */
	u32	res548[46];

	/* (0x2_n600) */
	u32	res600[32];

	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
	struct tsec_rmon_mib	rmon;
	u32	res740[48];

	/* Hash Function Registers (0x2_n800) */
	struct tsec_hash_regs	hash;

	u32	res900[128];

	/* Pattern Registers (0x2_nb00) */
	u32	resb00[62];
	u32	attr; /* Default Attribute Register */
	u32	attreli; /* Default Attribute Extract Length and Index */

	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
	u32	resc00[256];
};

#define TSEC_GIGABIT	(1 << 0)

/* These flags currently only have meaning if we're using the eTSEC */
#define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
#define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */

#define TX_BUF_CNT	2

struct tsec_data {
	u32 mdio_regs_off;
};

struct tsec_private {
	struct txbd8 __iomem txbd[TX_BUF_CNT];
	struct rxbd8 __iomem rxbd[PKTBUFSRX];
	struct tsec __iomem *regs;
	struct tsec_mii_mng __iomem *phyregs_sgmii;
	struct phy_device *phydev;
	phy_interface_t interface;
	struct mii_dev *bus;
	uint phyaddr;
	uint tbiaddr;
	char mii_devname[16];
	u32 flags;
	uint rx_idx;	/* index of the current RX buffer */
	uint tx_idx;	/* index of the current TX buffer */
	struct udevice *dev;
};

struct tsec_info_struct {
	struct tsec __iomem *regs;
	struct tsec_mii_mng __iomem *miiregs_sgmii;
	char *devname;
	char *mii_devname;
	phy_interface_t interface;
	unsigned int phyaddr;
	u32 flags;
};

#endif /* __TSEC_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
42d1f039 WD	2	/*
	3	* tsec.h
	4	*
	5	* Driver for the Motorola Triple Speed Ethernet Controller
	6	*
aec84bf6	7	* Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
42d1f039 WD	8	* (C) Copyright 2003, Motorola, Inc.
	9	* maintained by Xianghua Xiao (x.xiao@motorola.com)
	10	* author Andy Fleming
42d1f039 WD	11	*/
	12
	13	#ifndef __TSEC_H
	14	#define __TSEC_H
	15
	16	#include <net.h>
f046ccd1	17	#include <config.h>
063c1263	18	#include <phy.h>
f046ccd1	19
bca686a4 VO	20	#define TSEC_MDIO_REGS_OFFSET 0x520
bca686a4 VO	21
9872b736	22	#define MAC_ADDR_LEN 6
42d1f039	23
53677ef1	24	/* #define TSEC_TIMEOUT 1000000 */
9872b736 BM	25	#define TSEC_TIMEOUT 1000
9872b736 BM	26	#define TOUT_LOOP 1000000
42d1f039	27
2abe361c AF	28	/* TBI register addresses */
	29	#define TBI_CR 0x00
	30	#define TBI_SR 0x01
	31	#define TBI_ANA 0x04
	32	#define TBI_ANLPBPA 0x05
	33	#define TBI_ANEX 0x06
	34	#define TBI_TBICON 0x11
	35
	36	/* TBI MDIO register bit fields*/
	37	#define TBICON_CLK_SELECT 0x0020
9872b736 BM	38	#define TBIANA_ASYMMETRIC_PAUSE 0x0100
9872b736 BM	39	#define TBIANA_SYMMETRIC_PAUSE 0x0080
2abe361c AF	40	#define TBIANA_HALF_DUPLEX 0x0040
	41	#define TBIANA_FULL_DUPLEX 0x0020
	42	#define TBICR_PHY_RESET 0x8000
	43	#define TBICR_ANEG_ENABLE 0x1000
	44	#define TBICR_RESTART_ANEG 0x0200
	45	#define TBICR_FULL_DUPLEX 0x0100
	46	#define TBICR_SPEED1_SET 0x0040
	47
42d1f039 WD	48	/* MAC register bits */
	49	#define MACCFG1_SOFT_RESET 0x80000000
	50	#define MACCFG1_RESET_RX_MC 0x00080000
	51	#define MACCFG1_RESET_TX_MC 0x00040000
	52	#define MACCFG1_RESET_RX_FUN 0x00020000
9872b736	53	#define MACCFG1_RESET_TX_FUN 0x00010000
42d1f039 WD	54	#define MACCFG1_LOOPBACK 0x00000100
	55	#define MACCFG1_RX_FLOW 0x00000020
	56	#define MACCFG1_TX_FLOW 0x00000010
	57	#define MACCFG1_SYNCD_RX_EN 0x00000008
	58	#define MACCFG1_RX_EN 0x00000004
	59	#define MACCFG1_SYNCD_TX_EN 0x00000002
	60	#define MACCFG1_TX_EN 0x00000001
	61
	62	#define MACCFG2_INIT_SETTINGS 0x00007205
	63	#define MACCFG2_FULL_DUPLEX 0x00000001
53677ef1	64	#define MACCFG2_IF 0x00000300
97d80fc3	65	#define MACCFG2_GMII 0x00000200
53677ef1	66	#define MACCFG2_MII 0x00000100
42d1f039 WD	67
42d1f039 WD	68	#define ECNTRL_INIT_SETTINGS 0x00001000
53677ef1	69	#define ECNTRL_TBI_MODE 0x00000020
063c1263	70	#define ECNTRL_REDUCED_MODE 0x00000010
d9b94f28	71	#define ECNTRL_R100 0x00000008
063c1263	72	#define ECNTRL_REDUCED_MII_MODE 0x00000004
81f481ca	73	#define ECNTRL_SGMII_MODE 0x00000002
42d1f039	74
9dcb810b VO	75	#define RCTRL_PROM 0x00000008
9dcb810b VO	76
65cc0e2a TR	77	#ifndef CFG_SYS_TBIPA_VALUE
65cc0e2a TR	78	# define CFG_SYS_TBIPA_VALUE 0x1f
dcb84b72	79	#endif
42d1f039 WD	80
	81	#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
	82
	83	#define MINFLR_INIT_SETTINGS 0x00000040
	84
53677ef1 WD	85	#define DMACTRL_INIT_SETTINGS 0x000000c3
	86	#define DMACTRL_GRS 0x00000010
	87	#define DMACTRL_GTS 0x00000008
52d00a81	88	#define DMACTRL_LE 0x00008000
42d1f039	89
53677ef1 WD	90	#define TSTAT_CLEAR_THALT 0x80000000
53677ef1 WD	91	#define RSTAT_CLEAR_RHALT 0x00800000
42d1f039	92
42d1f039 WD	93	#define IEVENT_INIT_CLEAR 0xffffffff
	94	#define IEVENT_BABR 0x80000000
	95	#define IEVENT_RXC 0x40000000
	96	#define IEVENT_BSY 0x20000000
	97	#define IEVENT_EBERR 0x10000000
	98	#define IEVENT_MSRO 0x04000000
	99	#define IEVENT_GTSC 0x02000000
	100	#define IEVENT_BABT 0x01000000
	101	#define IEVENT_TXC 0x00800000
	102	#define IEVENT_TXE 0x00400000
	103	#define IEVENT_TXB 0x00200000
	104	#define IEVENT_TXF 0x00100000
	105	#define IEVENT_IE 0x00080000
	106	#define IEVENT_LC 0x00040000
	107	#define IEVENT_CRL 0x00020000
	108	#define IEVENT_XFUN 0x00010000
	109	#define IEVENT_RXB0 0x00008000
	110	#define IEVENT_GRSC 0x00000100
	111	#define IEVENT_RXF0 0x00000080
	112
	113	#define IMASK_INIT_CLEAR 0x00000000
	114	#define IMASK_TXEEN 0x00400000
	115	#define IMASK_TXBEN 0x00200000
53677ef1	116	#define IMASK_TXFEN 0x00100000
42d1f039 WD	117	#define IMASK_RXFEN0 0x00000080
42d1f039 WD	118
42d1f039	119	/* Default Attribute fields */
9872b736 BM	120	#define ATTR_INIT_SETTINGS 0x000000c0
9872b736 BM	121	#define ATTRELI_INIT_SETTINGS 0x00000000
42d1f039 WD	122
	123	/* TxBD status field bits */
	124	#define TXBD_READY 0x8000
	125	#define TXBD_PADCRC 0x4000
	126	#define TXBD_WRAP 0x2000
	127	#define TXBD_INTERRUPT 0x1000
	128	#define TXBD_LAST 0x0800
	129	#define TXBD_CRC 0x0400
	130	#define TXBD_DEF 0x0200
	131	#define TXBD_HUGEFRAME 0x0080
	132	#define TXBD_LATECOLLISION 0x0080
	133	#define TXBD_RETRYLIMIT 0x0040
9872b736	134	#define TXBD_RETRYCOUNTMASK 0x003c
42d1f039	135	#define TXBD_UNDERRUN 0x0002
53677ef1	136	#define TXBD_STATS 0x03ff
42d1f039 WD	137
	138	/* RxBD status field bits */
	139	#define RXBD_EMPTY 0x8000
	140	#define RXBD_RO1 0x4000
	141	#define RXBD_WRAP 0x2000
	142	#define RXBD_INTERRUPT 0x1000
	143	#define RXBD_LAST 0x0800
	144	#define RXBD_FIRST 0x0400
	145	#define RXBD_MISS 0x0100
	146	#define RXBD_BROADCAST 0x0080
	147	#define RXBD_MULTICAST 0x0040
	148	#define RXBD_LARGE 0x0020
	149	#define RXBD_NONOCTET 0x0010
	150	#define RXBD_SHORT 0x0008
	151	#define RXBD_CRCERR 0x0004
	152	#define RXBD_OVERRUN 0x0002
	153	#define RXBD_TRUNCATED 0x0001
	154	#define RXBD_STATS 0x003f
	155
9c9141fd	156	struct txbd8 {
9872b736 BM	157	uint16_t status; /* Status Fields */
	158	uint16_t length; /* Buffer length */
	159	uint32_t bufptr; /* Buffer Pointer */
9c9141fd CM	160	};
	161
	162	struct rxbd8 {
9872b736 BM	163	uint16_t status; /* Status Fields */
	164	uint16_t length; /* Buffer Length */
	165	uint32_t bufptr; /* Buffer Pointer */
9c9141fd	166	};
42d1f039	167
82ef75ca	168	struct tsec_rmon_mib {
42d1f039	169	/* Transmit and Receive Counters */
82ef75ca CM	170	u32 tr64; /* Tx/Rx 64-byte Frame Counter */
	171	u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
	172	u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
	173	u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
	174	u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
	175	u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
	176	u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
42d1f039	177	/* Receive Counters */
82ef75ca CM	178	u32 rbyt; /* Receive Byte Counter */
	179	u32 rpkt; /* Receive Packet Counter */
	180	u32 rfcs; /* Receive FCS Error Counter */
	181	u32 rmca; /* Receive Multicast Packet (Counter) */
	182	u32 rbca; /* Receive Broadcast Packet */
	183	u32 rxcf; /* Receive Control Frame Packet */
	184	u32 rxpf; /* Receive Pause Frame Packet */
	185	u32 rxuo; /* Receive Unknown OP Code */
	186	u32 raln; /* Receive Alignment Error */
	187	u32 rflr; /* Receive Frame Length Error */
	188	u32 rcde; /* Receive Code Error */
	189	u32 rcse; /* Receive Carrier Sense Error */
	190	u32 rund; /* Receive Undersize Packet */
	191	u32 rovr; /* Receive Oversize Packet */
	192	u32 rfrg; /* Receive Fragments */
	193	u32 rjbr; /* Receive Jabber */
	194	u32 rdrp; /* Receive Drop */
42d1f039	195	/* Transmit Counters */
82ef75ca CM	196	u32 tbyt; /* Transmit Byte Counter */
	197	u32 tpkt; /* Transmit Packet */
	198	u32 tmca; /* Transmit Multicast Packet */
	199	u32 tbca; /* Transmit Broadcast Packet */
	200	u32 txpf; /* Transmit Pause Control Frame */
	201	u32 tdfr; /* Transmit Deferral Packet */
	202	u32 tedf; /* Transmit Excessive Deferral Packet */
	203	u32 tscl; /* Transmit Single Collision Packet */
42d1f039	204	/* (0x2_n700) */
82ef75ca CM	205	u32 tmcl; /* Transmit Multiple Collision Packet */
	206	u32 tlcl; /* Transmit Late Collision Packet */
	207	u32 txcl; /* Transmit Excessive Collision Packet */
	208	u32 tncl; /* Transmit Total Collision */
	209
	210	u32 res2;
	211
	212	u32 tdrp; /* Transmit Drop Frame */
	213	u32 tjbr; /* Transmit Jabber Frame */
	214	u32 tfcs; /* Transmit FCS Error */
	215	u32 txcf; /* Transmit Control Frame */
	216	u32 tovr; /* Transmit Oversize Frame */
	217	u32 tund; /* Transmit Undersize Frame */
	218	u32 tfrg; /* Transmit Fragments Frame */
42d1f039	219	/* General Registers */
82ef75ca CM	220	u32 car1; /* Carry Register One */
	221	u32 car2; /* Carry Register Two */
	222	u32 cam1; /* Carry Register One Mask */
	223	u32 cam2; /* Carry Register Two Mask */
	224	};
	225
	226	struct tsec_hash_regs {
	227	u32 iaddr0; /* Individual Address Register 0 */
	228	u32 iaddr1; /* Individual Address Register 1 */
	229	u32 iaddr2; /* Individual Address Register 2 */
	230	u32 iaddr3; /* Individual Address Register 3 */
	231	u32 iaddr4; /* Individual Address Register 4 */
	232	u32 iaddr5; /* Individual Address Register 5 */
	233	u32 iaddr6; /* Individual Address Register 6 */
	234	u32 iaddr7; /* Individual Address Register 7 */
	235	u32 res1[24];
	236	u32 gaddr0; /* Group Address Register 0 */
	237	u32 gaddr1; /* Group Address Register 1 */
	238	u32 gaddr2; /* Group Address Register 2 */
	239	u32 gaddr3; /* Group Address Register 3 */
	240	u32 gaddr4; /* Group Address Register 4 */
	241	u32 gaddr5; /* Group Address Register 5 */
	242	u32 gaddr6; /* Group Address Register 6 */
	243	u32 gaddr7; /* Group Address Register 7 */
	244	u32 res2[24];
	245	};
42d1f039	246
aec84bf6	247	struct tsec {
42d1f039	248	/* General Control and Status Registers (0x2_n000) */
82ef75ca	249	u32 res000[4];
42d1f039	250
82ef75ca CM	251	u32 ievent; /* Interrupt Event */
	252	u32 imask; /* Interrupt Mask */
	253	u32 edis; /* Error Disabled */
	254	u32 res01c;
	255	u32 ecntrl; /* Ethernet Control */
	256	u32 minflr; /* Minimum Frame Length */
	257	u32 ptv; /* Pause Time Value */
	258	u32 dmactrl; /* DMA Control */
	259	u32 tbipa; /* TBI PHY Address */
42d1f039	260
82ef75ca CM	261	u32 res034[3];
82ef75ca CM	262	u32 res040[48];
42d1f039 WD	263
42d1f039 WD	264	/* Transmit Control and Status Registers (0x2_n100) */
82ef75ca CM	265	u32 tctrl; /* Transmit Control */
	266	u32 tstat; /* Transmit Status */
	267	u32 res108;
	268	u32 tbdlen; /* Tx BD Data Length */
	269	u32 res110[5];
	270	u32 ctbptr; /* Current TxBD Pointer */
	271	u32 res128[23];
	272	u32 tbptr; /* TxBD Pointer */
	273	u32 res188[30];
42d1f039	274	/* (0x2_n200) */
82ef75ca CM	275	u32 res200;
	276	u32 tbase; /* TxBD Base Address */
	277	u32 res208[42];
	278	u32 ostbd; /* Out of Sequence TxBD */
	279	u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
	280	u32 res2b8[18];
42d1f039 WD	281
42d1f039 WD	282	/* Receive Control and Status Registers (0x2_n300) */
82ef75ca CM	283	u32 rctrl; /* Receive Control */
	284	u32 rstat; /* Receive Status */
	285	u32 res308;
	286	u32 rbdlen; /* RxBD Data Length */
	287	u32 res310[4];
	288	u32 res320;
9872b736	289	u32 crbptr; /* Current Receive Buffer Pointer */
82ef75ca	290	u32 res328[6];
9872b736	291	u32 mrblr; /* Maximum Receive Buffer Length */
82ef75ca	292	u32 res344[16];
9872b736	293	u32 rbptr; /* RxBD Pointer */
82ef75ca	294	u32 res388[30];
42d1f039	295	/* (0x2_n400) */
82ef75ca	296	u32 res400;
9872b736	297	u32 rbase; /* RxBD Base Address */
82ef75ca	298	u32 res408[62];
42d1f039 WD	299
42d1f039 WD	300	/* MAC Registers (0x2_n500) */
82ef75ca CM	301	u32 maccfg1; /* MAC Configuration #1 */
	302	u32 maccfg2; /* MAC Configuration #2 */
	303	u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
	304	u32 hafdup; /* Half-duplex */
	305	u32 maxfrm; /* Maximum Frame */
	306	u32 res514;
	307	u32 res518;
42d1f039	308
82ef75ca	309	u32 res51c;
42d1f039	310
82ef75ca	311	u32 resmdio[6];
42d1f039	312
82ef75ca	313	u32 res538;
42d1f039	314
82ef75ca CM	315	u32 ifstat; /* Interface Status */
	316	u32 macstnaddr1; /* Station Address, part 1 */
	317	u32 macstnaddr2; /* Station Address, part 2 */
	318	u32 res548[46];
42d1f039 WD	319
42d1f039 WD	320	/* (0x2_n600) */
82ef75ca	321	u32 res600[32];
42d1f039 WD	322
42d1f039 WD	323	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
82ef75ca CM	324	struct tsec_rmon_mib rmon;
82ef75ca CM	325	u32 res740[48];
42d1f039 WD	326
42d1f039 WD	327	/* Hash Function Registers (0x2_n800) */
82ef75ca	328	struct tsec_hash_regs hash;
42d1f039	329
82ef75ca	330	u32 res900[128];
42d1f039 WD	331
42d1f039 WD	332	/* Pattern Registers (0x2_nb00) */
82ef75ca CM	333	u32 resb00[62];
	334	u32 attr; /* Default Attribute Register */
	335	u32 attreli; /* Default Attribute Extract Length and Index */
42d1f039 WD	336
42d1f039 WD	337	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
82ef75ca	338	u32 resc00[256];
aec84bf6	339	};
42d1f039	340
9872b736	341	#define TSEC_GIGABIT (1 << 0)
d9b94f28	342
063c1263	343	/* These flags currently only have meaning if we're using the eTSEC */
5f6b1442 PT	344	#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
5f6b1442 PT	345	#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
d9b94f28	346
e677da97 BM	347	#define TX_BUF_CNT 2
e677da97 BM	348
7fb568de HZ	349	struct tsec_data {
	350	u32 mdio_regs_off;
	351	};
	352
97d80fc3	353	struct tsec_private {
e677da97 BM	354	struct txbd8 __iomem txbd[TX_BUF_CNT];
e677da97 BM	355	struct rxbd8 __iomem rxbd[PKTBUFSRX];
aec84bf6 CM	356	struct tsec __iomem *regs;
aec84bf6 CM	357	struct tsec_mii_mng __iomem *phyregs_sgmii;
063c1263 AF	358	struct phy_device *phydev;
	359	phy_interface_t interface;
	360	struct mii_dev *bus;
97d80fc3	361	uint phyaddr;
a1c76c15	362	uint tbiaddr;
063c1263	363	char mii_devname[16];
d9b94f28	364	u32 flags;
362b123f BM	365	uint rx_idx; /* index of the current RX buffer */
362b123f BM	366	uint tx_idx; /* index of the current TX buffer */
9a1d6af5	367	struct udevice *dev;
97d80fc3 WD	368	};
97d80fc3 WD	369
dd3d1f56	370	struct tsec_info_struct {
aec84bf6 CM	371	struct tsec __iomem *regs;
aec84bf6 CM	372	struct tsec_mii_mng __iomem *miiregs_sgmii;
75b9d4ae	373	char *devname;
063c1263 AF	374	char *mii_devname;
063c1263 AF	375	phy_interface_t interface;
dd3d1f56 AF	376	unsigned int phyaddr;
dd3d1f56 AF	377	u32 flags;
dd3d1f56 AF	378	};
dd3d1f56 AF	379
42d1f039	380	#endif /* __TSEC_H */