[thirdparty/u-boot.git] / include / tsec.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  tsec.h
 *
 *  Driver for the Motorola Triple Speed Ethernet Controller
 *
 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
 * (C) Copyright 2003, Motorola, Inc.
 * maintained by Xianghua Xiao (x.xiao@motorola.com)
 * author Andy Fleming
 */

#ifndef __TSEC_H
#define __TSEC_H

#include <net.h>
#include <config.h>
#include <phy.h>

#ifndef CONFIG_DM_ETH

#ifdef CONFIG_ARCH_LS1021A
#define TSEC_SIZE		0x40000
#define TSEC_MDIO_OFFSET	0x40000
#else
#define TSEC_SIZE 		0x01000
#define TSEC_MDIO_OFFSET	0x01000
#endif

#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)

#define TSEC_GET_REGS(num, offset) \
	(struct tsec __iomem *)\
	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))

#define TSEC_GET_REGS_BASE(num) \
	TSEC_GET_REGS((num), TSEC_SIZE)

#define TSEC_GET_MDIO_REGS(num, offset) \
	(struct tsec_mii_mng __iomem *)\
	(CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))

#define TSEC_GET_MDIO_REGS_BASE(num) \
	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)

#define DEFAULT_MII_NAME "FSL_MDIO"

#define STD_TSEC_INFO(num) \
{			\
	.regs = TSEC_GET_REGS_BASE(num), \
	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
	.devname = CONFIG_TSEC##num##_NAME, \
	.phyaddr = TSEC##num##_PHY_ADDR, \
	.flags = TSEC##num##_FLAGS, \
	.mii_devname = DEFAULT_MII_NAME \
}

#define SET_STD_TSEC_INFO(x, num) \
{			\
	x.regs = TSEC_GET_REGS_BASE(num); \
	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
	x.devname = CONFIG_TSEC##num##_NAME; \
	x.phyaddr = TSEC##num##_PHY_ADDR; \
	x.flags = TSEC##num##_FLAGS;\
	x.mii_devname = DEFAULT_MII_NAME;\
}

#endif /* CONFIG_DM_ETH */

#define MAC_ADDR_LEN		6

/* #define TSEC_TIMEOUT	1000000 */
#define TSEC_TIMEOUT		1000
#define TOUT_LOOP		1000000

/* TBI register addresses */
#define TBI_CR			0x00
#define TBI_SR			0x01
#define TBI_ANA			0x04
#define TBI_ANLPBPA		0x05
#define TBI_ANEX		0x06
#define TBI_TBICON		0x11

/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT	0x0020
#define TBIANA_ASYMMETRIC_PAUSE	0x0100
#define TBIANA_SYMMETRIC_PAUSE	0x0080
#define TBIANA_HALF_DUPLEX	0x0040
#define TBIANA_FULL_DUPLEX	0x0020
#define TBICR_PHY_RESET		0x8000
#define TBICR_ANEG_ENABLE	0x1000
#define TBICR_RESTART_ANEG	0x0200
#define TBICR_FULL_DUPLEX	0x0100
#define TBICR_SPEED1_SET	0x0040

/* MAC register bits */
#define MACCFG1_SOFT_RESET	0x80000000
#define MACCFG1_RESET_RX_MC	0x00080000
#define MACCFG1_RESET_TX_MC	0x00040000
#define MACCFG1_RESET_RX_FUN	0x00020000
#define MACCFG1_RESET_TX_FUN	0x00010000
#define MACCFG1_LOOPBACK	0x00000100
#define MACCFG1_RX_FLOW		0x00000020
#define MACCFG1_TX_FLOW		0x00000010
#define MACCFG1_SYNCD_RX_EN	0x00000008
#define MACCFG1_RX_EN		0x00000004
#define MACCFG1_SYNCD_TX_EN	0x00000002
#define MACCFG1_TX_EN		0x00000001

#define MACCFG2_INIT_SETTINGS	0x00007205
#define MACCFG2_FULL_DUPLEX	0x00000001
#define MACCFG2_IF		0x00000300
#define MACCFG2_GMII		0x00000200
#define MACCFG2_MII		0x00000100

#define ECNTRL_INIT_SETTINGS	0x00001000
#define ECNTRL_TBI_MODE		0x00000020
#define ECNTRL_REDUCED_MODE	0x00000010
#define ECNTRL_R100		0x00000008
#define ECNTRL_REDUCED_MII_MODE	0x00000004
#define ECNTRL_SGMII_MODE	0x00000002

#ifndef CONFIG_SYS_TBIPA_VALUE
# define CONFIG_SYS_TBIPA_VALUE	0x1f
#endif

#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN

#define MINFLR_INIT_SETTINGS	0x00000040

#define DMACTRL_INIT_SETTINGS	0x000000c3
#define DMACTRL_GRS		0x00000010
#define DMACTRL_GTS		0x00000008
#define DMACTRL_LE		0x00008000

#define TSTAT_CLEAR_THALT	0x80000000
#define RSTAT_CLEAR_RHALT	0x00800000

#define IEVENT_INIT_CLEAR	0xffffffff
#define IEVENT_BABR		0x80000000
#define IEVENT_RXC		0x40000000
#define IEVENT_BSY		0x20000000
#define IEVENT_EBERR		0x10000000
#define IEVENT_MSRO		0x04000000
#define IEVENT_GTSC		0x02000000
#define IEVENT_BABT		0x01000000
#define IEVENT_TXC		0x00800000
#define IEVENT_TXE		0x00400000
#define IEVENT_TXB		0x00200000
#define IEVENT_TXF		0x00100000
#define IEVENT_IE		0x00080000
#define IEVENT_LC		0x00040000
#define IEVENT_CRL		0x00020000
#define IEVENT_XFUN		0x00010000
#define IEVENT_RXB0		0x00008000
#define IEVENT_GRSC		0x00000100
#define IEVENT_RXF0		0x00000080

#define IMASK_INIT_CLEAR	0x00000000
#define IMASK_TXEEN		0x00400000
#define IMASK_TXBEN		0x00200000
#define IMASK_TXFEN		0x00100000
#define IMASK_RXFEN0		0x00000080

/* Default Attribute fields */
#define ATTR_INIT_SETTINGS	0x000000c0
#define ATTRELI_INIT_SETTINGS	0x00000000

/* TxBD status field bits */
#define TXBD_READY		0x8000
#define TXBD_PADCRC		0x4000
#define TXBD_WRAP		0x2000
#define TXBD_INTERRUPT		0x1000
#define TXBD_LAST		0x0800
#define TXBD_CRC		0x0400
#define TXBD_DEF		0x0200
#define TXBD_HUGEFRAME		0x0080
#define TXBD_LATECOLLISION	0x0080
#define TXBD_RETRYLIMIT		0x0040
#define TXBD_RETRYCOUNTMASK	0x003c
#define TXBD_UNDERRUN		0x0002
#define TXBD_STATS		0x03ff

/* RxBD status field bits */
#define RXBD_EMPTY		0x8000
#define RXBD_RO1		0x4000
#define RXBD_WRAP		0x2000
#define RXBD_INTERRUPT		0x1000
#define RXBD_LAST		0x0800
#define RXBD_FIRST		0x0400
#define RXBD_MISS		0x0100
#define RXBD_BROADCAST		0x0080
#define RXBD_MULTICAST		0x0040
#define RXBD_LARGE		0x0020
#define RXBD_NONOCTET		0x0010
#define RXBD_SHORT		0x0008
#define RXBD_CRCERR		0x0004
#define RXBD_OVERRUN		0x0002
#define RXBD_TRUNCATED		0x0001
#define RXBD_STATS		0x003f

struct txbd8 {
	uint16_t status;	/* Status Fields */
	uint16_t length;	/* Buffer length */
	uint32_t bufptr;	/* Buffer Pointer */
};

struct rxbd8 {
	uint16_t status;	/* Status Fields */
	uint16_t length;	/* Buffer Length */
	uint32_t bufptr;	/* Buffer Pointer */
};

struct tsec_rmon_mib {
	/* Transmit and Receive Counters */
	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
	/* Receive Counters */
	u32	rbyt;		/* Receive Byte Counter */
	u32	rpkt;		/* Receive Packet Counter */
	u32	rfcs;		/* Receive FCS Error Counter */
	u32	rmca;		/* Receive Multicast Packet (Counter) */
	u32	rbca;		/* Receive Broadcast Packet */
	u32	rxcf;		/* Receive Control Frame Packet */
	u32	rxpf;		/* Receive Pause Frame Packet */
	u32	rxuo;		/* Receive Unknown OP Code */
	u32	raln;		/* Receive Alignment Error */
	u32	rflr;		/* Receive Frame Length Error */
	u32	rcde;		/* Receive Code Error */
	u32	rcse;		/* Receive Carrier Sense Error */
	u32	rund;		/* Receive Undersize Packet */
	u32	rovr;		/* Receive Oversize Packet */
	u32	rfrg;		/* Receive Fragments */
	u32	rjbr;		/* Receive Jabber */
	u32	rdrp;		/* Receive Drop */
	/* Transmit Counters */
	u32	tbyt;		/* Transmit Byte Counter */
	u32	tpkt;		/* Transmit Packet */
	u32	tmca;		/* Transmit Multicast Packet */
	u32	tbca;		/* Transmit Broadcast Packet */
	u32	txpf;		/* Transmit Pause Control Frame */
	u32	tdfr;		/* Transmit Deferral Packet */
	u32	tedf;		/* Transmit Excessive Deferral Packet */
	u32	tscl;		/* Transmit Single Collision Packet */
	/* (0x2_n700) */
	u32	tmcl;		/* Transmit Multiple Collision Packet */
	u32	tlcl;		/* Transmit Late Collision Packet */
	u32	txcl;		/* Transmit Excessive Collision Packet */
	u32	tncl;		/* Transmit Total Collision */

	u32	res2;

	u32	tdrp;		/* Transmit Drop Frame */
	u32	tjbr;		/* Transmit Jabber Frame */
	u32	tfcs;		/* Transmit FCS Error */
	u32	txcf;		/* Transmit Control Frame */
	u32	tovr;		/* Transmit Oversize Frame */
	u32	tund;		/* Transmit Undersize Frame */
	u32	tfrg;		/* Transmit Fragments Frame */
	/* General Registers */
	u32	car1;		/* Carry Register One */
	u32	car2;		/* Carry Register Two */
	u32	cam1;		/* Carry Register One Mask */
	u32	cam2;		/* Carry Register Two Mask */
};

struct tsec_hash_regs {
	u32	iaddr0;		/* Individual Address Register 0 */
	u32	iaddr1;		/* Individual Address Register 1 */
	u32	iaddr2;		/* Individual Address Register 2 */
	u32	iaddr3;		/* Individual Address Register 3 */
	u32	iaddr4;		/* Individual Address Register 4 */
	u32	iaddr5;		/* Individual Address Register 5 */
	u32	iaddr6;		/* Individual Address Register 6 */
	u32	iaddr7;		/* Individual Address Register 7 */
	u32	res1[24];
	u32	gaddr0;		/* Group Address Register 0 */
	u32	gaddr1;		/* Group Address Register 1 */
	u32	gaddr2;		/* Group Address Register 2 */
	u32	gaddr3;		/* Group Address Register 3 */
	u32	gaddr4;		/* Group Address Register 4 */
	u32	gaddr5;		/* Group Address Register 5 */
	u32	gaddr6;		/* Group Address Register 6 */
	u32	gaddr7;		/* Group Address Register 7 */
	u32	res2[24];
};

struct tsec {
	/* General Control and Status Registers (0x2_n000) */
	u32	res000[4];

	u32	ievent;		/* Interrupt Event */
	u32	imask;		/* Interrupt Mask */
	u32	edis;		/* Error Disabled */
	u32	res01c;
	u32	ecntrl;		/* Ethernet Control */
	u32	minflr;		/* Minimum Frame Length */
	u32	ptv;		/* Pause Time Value */
	u32	dmactrl;	/* DMA Control */
	u32	tbipa;		/* TBI PHY Address */

	u32	res034[3];
	u32	res040[48];

	/* Transmit Control and Status Registers (0x2_n100) */
	u32	tctrl;		/* Transmit Control */
	u32	tstat;		/* Transmit Status */
	u32	res108;
	u32	tbdlen;		/* Tx BD Data Length */
	u32	res110[5];
	u32	ctbptr;		/* Current TxBD Pointer */
	u32	res128[23];
	u32	tbptr;		/* TxBD Pointer */
	u32	res188[30];
	/* (0x2_n200) */
	u32	res200;
	u32	tbase;		/* TxBD Base Address */
	u32	res208[42];
	u32	ostbd;		/* Out of Sequence TxBD */
	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
	u32	res2b8[18];

	/* Receive Control and Status Registers (0x2_n300) */
	u32	rctrl;		/* Receive Control */
	u32	rstat;		/* Receive Status */
	u32	res308;
	u32	rbdlen;		/* RxBD Data Length */
	u32	res310[4];
	u32	res320;
	u32	crbptr;		/* Current Receive Buffer Pointer */
	u32	res328[6];
	u32	mrblr;		/* Maximum Receive Buffer Length */
	u32	res344[16];
	u32	rbptr;		/* RxBD Pointer */
	u32	res388[30];
	/* (0x2_n400) */
	u32	res400;
	u32	rbase;		/* RxBD Base Address */
	u32	res408[62];

	/* MAC Registers (0x2_n500) */
	u32	maccfg1;	/* MAC Configuration #1 */
	u32	maccfg2;	/* MAC Configuration #2 */
	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
	u32	hafdup;		/* Half-duplex */
	u32	maxfrm;		/* Maximum Frame */
	u32	res514;
	u32	res518;

	u32	res51c;

	u32	resmdio[6];

	u32	res538;

	u32	ifstat;		/* Interface Status */
	u32	macstnaddr1;	/* Station Address, part 1 */
	u32	macstnaddr2;	/* Station Address, part 2 */
	u32	res548[46];

	/* (0x2_n600) */
	u32	res600[32];

	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
	struct tsec_rmon_mib	rmon;
	u32	res740[48];

	/* Hash Function Registers (0x2_n800) */
	struct tsec_hash_regs	hash;

	u32	res900[128];

	/* Pattern Registers (0x2_nb00) */
	u32	resb00[62];
	u32	attr; /* Default Attribute Register */
	u32	attreli; /* Default Attribute Extract Length and Index */

	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
	u32	resc00[256];
};

#define TSEC_GIGABIT	(1 << 0)

/* These flags currently only have meaning if we're using the eTSEC */
#define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
#define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */

#define TX_BUF_CNT	2

struct tsec_private {
	struct txbd8 __iomem txbd[TX_BUF_CNT];
	struct rxbd8 __iomem rxbd[PKTBUFSRX];
	struct tsec __iomem *regs;
	struct tsec_mii_mng __iomem *phyregs_sgmii;
	struct phy_device *phydev;
	phy_interface_t interface;
	struct mii_dev *bus;
	uint phyaddr;
	uint tbiaddr;
	char mii_devname[16];
	u32 flags;
	uint rx_idx;	/* index of the current RX buffer */
	uint tx_idx;	/* index of the current TX buffer */
#ifndef CONFIG_DM_ETH
	struct eth_device *dev;
#else
	struct udevice *dev;
#endif
};

struct tsec_info_struct {
	struct tsec __iomem *regs;
	struct tsec_mii_mng __iomem *miiregs_sgmii;
	char *devname;
	char *mii_devname;
	phy_interface_t interface;
	unsigned int phyaddr;
	u32 flags;
};

#ifndef CONFIG_DM_ETH
int tsec_standard_init(bd_t *bis);
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
#endif

#endif /* __TSEC_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
42d1f039 WD	2	/*
	3	* tsec.h
	4	*
	5	* Driver for the Motorola Triple Speed Ethernet Controller
	6	*
aec84bf6	7	* Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
42d1f039 WD	8	* (C) Copyright 2003, Motorola, Inc.
	9	* maintained by Xianghua Xiao (x.xiao@motorola.com)
	10	* author Andy Fleming
42d1f039 WD	11	*/
	12
	13	#ifndef __TSEC_H
	14	#define __TSEC_H
	15
	16	#include <net.h>
f046ccd1	17	#include <config.h>
063c1263	18	#include <phy.h>
f046ccd1	19
9a1d6af5 BM	20	#ifndef CONFIG_DM_ETH
9a1d6af5 BM	21
73fb5838	22	#ifdef CONFIG_ARCH_LS1021A
52d00a81 AW	23	#define TSEC_SIZE 0x40000
	24	#define TSEC_MDIO_OFFSET 0x40000
	25	#else
b9e186fc SG	26	#define TSEC_SIZE 0x01000
b9e186fc SG	27	#define TSEC_MDIO_OFFSET 0x01000
52d00a81	28	#endif
f046ccd1	29
40ac3d46	30	#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
063c1263	31
aec84bf6 CM	32	#define TSEC_GET_REGS(num, offset) \
	33	(struct tsec __iomem *)\
	34	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
	35
	36	#define TSEC_GET_REGS_BASE(num) \
	37	TSEC_GET_REGS((num), TSEC_SIZE)
	38
	39	#define TSEC_GET_MDIO_REGS(num, offset) \
	40	(struct tsec_mii_mng __iomem *)\
	41	(CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
	42
	43	#define TSEC_GET_MDIO_REGS_BASE(num) \
	44	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
	45
063c1263 AF	46	#define DEFAULT_MII_NAME "FSL_MDIO"
063c1263 AF	47
75b9d4ae AF	48	#define STD_TSEC_INFO(num) \
75b9d4ae AF	49	{ \
aec84bf6 CM	50	.regs = TSEC_GET_REGS_BASE(num), \
aec84bf6 CM	51	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
75b9d4ae AF	52	.devname = CONFIG_TSEC##num##_NAME, \
75b9d4ae AF	53	.phyaddr = TSEC##num##_PHY_ADDR, \
063c1263 AF	54	.flags = TSEC##num##_FLAGS, \
063c1263 AF	55	.mii_devname = DEFAULT_MII_NAME \
75b9d4ae AF	56	}
	57
	58	#define SET_STD_TSEC_INFO(x, num) \
	59	{ \
aec84bf6 CM	60	x.regs = TSEC_GET_REGS_BASE(num); \
aec84bf6 CM	61	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
75b9d4ae AF	62	x.devname = CONFIG_TSEC##num##_NAME; \
	63	x.phyaddr = TSEC##num##_PHY_ADDR; \
	64	x.flags = TSEC##num##_FLAGS;\
063c1263	65	x.mii_devname = DEFAULT_MII_NAME;\
75b9d4ae AF	66	}
75b9d4ae AF	67
9a1d6af5 BM	68	#endif /* CONFIG_DM_ETH */
9a1d6af5 BM	69
9872b736	70	#define MAC_ADDR_LEN 6
42d1f039	71
53677ef1	72	/* #define TSEC_TIMEOUT 1000000 */
9872b736 BM	73	#define TSEC_TIMEOUT 1000
9872b736 BM	74	#define TOUT_LOOP 1000000
42d1f039	75
2abe361c AF	76	/* TBI register addresses */
	77	#define TBI_CR 0x00
	78	#define TBI_SR 0x01
	79	#define TBI_ANA 0x04
	80	#define TBI_ANLPBPA 0x05
	81	#define TBI_ANEX 0x06
	82	#define TBI_TBICON 0x11
	83
	84	/* TBI MDIO register bit fields*/
	85	#define TBICON_CLK_SELECT 0x0020
9872b736 BM	86	#define TBIANA_ASYMMETRIC_PAUSE 0x0100
9872b736 BM	87	#define TBIANA_SYMMETRIC_PAUSE 0x0080
2abe361c AF	88	#define TBIANA_HALF_DUPLEX 0x0040
	89	#define TBIANA_FULL_DUPLEX 0x0020
	90	#define TBICR_PHY_RESET 0x8000
	91	#define TBICR_ANEG_ENABLE 0x1000
	92	#define TBICR_RESTART_ANEG 0x0200
	93	#define TBICR_FULL_DUPLEX 0x0100
	94	#define TBICR_SPEED1_SET 0x0040
	95
42d1f039 WD	96	/* MAC register bits */
	97	#define MACCFG1_SOFT_RESET 0x80000000
	98	#define MACCFG1_RESET_RX_MC 0x00080000
	99	#define MACCFG1_RESET_TX_MC 0x00040000
	100	#define MACCFG1_RESET_RX_FUN 0x00020000
9872b736	101	#define MACCFG1_RESET_TX_FUN 0x00010000
42d1f039 WD	102	#define MACCFG1_LOOPBACK 0x00000100
	103	#define MACCFG1_RX_FLOW 0x00000020
	104	#define MACCFG1_TX_FLOW 0x00000010
	105	#define MACCFG1_SYNCD_RX_EN 0x00000008
	106	#define MACCFG1_RX_EN 0x00000004
	107	#define MACCFG1_SYNCD_TX_EN 0x00000002
	108	#define MACCFG1_TX_EN 0x00000001
	109
	110	#define MACCFG2_INIT_SETTINGS 0x00007205
	111	#define MACCFG2_FULL_DUPLEX 0x00000001
53677ef1	112	#define MACCFG2_IF 0x00000300
97d80fc3	113	#define MACCFG2_GMII 0x00000200
53677ef1	114	#define MACCFG2_MII 0x00000100
42d1f039 WD	115
42d1f039 WD	116	#define ECNTRL_INIT_SETTINGS 0x00001000
53677ef1	117	#define ECNTRL_TBI_MODE 0x00000020
063c1263	118	#define ECNTRL_REDUCED_MODE 0x00000010
d9b94f28	119	#define ECNTRL_R100 0x00000008
063c1263	120	#define ECNTRL_REDUCED_MII_MODE 0x00000004
81f481ca	121	#define ECNTRL_SGMII_MODE 0x00000002
42d1f039	122
6d0f6bcf	123	#ifndef CONFIG_SYS_TBIPA_VALUE
9872b736	124	# define CONFIG_SYS_TBIPA_VALUE 0x1f
dcb84b72	125	#endif
42d1f039 WD	126
	127	#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
	128
	129	#define MINFLR_INIT_SETTINGS 0x00000040
	130
53677ef1 WD	131	#define DMACTRL_INIT_SETTINGS 0x000000c3
	132	#define DMACTRL_GRS 0x00000010
	133	#define DMACTRL_GTS 0x00000008
52d00a81	134	#define DMACTRL_LE 0x00008000
42d1f039	135
53677ef1 WD	136	#define TSTAT_CLEAR_THALT 0x80000000
53677ef1 WD	137	#define RSTAT_CLEAR_RHALT 0x00800000
42d1f039	138
42d1f039 WD	139	#define IEVENT_INIT_CLEAR 0xffffffff
	140	#define IEVENT_BABR 0x80000000
	141	#define IEVENT_RXC 0x40000000
	142	#define IEVENT_BSY 0x20000000
	143	#define IEVENT_EBERR 0x10000000
	144	#define IEVENT_MSRO 0x04000000
	145	#define IEVENT_GTSC 0x02000000
	146	#define IEVENT_BABT 0x01000000
	147	#define IEVENT_TXC 0x00800000
	148	#define IEVENT_TXE 0x00400000
	149	#define IEVENT_TXB 0x00200000
	150	#define IEVENT_TXF 0x00100000
	151	#define IEVENT_IE 0x00080000
	152	#define IEVENT_LC 0x00040000
	153	#define IEVENT_CRL 0x00020000
	154	#define IEVENT_XFUN 0x00010000
	155	#define IEVENT_RXB0 0x00008000
	156	#define IEVENT_GRSC 0x00000100
	157	#define IEVENT_RXF0 0x00000080
	158
	159	#define IMASK_INIT_CLEAR 0x00000000
	160	#define IMASK_TXEEN 0x00400000
	161	#define IMASK_TXBEN 0x00200000
53677ef1	162	#define IMASK_TXFEN 0x00100000
42d1f039 WD	163	#define IMASK_RXFEN0 0x00000080
42d1f039 WD	164
42d1f039	165	/* Default Attribute fields */
9872b736 BM	166	#define ATTR_INIT_SETTINGS 0x000000c0
9872b736 BM	167	#define ATTRELI_INIT_SETTINGS 0x00000000
42d1f039 WD	168
	169	/* TxBD status field bits */
	170	#define TXBD_READY 0x8000
	171	#define TXBD_PADCRC 0x4000
	172	#define TXBD_WRAP 0x2000
	173	#define TXBD_INTERRUPT 0x1000
	174	#define TXBD_LAST 0x0800
	175	#define TXBD_CRC 0x0400
	176	#define TXBD_DEF 0x0200
	177	#define TXBD_HUGEFRAME 0x0080
	178	#define TXBD_LATECOLLISION 0x0080
	179	#define TXBD_RETRYLIMIT 0x0040
9872b736	180	#define TXBD_RETRYCOUNTMASK 0x003c
42d1f039	181	#define TXBD_UNDERRUN 0x0002
53677ef1	182	#define TXBD_STATS 0x03ff
42d1f039 WD	183
	184	/* RxBD status field bits */
	185	#define RXBD_EMPTY 0x8000
	186	#define RXBD_RO1 0x4000
	187	#define RXBD_WRAP 0x2000
	188	#define RXBD_INTERRUPT 0x1000
	189	#define RXBD_LAST 0x0800
	190	#define RXBD_FIRST 0x0400
	191	#define RXBD_MISS 0x0100
	192	#define RXBD_BROADCAST 0x0080
	193	#define RXBD_MULTICAST 0x0040
	194	#define RXBD_LARGE 0x0020
	195	#define RXBD_NONOCTET 0x0010
	196	#define RXBD_SHORT 0x0008
	197	#define RXBD_CRCERR 0x0004
	198	#define RXBD_OVERRUN 0x0002
	199	#define RXBD_TRUNCATED 0x0001
	200	#define RXBD_STATS 0x003f
	201
9c9141fd	202	struct txbd8 {
9872b736 BM	203	uint16_t status; /* Status Fields */
	204	uint16_t length; /* Buffer length */
	205	uint32_t bufptr; /* Buffer Pointer */
9c9141fd CM	206	};
	207
	208	struct rxbd8 {
9872b736 BM	209	uint16_t status; /* Status Fields */
	210	uint16_t length; /* Buffer Length */
	211	uint32_t bufptr; /* Buffer Pointer */
9c9141fd	212	};
42d1f039	213
82ef75ca	214	struct tsec_rmon_mib {
42d1f039	215	/* Transmit and Receive Counters */
82ef75ca CM	216	u32 tr64; /* Tx/Rx 64-byte Frame Counter */
	217	u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
	218	u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
	219	u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
	220	u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
	221	u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
	222	u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
42d1f039	223	/* Receive Counters */
82ef75ca CM	224	u32 rbyt; /* Receive Byte Counter */
	225	u32 rpkt; /* Receive Packet Counter */
	226	u32 rfcs; /* Receive FCS Error Counter */
	227	u32 rmca; /* Receive Multicast Packet (Counter) */
	228	u32 rbca; /* Receive Broadcast Packet */
	229	u32 rxcf; /* Receive Control Frame Packet */
	230	u32 rxpf; /* Receive Pause Frame Packet */
	231	u32 rxuo; /* Receive Unknown OP Code */
	232	u32 raln; /* Receive Alignment Error */
	233	u32 rflr; /* Receive Frame Length Error */
	234	u32 rcde; /* Receive Code Error */
	235	u32 rcse; /* Receive Carrier Sense Error */
	236	u32 rund; /* Receive Undersize Packet */
	237	u32 rovr; /* Receive Oversize Packet */
	238	u32 rfrg; /* Receive Fragments */
	239	u32 rjbr; /* Receive Jabber */
	240	u32 rdrp; /* Receive Drop */
42d1f039	241	/* Transmit Counters */
82ef75ca CM	242	u32 tbyt; /* Transmit Byte Counter */
	243	u32 tpkt; /* Transmit Packet */
	244	u32 tmca; /* Transmit Multicast Packet */
	245	u32 tbca; /* Transmit Broadcast Packet */
	246	u32 txpf; /* Transmit Pause Control Frame */
	247	u32 tdfr; /* Transmit Deferral Packet */
	248	u32 tedf; /* Transmit Excessive Deferral Packet */
	249	u32 tscl; /* Transmit Single Collision Packet */
42d1f039	250	/* (0x2_n700) */
82ef75ca CM	251	u32 tmcl; /* Transmit Multiple Collision Packet */
	252	u32 tlcl; /* Transmit Late Collision Packet */
	253	u32 txcl; /* Transmit Excessive Collision Packet */
	254	u32 tncl; /* Transmit Total Collision */
	255
	256	u32 res2;
	257
	258	u32 tdrp; /* Transmit Drop Frame */
	259	u32 tjbr; /* Transmit Jabber Frame */
	260	u32 tfcs; /* Transmit FCS Error */
	261	u32 txcf; /* Transmit Control Frame */
	262	u32 tovr; /* Transmit Oversize Frame */
	263	u32 tund; /* Transmit Undersize Frame */
	264	u32 tfrg; /* Transmit Fragments Frame */
42d1f039	265	/* General Registers */
82ef75ca CM	266	u32 car1; /* Carry Register One */
	267	u32 car2; /* Carry Register Two */
	268	u32 cam1; /* Carry Register One Mask */
	269	u32 cam2; /* Carry Register Two Mask */
	270	};
	271
	272	struct tsec_hash_regs {
	273	u32 iaddr0; /* Individual Address Register 0 */
	274	u32 iaddr1; /* Individual Address Register 1 */
	275	u32 iaddr2; /* Individual Address Register 2 */
	276	u32 iaddr3; /* Individual Address Register 3 */
	277	u32 iaddr4; /* Individual Address Register 4 */
	278	u32 iaddr5; /* Individual Address Register 5 */
	279	u32 iaddr6; /* Individual Address Register 6 */
	280	u32 iaddr7; /* Individual Address Register 7 */
	281	u32 res1[24];
	282	u32 gaddr0; /* Group Address Register 0 */
	283	u32 gaddr1; /* Group Address Register 1 */
	284	u32 gaddr2; /* Group Address Register 2 */
	285	u32 gaddr3; /* Group Address Register 3 */
	286	u32 gaddr4; /* Group Address Register 4 */
	287	u32 gaddr5; /* Group Address Register 5 */
	288	u32 gaddr6; /* Group Address Register 6 */
	289	u32 gaddr7; /* Group Address Register 7 */
	290	u32 res2[24];
	291	};
42d1f039	292
aec84bf6	293	struct tsec {
42d1f039	294	/* General Control and Status Registers (0x2_n000) */
82ef75ca	295	u32 res000[4];
42d1f039	296
82ef75ca CM	297	u32 ievent; /* Interrupt Event */
	298	u32 imask; /* Interrupt Mask */
	299	u32 edis; /* Error Disabled */
	300	u32 res01c;
	301	u32 ecntrl; /* Ethernet Control */
	302	u32 minflr; /* Minimum Frame Length */
	303	u32 ptv; /* Pause Time Value */
	304	u32 dmactrl; /* DMA Control */
	305	u32 tbipa; /* TBI PHY Address */
42d1f039	306
82ef75ca CM	307	u32 res034[3];
82ef75ca CM	308	u32 res040[48];
42d1f039 WD	309
42d1f039 WD	310	/* Transmit Control and Status Registers (0x2_n100) */
82ef75ca CM	311	u32 tctrl; /* Transmit Control */
	312	u32 tstat; /* Transmit Status */
	313	u32 res108;
	314	u32 tbdlen; /* Tx BD Data Length */
	315	u32 res110[5];
	316	u32 ctbptr; /* Current TxBD Pointer */
	317	u32 res128[23];
	318	u32 tbptr; /* TxBD Pointer */
	319	u32 res188[30];
42d1f039	320	/* (0x2_n200) */
82ef75ca CM	321	u32 res200;
	322	u32 tbase; /* TxBD Base Address */
	323	u32 res208[42];
	324	u32 ostbd; /* Out of Sequence TxBD */
	325	u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
	326	u32 res2b8[18];
42d1f039 WD	327
42d1f039 WD	328	/* Receive Control and Status Registers (0x2_n300) */
82ef75ca CM	329	u32 rctrl; /* Receive Control */
	330	u32 rstat; /* Receive Status */
	331	u32 res308;
	332	u32 rbdlen; /* RxBD Data Length */
	333	u32 res310[4];
	334	u32 res320;
9872b736	335	u32 crbptr; /* Current Receive Buffer Pointer */
82ef75ca	336	u32 res328[6];
9872b736	337	u32 mrblr; /* Maximum Receive Buffer Length */
82ef75ca	338	u32 res344[16];
9872b736	339	u32 rbptr; /* RxBD Pointer */
82ef75ca	340	u32 res388[30];
42d1f039	341	/* (0x2_n400) */
82ef75ca	342	u32 res400;
9872b736	343	u32 rbase; /* RxBD Base Address */
82ef75ca	344	u32 res408[62];
42d1f039 WD	345
42d1f039 WD	346	/* MAC Registers (0x2_n500) */
82ef75ca CM	347	u32 maccfg1; /* MAC Configuration #1 */
	348	u32 maccfg2; /* MAC Configuration #2 */
	349	u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
	350	u32 hafdup; /* Half-duplex */
	351	u32 maxfrm; /* Maximum Frame */
	352	u32 res514;
	353	u32 res518;
42d1f039	354
82ef75ca	355	u32 res51c;
42d1f039	356
82ef75ca	357	u32 resmdio[6];
42d1f039	358
82ef75ca	359	u32 res538;
42d1f039	360
82ef75ca CM	361	u32 ifstat; /* Interface Status */
	362	u32 macstnaddr1; /* Station Address, part 1 */
	363	u32 macstnaddr2; /* Station Address, part 2 */
	364	u32 res548[46];
42d1f039 WD	365
42d1f039 WD	366	/* (0x2_n600) */
82ef75ca	367	u32 res600[32];
42d1f039 WD	368
42d1f039 WD	369	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
82ef75ca CM	370	struct tsec_rmon_mib rmon;
82ef75ca CM	371	u32 res740[48];
42d1f039 WD	372
42d1f039 WD	373	/* Hash Function Registers (0x2_n800) */
82ef75ca	374	struct tsec_hash_regs hash;
42d1f039	375
82ef75ca	376	u32 res900[128];
42d1f039 WD	377
42d1f039 WD	378	/* Pattern Registers (0x2_nb00) */
82ef75ca CM	379	u32 resb00[62];
	380	u32 attr; /* Default Attribute Register */
	381	u32 attreli; /* Default Attribute Extract Length and Index */
42d1f039 WD	382
42d1f039 WD	383	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
82ef75ca	384	u32 resc00[256];
aec84bf6	385	};
42d1f039	386
9872b736	387	#define TSEC_GIGABIT (1 << 0)
d9b94f28	388
063c1263	389	/* These flags currently only have meaning if we're using the eTSEC */
5f6b1442 PT	390	#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
5f6b1442 PT	391	#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
d9b94f28	392
e677da97 BM	393	#define TX_BUF_CNT 2
e677da97 BM	394
97d80fc3	395	struct tsec_private {
e677da97 BM	396	struct txbd8 __iomem txbd[TX_BUF_CNT];
e677da97 BM	397	struct rxbd8 __iomem rxbd[PKTBUFSRX];
aec84bf6 CM	398	struct tsec __iomem *regs;
aec84bf6 CM	399	struct tsec_mii_mng __iomem *phyregs_sgmii;
063c1263 AF	400	struct phy_device *phydev;
	401	phy_interface_t interface;
	402	struct mii_dev *bus;
97d80fc3	403	uint phyaddr;
a1c76c15	404	uint tbiaddr;
063c1263	405	char mii_devname[16];
d9b94f28	406	u32 flags;
362b123f BM	407	uint rx_idx; /* index of the current RX buffer */
362b123f BM	408	uint tx_idx; /* index of the current TX buffer */
9a1d6af5	409	#ifndef CONFIG_DM_ETH
56a27a1e	410	struct eth_device *dev;
9a1d6af5 BM	411	#else
	412	struct udevice *dev;
	413	#endif
97d80fc3 WD	414	};
97d80fc3 WD	415
dd3d1f56	416	struct tsec_info_struct {
aec84bf6 CM	417	struct tsec __iomem *regs;
aec84bf6 CM	418	struct tsec_mii_mng __iomem *miiregs_sgmii;
75b9d4ae	419	char *devname;
063c1263 AF	420	char *mii_devname;
063c1263 AF	421	phy_interface_t interface;
dd3d1f56 AF	422	unsigned int phyaddr;
dd3d1f56 AF	423	u32 flags;
dd3d1f56 AF	424	};
dd3d1f56 AF	425
9a1d6af5	426	#ifndef CONFIG_DM_ETH
75b9d4ae AF	427	int tsec_standard_init(bd_t *bis);
75b9d4ae AF	428	int tsec_eth_init(bd_t bis, struct tsec_info_struct tsec_info, int num);
9a1d6af5	429	#endif
75b9d4ae	430
42d1f039	431	#endif /* __TSEC_H */