]>
Commit | Line | Data |
---|---|---|
42d1f039 WD |
1 | /* |
2 | * tsec.h | |
3 | * | |
4 | * Driver for the Motorola Triple Speed Ethernet Controller | |
5 | * | |
6 | * This software may be used and distributed according to the | |
7 | * terms of the GNU Public License, Version 2, incorporated | |
8 | * herein by reference. | |
9 | * | |
81f481ca | 10 | * Copyright 2004, 2007 Freescale Semiconductor, Inc. |
42d1f039 WD |
11 | * (C) Copyright 2003, Motorola, Inc. |
12 | * maintained by Xianghua Xiao (x.xiao@motorola.com) | |
13 | * author Andy Fleming | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __TSEC_H | |
18 | #define __TSEC_H | |
19 | ||
20 | #include <net.h> | |
f046ccd1 EL |
21 | #include <config.h> |
22 | ||
23 | #ifndef CFG_TSEC1_OFFSET | |
24 | #define CFG_TSEC1_OFFSET (0x24000) | |
25 | #endif | |
42d1f039 | 26 | |
97d80fc3 | 27 | #define TSEC_SIZE 0x01000 |
42d1f039 | 28 | |
f046ccd1 | 29 | /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ |
debb7354 | 30 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
f046ccd1 EL |
31 | #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) |
32 | #elif defined(CONFIG_MPC83XX) | |
d239d74b | 33 | #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) |
f046ccd1 EL |
34 | #endif |
35 | ||
36 | ||
42d1f039 WD |
37 | #define MAC_ADDR_LEN 6 |
38 | ||
53677ef1 | 39 | /* #define TSEC_TIMEOUT 1000000 */ |
97d80fc3 | 40 | #define TSEC_TIMEOUT 1000 |
53677ef1 | 41 | #define TOUT_LOOP 1000000 |
42d1f039 | 42 | |
5810dc3a SR |
43 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ |
44 | ||
42d1f039 WD |
45 | /* MAC register bits */ |
46 | #define MACCFG1_SOFT_RESET 0x80000000 | |
47 | #define MACCFG1_RESET_RX_MC 0x00080000 | |
48 | #define MACCFG1_RESET_TX_MC 0x00040000 | |
49 | #define MACCFG1_RESET_RX_FUN 0x00020000 | |
50 | #define MACCFG1_RESET_TX_FUN 0x00010000 | |
51 | #define MACCFG1_LOOPBACK 0x00000100 | |
52 | #define MACCFG1_RX_FLOW 0x00000020 | |
53 | #define MACCFG1_TX_FLOW 0x00000010 | |
54 | #define MACCFG1_SYNCD_RX_EN 0x00000008 | |
55 | #define MACCFG1_RX_EN 0x00000004 | |
56 | #define MACCFG1_SYNCD_TX_EN 0x00000002 | |
57 | #define MACCFG1_TX_EN 0x00000001 | |
58 | ||
59 | #define MACCFG2_INIT_SETTINGS 0x00007205 | |
60 | #define MACCFG2_FULL_DUPLEX 0x00000001 | |
53677ef1 | 61 | #define MACCFG2_IF 0x00000300 |
97d80fc3 | 62 | #define MACCFG2_GMII 0x00000200 |
53677ef1 | 63 | #define MACCFG2_MII 0x00000100 |
42d1f039 WD |
64 | |
65 | #define ECNTRL_INIT_SETTINGS 0x00001000 | |
53677ef1 | 66 | #define ECNTRL_TBI_MODE 0x00000020 |
d9b94f28 | 67 | #define ECNTRL_R100 0x00000008 |
81f481ca | 68 | #define ECNTRL_SGMII_MODE 0x00000002 |
42d1f039 | 69 | |
97d80fc3 WD |
70 | #define miim_end -2 |
71 | #define miim_read -1 | |
72 | ||
dcb84b72 JH |
73 | #ifndef CFG_TBIPA_VALUE |
74 | #define CFG_TBIPA_VALUE 0x1f | |
75 | #endif | |
42d1f039 WD |
76 | #define MIIMCFG_INIT_VALUE 0x00000003 |
77 | #define MIIMCFG_RESET 0x80000000 | |
78 | ||
53677ef1 WD |
79 | #define MIIMIND_BUSY 0x00000001 |
80 | #define MIIMIND_NOTVALID 0x00000004 | |
42d1f039 | 81 | |
53677ef1 | 82 | #define MIIM_CONTROL 0x00 |
97d80fc3 | 83 | #define MIIM_CONTROL_RESET 0x00009140 |
53677ef1 WD |
84 | #define MIIM_CONTROL_INIT 0x00001140 |
85 | #define MIIM_CONTROL_RESTART 0x00001340 | |
86 | #define MIIM_ANEN 0x00001000 | |
97d80fc3 | 87 | |
53677ef1 | 88 | #define MIIM_CR 0x00 |
97d80fc3 | 89 | #define MIIM_CR_RST 0x00008000 |
53677ef1 | 90 | #define MIIM_CR_INIT 0x00001000 |
7abf0c58 WD |
91 | |
92 | #define MIIM_STATUS 0x1 | |
53677ef1 | 93 | #define MIIM_STATUS_AN_DONE 0x00000020 |
97d80fc3 | 94 | #define MIIM_STATUS_LINK 0x0004 |
5810dc3a SR |
95 | #define PHY_BMSR_AUTN_ABLE 0x0008 |
96 | #define PHY_BMSR_AUTN_COMP 0x0020 | |
42d1f039 | 97 | |
97d80fc3 WD |
98 | #define MIIM_PHYIR1 0x2 |
99 | #define MIIM_PHYIR2 0x3 | |
42d1f039 | 100 | |
97d80fc3 WD |
101 | #define MIIM_ANAR 0x4 |
102 | #define MIIM_ANAR_INIT 0x1e1 | |
42d1f039 WD |
103 | |
104 | #define MIIM_TBI_ANLPBPA 0x5 | |
105 | #define MIIM_TBI_ANLPBPA_HALF 0x00000040 | |
106 | #define MIIM_TBI_ANLPBPA_FULL 0x00000020 | |
107 | ||
97d80fc3 WD |
108 | #define MIIM_TBI_ANEX 0x6 |
109 | #define MIIM_TBI_ANEX_NP 0x00000004 | |
110 | #define MIIM_TBI_ANEX_PRX 0x00000002 | |
111 | ||
112 | #define MIIM_GBIT_CONTROL 0x9 | |
113 | #define MIIM_GBIT_CONTROL_INIT 0xe00 | |
114 | ||
9acde129 AS |
115 | #define MIIM_EXT_PAGE_ACCESS 0x1f |
116 | ||
91e25769 PG |
117 | /* Broadcom BCM54xx -- taken from linux sungem_phy */ |
118 | #define MIIM_BCM54xx_AUXSTATUS 0x19 | |
119 | #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 | |
120 | #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 | |
121 | ||
97d80fc3 | 122 | /* Cicada Auxiliary Control/Status Register */ |
53677ef1 WD |
123 | #define MIIM_CIS8201_AUX_CONSTAT 0x1c |
124 | #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 | |
125 | #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 | |
126 | #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 | |
127 | #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 | |
128 | #define MIIM_CIS8201_AUXCONSTAT_100 0x0008 | |
42d1f039 | 129 | |
97d80fc3 | 130 | /* Cicada Extended Control Register 1 */ |
53677ef1 WD |
131 | #define MIIM_CIS8201_EXT_CON1 0x17 |
132 | #define MIIM_CIS8201_EXTCON1_INIT 0x0000 | |
42d1f039 | 133 | |
97d80fc3 WD |
134 | /* Cicada 8204 Extended PHY Control Register 1 */ |
135 | #define MIIM_CIS8204_EPHY_CON 0x17 | |
136 | #define MIIM_CIS8204_EPHYCON_INIT 0x0006 | |
03469832 | 137 | #define MIIM_CIS8204_EPHYCON_RGMII 0x1100 |
42d1f039 | 138 | |
97d80fc3 WD |
139 | /* Cicada 8204 Serial LED Control Register */ |
140 | #define MIIM_CIS8204_SLED_CON 0x1b | |
141 | #define MIIM_CIS8204_SLEDCON_INIT 0x1115 | |
42d1f039 WD |
142 | |
143 | #define MIIM_GBIT_CON 0x09 | |
7abf0c58 | 144 | #define MIIM_GBIT_CON_ADVERT 0x0e00 |
42d1f039 | 145 | |
debb7354 JL |
146 | /* Entry for Vitesse VSC8244 regs starts here */ |
147 | /* Vitesse VSC8244 Auxiliary Control/Status Register */ | |
53677ef1 WD |
148 | #define MIIM_VSC8244_AUX_CONSTAT 0x1c |
149 | #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 | |
150 | #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 | |
151 | #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 | |
152 | #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 | |
153 | #define MIIM_VSC8244_AUXCONSTAT_100 0x0008 | |
154 | #define MIIM_CONTROL_INIT_LOOPBACK 0x4000 | |
debb7354 JL |
155 | |
156 | /* Vitesse VSC8244 Extended PHY Control Register 1 */ | |
53677ef1 WD |
157 | #define MIIM_VSC8244_EPHY_CON 0x17 |
158 | #define MIIM_VSC8244_EPHYCON_INIT 0x0006 | |
debb7354 JL |
159 | |
160 | /* Vitesse VSC8244 Serial LED Control Register */ | |
53677ef1 WD |
161 | #define MIIM_VSC8244_LED_CON 0x1b |
162 | #define MIIM_VSC8244_LEDCON_INIT 0xF011 | |
debb7354 | 163 | |
2d934ea5 TK |
164 | /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ |
165 | /* Vitesse VSC8601 Extended PHY Control Register 1 */ | |
9acde129 | 166 | #define MIIM_VSC8601_EPHY_CON 0x17 |
2d934ea5 | 167 | #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 |
9acde129 | 168 | #define MIIM_VSC8601_SKEW_CTRL 0x1c |
2d934ea5 | 169 | |
97d80fc3 | 170 | /* 88E1011 PHY Status Register */ |
53677ef1 WD |
171 | #define MIIM_88E1011_PHY_STATUS 0x11 |
172 | #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 | |
173 | #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 | |
174 | #define MIIM_88E1011_PHYSTAT_100 0x4000 | |
175 | #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 | |
97d80fc3 WD |
176 | #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 |
177 | #define MIIM_88E1011_PHYSTAT_LINK 0x0400 | |
178 | ||
09f3e09e AF |
179 | #define MIIM_88E1011_PHY_SCR 0x10 |
180 | #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 | |
181 | ||
182 | /* 88E1111 PHY LED Control Register */ | |
9acde129 AS |
183 | #define MIIM_88E1111_PHY_LED_CONTROL 24 |
184 | #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 | |
185 | #define MIIM_88E1111_PHY_LED_COMBINE 0x411C | |
09f3e09e | 186 | |
d23dc394 SP |
187 | /* 88E1121 PHY LED Control Register */ |
188 | #define MIIM_88E1121_PHY_LED_CTRL 16 | |
189 | #define MIIM_88E1121_PHY_LED_PAGE 3 | |
190 | #define MIIM_88E1121_PHY_LED_DEF 0x0030 | |
191 | ||
192 | #define MIIM_88E1121_PHY_PAGE 22 | |
193 | ||
09f3e09e AF |
194 | /* 88E1145 Extended PHY Specific Control Register */ |
195 | #define MIIM_88E1145_PHY_EXT_CR 20 | |
196 | #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 | |
197 | #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 | |
198 | ||
53677ef1 | 199 | #define MIIM_88E1145_PHY_PAGE 29 |
09f3e09e AF |
200 | #define MIIM_88E1145_PHY_CAL_OV 30 |
201 | ||
18ee320f DL |
202 | /* RTL8211B PHY Status Register */ |
203 | #define MIIM_RTL8211B_PHY_STATUS 0x11 | |
204 | #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 | |
205 | #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 | |
206 | #define MIIM_RTL8211B_PHYSTAT_100 0x4000 | |
207 | #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 | |
208 | #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 | |
209 | #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 | |
09f3e09e | 210 | |
97d80fc3 WD |
211 | /* DM9161 Control register values */ |
212 | #define MIIM_DM9161_CR_STOP 0x0400 | |
213 | #define MIIM_DM9161_CR_RSTAN 0x1200 | |
214 | ||
215 | #define MIIM_DM9161_SCR 0x10 | |
216 | #define MIIM_DM9161_SCR_INIT 0x0610 | |
217 | ||
218 | /* DM9161 Specified Configuration and Status Register */ | |
219 | #define MIIM_DM9161_SCSR 0x11 | |
220 | #define MIIM_DM9161_SCSR_100F 0x8000 | |
221 | #define MIIM_DM9161_SCSR_100H 0x4000 | |
222 | #define MIIM_DM9161_SCSR_10F 0x2000 | |
223 | #define MIIM_DM9161_SCSR_10H 0x1000 | |
224 | ||
225 | /* DM9161 10BT Configuration/Status */ | |
226 | #define MIIM_DM9161_10BTCSR 0x12 | |
227 | #define MIIM_DM9161_10BTCSR_INIT 0x7800 | |
42d1f039 | 228 | |
3dd7f0f0 | 229 | /* LXT971 Status 2 registers */ |
53677ef1 | 230 | #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ |
d8169c9f | 231 | #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 |
53677ef1 WD |
232 | #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ |
233 | #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ | |
234 | #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ | |
235 | #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ | |
3dd7f0f0 | 236 | |
be5048f1 WD |
237 | /* DP83865 Control register values */ |
238 | #define MIIM_DP83865_CR_INIT 0x9200 | |
239 | ||
240 | /* DP83865 Link and Auto-Neg Status Register */ | |
241 | #define MIIM_DP83865_LANR 0x11 | |
242 | #define MIIM_DP83865_SPD_MASK 0x0018 | |
243 | #define MIIM_DP83865_SPD_1000 0x0010 | |
244 | #define MIIM_DP83865_SPD_100 0x0008 | |
245 | #define MIIM_DP83865_DPX_FULL 0x0002 | |
246 | ||
53677ef1 | 247 | #define MIIM_READ_COMMAND 0x00000001 |
42d1f039 WD |
248 | |
249 | #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN | |
250 | ||
251 | #define MINFLR_INIT_SETTINGS 0x00000040 | |
252 | ||
53677ef1 WD |
253 | #define DMACTRL_INIT_SETTINGS 0x000000c3 |
254 | #define DMACTRL_GRS 0x00000010 | |
255 | #define DMACTRL_GTS 0x00000008 | |
42d1f039 | 256 | |
53677ef1 WD |
257 | #define TSTAT_CLEAR_THALT 0x80000000 |
258 | #define RSTAT_CLEAR_RHALT 0x00800000 | |
42d1f039 | 259 | |
7abf0c58 | 260 | |
42d1f039 WD |
261 | #define IEVENT_INIT_CLEAR 0xffffffff |
262 | #define IEVENT_BABR 0x80000000 | |
263 | #define IEVENT_RXC 0x40000000 | |
264 | #define IEVENT_BSY 0x20000000 | |
265 | #define IEVENT_EBERR 0x10000000 | |
266 | #define IEVENT_MSRO 0x04000000 | |
267 | #define IEVENT_GTSC 0x02000000 | |
268 | #define IEVENT_BABT 0x01000000 | |
269 | #define IEVENT_TXC 0x00800000 | |
270 | #define IEVENT_TXE 0x00400000 | |
271 | #define IEVENT_TXB 0x00200000 | |
272 | #define IEVENT_TXF 0x00100000 | |
273 | #define IEVENT_IE 0x00080000 | |
274 | #define IEVENT_LC 0x00040000 | |
275 | #define IEVENT_CRL 0x00020000 | |
276 | #define IEVENT_XFUN 0x00010000 | |
277 | #define IEVENT_RXB0 0x00008000 | |
278 | #define IEVENT_GRSC 0x00000100 | |
279 | #define IEVENT_RXF0 0x00000080 | |
280 | ||
281 | #define IMASK_INIT_CLEAR 0x00000000 | |
282 | #define IMASK_TXEEN 0x00400000 | |
283 | #define IMASK_TXBEN 0x00200000 | |
53677ef1 | 284 | #define IMASK_TXFEN 0x00100000 |
42d1f039 WD |
285 | #define IMASK_RXFEN0 0x00000080 |
286 | ||
287 | ||
288 | /* Default Attribute fields */ | |
289 | #define ATTR_INIT_SETTINGS 0x000000c0 | |
290 | #define ATTRELI_INIT_SETTINGS 0x00000000 | |
291 | ||
292 | ||
293 | /* TxBD status field bits */ | |
294 | #define TXBD_READY 0x8000 | |
295 | #define TXBD_PADCRC 0x4000 | |
296 | #define TXBD_WRAP 0x2000 | |
297 | #define TXBD_INTERRUPT 0x1000 | |
298 | #define TXBD_LAST 0x0800 | |
299 | #define TXBD_CRC 0x0400 | |
300 | #define TXBD_DEF 0x0200 | |
301 | #define TXBD_HUGEFRAME 0x0080 | |
302 | #define TXBD_LATECOLLISION 0x0080 | |
303 | #define TXBD_RETRYLIMIT 0x0040 | |
304 | #define TXBD_RETRYCOUNTMASK 0x003c | |
305 | #define TXBD_UNDERRUN 0x0002 | |
53677ef1 | 306 | #define TXBD_STATS 0x03ff |
42d1f039 WD |
307 | |
308 | /* RxBD status field bits */ | |
309 | #define RXBD_EMPTY 0x8000 | |
310 | #define RXBD_RO1 0x4000 | |
311 | #define RXBD_WRAP 0x2000 | |
312 | #define RXBD_INTERRUPT 0x1000 | |
313 | #define RXBD_LAST 0x0800 | |
314 | #define RXBD_FIRST 0x0400 | |
315 | #define RXBD_MISS 0x0100 | |
316 | #define RXBD_BROADCAST 0x0080 | |
317 | #define RXBD_MULTICAST 0x0040 | |
318 | #define RXBD_LARGE 0x0020 | |
319 | #define RXBD_NONOCTET 0x0010 | |
320 | #define RXBD_SHORT 0x0008 | |
321 | #define RXBD_CRCERR 0x0004 | |
322 | #define RXBD_OVERRUN 0x0002 | |
323 | #define RXBD_TRUNCATED 0x0001 | |
324 | #define RXBD_STATS 0x003f | |
325 | ||
326 | typedef struct txbd8 | |
327 | { | |
53677ef1 WD |
328 | ushort status; /* Status Fields */ |
329 | ushort length; /* Buffer length */ | |
330 | uint bufPtr; /* Buffer Pointer */ | |
42d1f039 WD |
331 | } txbd8_t; |
332 | ||
333 | typedef struct rxbd8 | |
334 | { | |
53677ef1 WD |
335 | ushort status; /* Status Fields */ |
336 | ushort length; /* Buffer Length */ | |
337 | uint bufPtr; /* Buffer Pointer */ | |
42d1f039 WD |
338 | } rxbd8_t; |
339 | ||
340 | typedef struct rmon_mib | |
341 | { | |
342 | /* Transmit and Receive Counters */ | |
343 | uint tr64; /* Transmit and Receive 64-byte Frame Counter */ | |
344 | uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ | |
345 | uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ | |
346 | uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ | |
347 | uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ | |
348 | uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ | |
349 | uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ | |
350 | /* Receive Counters */ | |
351 | uint rbyt; /* Receive Byte Counter */ | |
352 | uint rpkt; /* Receive Packet Counter */ | |
353 | uint rfcs; /* Receive FCS Error Counter */ | |
354 | uint rmca; /* Receive Multicast Packet (Counter) */ | |
355 | uint rbca; /* Receive Broadcast Packet */ | |
356 | uint rxcf; /* Receive Control Frame Packet */ | |
357 | uint rxpf; /* Receive Pause Frame Packet */ | |
358 | uint rxuo; /* Receive Unknown OP Code */ | |
359 | uint raln; /* Receive Alignment Error */ | |
360 | uint rflr; /* Receive Frame Length Error */ | |
361 | uint rcde; /* Receive Code Error */ | |
362 | uint rcse; /* Receive Carrier Sense Error */ | |
363 | uint rund; /* Receive Undersize Packet */ | |
364 | uint rovr; /* Receive Oversize Packet */ | |
365 | uint rfrg; /* Receive Fragments */ | |
366 | uint rjbr; /* Receive Jabber */ | |
367 | uint rdrp; /* Receive Drop */ | |
368 | /* Transmit Counters */ | |
369 | uint tbyt; /* Transmit Byte Counter */ | |
370 | uint tpkt; /* Transmit Packet */ | |
371 | uint tmca; /* Transmit Multicast Packet */ | |
372 | uint tbca; /* Transmit Broadcast Packet */ | |
373 | uint txpf; /* Transmit Pause Control Frame */ | |
374 | uint tdfr; /* Transmit Deferral Packet */ | |
375 | uint tedf; /* Transmit Excessive Deferral Packet */ | |
376 | uint tscl; /* Transmit Single Collision Packet */ | |
377 | /* (0x2_n700) */ | |
378 | uint tmcl; /* Transmit Multiple Collision Packet */ | |
379 | uint tlcl; /* Transmit Late Collision Packet */ | |
380 | uint txcl; /* Transmit Excessive Collision Packet */ | |
381 | uint tncl; /* Transmit Total Collision */ | |
382 | ||
383 | uint res2; | |
384 | ||
385 | uint tdrp; /* Transmit Drop Frame */ | |
386 | uint tjbr; /* Transmit Jabber Frame */ | |
387 | uint tfcs; /* Transmit FCS Error */ | |
388 | uint txcf; /* Transmit Control Frame */ | |
389 | uint tovr; /* Transmit Oversize Frame */ | |
390 | uint tund; /* Transmit Undersize Frame */ | |
391 | uint tfrg; /* Transmit Fragments Frame */ | |
392 | /* General Registers */ | |
393 | uint car1; /* Carry Register One */ | |
394 | uint car2; /* Carry Register Two */ | |
395 | uint cam1; /* Carry Register One Mask */ | |
396 | uint cam2; /* Carry Register Two Mask */ | |
397 | } rmon_mib_t; | |
398 | ||
399 | typedef struct tsec_hash_regs | |
400 | { | |
401 | uint iaddr0; /* Individual Address Register 0 */ | |
402 | uint iaddr1; /* Individual Address Register 1 */ | |
403 | uint iaddr2; /* Individual Address Register 2 */ | |
404 | uint iaddr3; /* Individual Address Register 3 */ | |
405 | uint iaddr4; /* Individual Address Register 4 */ | |
406 | uint iaddr5; /* Individual Address Register 5 */ | |
407 | uint iaddr6; /* Individual Address Register 6 */ | |
408 | uint iaddr7; /* Individual Address Register 7 */ | |
409 | uint res1[24]; | |
410 | uint gaddr0; /* Group Address Register 0 */ | |
411 | uint gaddr1; /* Group Address Register 1 */ | |
412 | uint gaddr2; /* Group Address Register 2 */ | |
413 | uint gaddr3; /* Group Address Register 3 */ | |
414 | uint gaddr4; /* Group Address Register 4 */ | |
415 | uint gaddr5; /* Group Address Register 5 */ | |
416 | uint gaddr6; /* Group Address Register 6 */ | |
417 | uint gaddr7; /* Group Address Register 7 */ | |
418 | uint res2[24]; | |
419 | } tsec_hash_t; | |
420 | ||
421 | typedef struct tsec | |
422 | { | |
423 | /* General Control and Status Registers (0x2_n000) */ | |
424 | uint res000[4]; | |
425 | ||
426 | uint ievent; /* Interrupt Event */ | |
427 | uint imask; /* Interrupt Mask */ | |
428 | uint edis; /* Error Disabled */ | |
429 | uint res01c; | |
430 | uint ecntrl; /* Ethernet Control */ | |
431 | uint minflr; /* Minimum Frame Length */ | |
432 | uint ptv; /* Pause Time Value */ | |
433 | uint dmactrl; /* DMA Control */ | |
434 | uint tbipa; /* TBI PHY Address */ | |
435 | ||
436 | uint res034[3]; | |
437 | uint res040[48]; | |
438 | ||
439 | /* Transmit Control and Status Registers (0x2_n100) */ | |
440 | uint tctrl; /* Transmit Control */ | |
53677ef1 | 441 | uint tstat; /* Transmit Status */ |
42d1f039 WD |
442 | uint res108; |
443 | uint tbdlen; /* Tx BD Data Length */ | |
444 | uint res110[5]; | |
53677ef1 | 445 | uint ctbptr; /* Current TxBD Pointer */ |
42d1f039 WD |
446 | uint res128[23]; |
447 | uint tbptr; /* TxBD Pointer */ | |
448 | uint res188[30]; | |
449 | /* (0x2_n200) */ | |
53677ef1 | 450 | uint res200; |
42d1f039 WD |
451 | uint tbase; /* TxBD Base Address */ |
452 | uint res208[42]; | |
453 | uint ostbd; /* Out of Sequence TxBD */ | |
454 | uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ | |
53677ef1 | 455 | uint res2b8[18]; |
42d1f039 WD |
456 | |
457 | /* Receive Control and Status Registers (0x2_n300) */ | |
458 | uint rctrl; /* Receive Control */ | |
459 | uint rstat; /* Receive Status */ | |
460 | uint res308; | |
461 | uint rbdlen; /* RxBD Data Length */ | |
462 | uint res310[4]; | |
53677ef1 WD |
463 | uint res320; |
464 | uint crbptr; /* Current Receive Buffer Pointer */ | |
42d1f039 | 465 | uint res328[6]; |
53677ef1 | 466 | uint mrblr; /* Maximum Receive Buffer Length */ |
42d1f039 | 467 | uint res344[16]; |
53677ef1 WD |
468 | uint rbptr; /* RxBD Pointer */ |
469 | uint res388[30]; | |
42d1f039 | 470 | /* (0x2_n400) */ |
53677ef1 WD |
471 | uint res400; |
472 | uint rbase; /* RxBD Base Address */ | |
473 | uint res408[62]; | |
42d1f039 WD |
474 | |
475 | /* MAC Registers (0x2_n500) */ | |
476 | uint maccfg1; /* MAC Configuration #1 */ | |
477 | uint maccfg2; /* MAC Configuration #2 */ | |
478 | uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ | |
479 | uint hafdup; /* Half-duplex */ | |
480 | uint maxfrm; /* Maximum Frame */ | |
481 | uint res514; | |
482 | uint res518; | |
483 | ||
484 | uint res51c; | |
485 | ||
486 | uint miimcfg; /* MII Management: Configuration */ | |
487 | uint miimcom; /* MII Management: Command */ | |
488 | uint miimadd; /* MII Management: Address */ | |
489 | uint miimcon; /* MII Management: Control */ | |
490 | uint miimstat; /* MII Management: Status */ | |
491 | uint miimind; /* MII Management: Indicators */ | |
492 | ||
493 | uint res538; | |
494 | ||
495 | uint ifstat; /* Interface Status */ | |
496 | uint macstnaddr1; /* Station Address, part 1 */ | |
497 | uint macstnaddr2; /* Station Address, part 2 */ | |
498 | uint res548[46]; | |
499 | ||
500 | /* (0x2_n600) */ | |
501 | uint res600[32]; | |
502 | ||
503 | /* RMON MIB Registers (0x2_n680-0x2_n73c) */ | |
504 | rmon_mib_t rmon; | |
505 | uint res740[48]; | |
506 | ||
507 | /* Hash Function Registers (0x2_n800) */ | |
508 | tsec_hash_t hash; | |
509 | ||
53677ef1 | 510 | uint res900[128]; |
42d1f039 WD |
511 | |
512 | /* Pattern Registers (0x2_nb00) */ | |
53677ef1 WD |
513 | uint resb00[62]; |
514 | uint attr; /* Default Attribute Register */ | |
515 | uint attreli; /* Default Attribute Extract Length and Index */ | |
42d1f039 WD |
516 | |
517 | /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ | |
518 | uint resc00[256]; | |
519 | } tsec_t; | |
520 | ||
d9b94f28 JL |
521 | #define TSEC_GIGABIT (1) |
522 | ||
523 | /* This flag currently only has | |
524 | * meaning if we're using the eTSEC */ | |
525 | #define TSEC_REDUCED (1 << 1) | |
526 | ||
97d80fc3 WD |
527 | struct tsec_private { |
528 | volatile tsec_t *regs; | |
529 | volatile tsec_t *phyregs; | |
530 | struct phy_info *phyinfo; | |
531 | uint phyaddr; | |
d9b94f28 | 532 | u32 flags; |
97d80fc3 WD |
533 | uint link; |
534 | uint duplexity; | |
535 | uint speed; | |
536 | }; | |
537 | ||
538 | ||
539 | /* | |
540 | * struct phy_cmd: A command for reading or writing a PHY register | |
541 | * | |
542 | * mii_reg: The register to read or write | |
543 | * | |
544 | * mii_data: For writes, the value to put in the register. | |
53677ef1 | 545 | * A value of -1 indicates this is a read. |
97d80fc3 WD |
546 | * |
547 | * funct: A function pointer which is invoked for each command. | |
53677ef1 | 548 | * For reads, this function will be passed the value read |
97d80fc3 WD |
549 | * from the PHY, and process it. |
550 | * For writes, the result of this function will be written | |
551 | * to the PHY register | |
552 | */ | |
553 | struct phy_cmd { | |
53677ef1 WD |
554 | uint mii_reg; |
555 | uint mii_data; | |
556 | uint (*funct) (uint mii_reg, struct tsec_private * priv); | |
97d80fc3 WD |
557 | }; |
558 | ||
559 | /* struct phy_info: a structure which defines attributes for a PHY | |
560 | * | |
561 | * id will contain a number which represents the PHY. During | |
562 | * startup, the driver will poll the PHY to find out what its | |
563 | * UID--as defined by registers 2 and 3--is. The 32-bit result | |
564 | * gotten from the PHY will be shifted right by "shift" bits to | |
565 | * discard any bits which may change based on revision numbers | |
566 | * unimportant to functionality | |
567 | * | |
568 | * The struct phy_cmd entries represent pointers to an arrays of | |
569 | * commands which tell the driver what to do to the PHY. | |
570 | */ | |
571 | struct phy_info { | |
53677ef1 WD |
572 | uint id; |
573 | char *name; | |
574 | uint shift; | |
575 | /* Called to configure the PHY, and modify the controller | |
576 | * based on the results */ | |
577 | struct phy_cmd *config; | |
578 | ||
579 | /* Called when starting up the controller */ | |
580 | struct phy_cmd *startup; | |
581 | ||
582 | /* Called when bringing down the controller */ | |
583 | struct phy_cmd *shutdown; | |
97d80fc3 WD |
584 | }; |
585 | ||
dd3d1f56 AF |
586 | struct tsec_info_struct { |
587 | unsigned int phyaddr; | |
588 | u32 flags; | |
589 | unsigned int phyregidx; | |
590 | }; | |
591 | ||
42d1f039 | 592 | #endif /* __TSEC_H */ |