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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
cfbcacf4 | 54 | #define DRM_AMDGPU_VM 0x13 |
7ca24cf2 | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
52c6a62c | 56 | #define DRM_AMDGPU_SCHED 0x15 |
81629cba AD |
57 | |
58 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
59 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
60 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
61 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
62 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
63 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
64 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
65 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 66 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
67 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
68 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
69 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 70 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
cfbcacf4 | 71 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
7ca24cf2 | 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
52c6a62c | 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
81629cba | 74 | |
b646c1dc SL |
75 | /** |
76 | * DOC: memory domains | |
77 | * | |
78 | * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. | |
79 | * Memory in this pool could be swapped out to disk if there is pressure. | |
80 | * | |
81 | * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the | |
82 | * GPU's virtual address space via gart. Gart memory linearizes non-contiguous | |
83 | * pages of system memory, allows GPU access system memory in a linezrized | |
84 | * fashion. | |
85 | * | |
86 | * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory | |
87 | * carved out by the BIOS. | |
88 | * | |
89 | * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data | |
90 | * across shader threads. | |
91 | * | |
92 | * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the | |
93 | * execution of all the waves on a device. | |
94 | * | |
95 | * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines | |
96 | * for appending data. | |
97 | */ | |
81629cba AD |
98 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
99 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
100 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
101 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
102 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
103 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
3f188453 CZ |
104 | #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ |
105 | AMDGPU_GEM_DOMAIN_GTT | \ | |
106 | AMDGPU_GEM_DOMAIN_VRAM | \ | |
107 | AMDGPU_GEM_DOMAIN_GDS | \ | |
108 | AMDGPU_GEM_DOMAIN_GWS | \ | |
109 | AMDGPU_GEM_DOMAIN_OA) | |
81629cba | 110 | |
81629cba AD |
111 | /* Flag that CPU access will be required for the case of VRAM domain */ |
112 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
113 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
114 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 115 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 116 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
117 | /* Flag that the memory should be in VRAM and cleared */ |
118 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
119 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
120 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
121 | /* Flag that allocating the BO should use linear VRAM */ |
122 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
e1eb899b CK |
123 | /* Flag that BO is always valid in this VM */ |
124 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) | |
177ae09b AR |
125 | /* Flag that BO sharing will be explicitly synchronized */ |
126 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) | |
959a2091 YZ |
127 | /* Flag that indicates allocating MQD gart on GFX9, where the mtype |
128 | * for the second page onward should be set to NC. | |
129 | */ | |
130 | #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) | |
81629cba | 131 | |
81629cba AD |
132 | struct drm_amdgpu_gem_create_in { |
133 | /** the requested memory size */ | |
2ce9dde0 | 134 | __u64 bo_size; |
81629cba | 135 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 136 | __u64 alignment; |
81629cba | 137 | /** the requested memory domains */ |
2ce9dde0 | 138 | __u64 domains; |
81629cba | 139 | /** allocation flags */ |
2ce9dde0 | 140 | __u64 domain_flags; |
81629cba AD |
141 | }; |
142 | ||
143 | struct drm_amdgpu_gem_create_out { | |
144 | /** returned GEM object handle */ | |
2ce9dde0 MR |
145 | __u32 handle; |
146 | __u32 _pad; | |
81629cba AD |
147 | }; |
148 | ||
149 | union drm_amdgpu_gem_create { | |
150 | struct drm_amdgpu_gem_create_in in; | |
151 | struct drm_amdgpu_gem_create_out out; | |
152 | }; | |
153 | ||
154 | /** Opcode to create new residency list. */ | |
155 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
156 | /** Opcode to destroy previously created residency list */ | |
157 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
158 | /** Opcode to update resource information in the list */ | |
159 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
160 | ||
161 | struct drm_amdgpu_bo_list_in { | |
162 | /** Type of operation */ | |
2ce9dde0 | 163 | __u32 operation; |
81629cba | 164 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 165 | __u32 list_handle; |
81629cba | 166 | /** Number of BOs in list */ |
2ce9dde0 | 167 | __u32 bo_number; |
81629cba | 168 | /** Size of each element describing BO */ |
2ce9dde0 | 169 | __u32 bo_info_size; |
81629cba | 170 | /** Pointer to array describing BOs */ |
2ce9dde0 | 171 | __u64 bo_info_ptr; |
81629cba AD |
172 | }; |
173 | ||
174 | struct drm_amdgpu_bo_list_entry { | |
175 | /** Handle of BO */ | |
2ce9dde0 | 176 | __u32 bo_handle; |
81629cba | 177 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 178 | __u32 bo_priority; |
81629cba AD |
179 | }; |
180 | ||
181 | struct drm_amdgpu_bo_list_out { | |
182 | /** Handle of resource list */ | |
2ce9dde0 MR |
183 | __u32 list_handle; |
184 | __u32 _pad; | |
81629cba AD |
185 | }; |
186 | ||
187 | union drm_amdgpu_bo_list { | |
188 | struct drm_amdgpu_bo_list_in in; | |
189 | struct drm_amdgpu_bo_list_out out; | |
190 | }; | |
191 | ||
192 | /* context related */ | |
193 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
194 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
195 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
bc1b1bf6 | 196 | #define AMDGPU_CTX_OP_QUERY_STATE2 4 |
81629cba | 197 | |
d94aed5a MO |
198 | /* GPU reset status */ |
199 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
200 | /* this the context caused it */ |
201 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
202 | /* some other context caused it */ | |
203 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
204 | /* unknown cause */ | |
205 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 206 | |
bc1b1bf6 ML |
207 | /* indicate gpu reset occured after ctx created */ |
208 | #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) | |
209 | /* indicate vram lost occured after ctx created */ | |
210 | #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) | |
211 | /* indicate some job from this context once cause gpu hang */ | |
212 | #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) | |
213 | ||
c2636dc5 | 214 | /* Context priority level */ |
f3d19bf8 | 215 | #define AMDGPU_CTX_PRIORITY_UNSET -2048 |
8bc4c256 AR |
216 | #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 |
217 | #define AMDGPU_CTX_PRIORITY_LOW -512 | |
c2636dc5 AR |
218 | #define AMDGPU_CTX_PRIORITY_NORMAL 0 |
219 | /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ | |
8bc4c256 AR |
220 | #define AMDGPU_CTX_PRIORITY_HIGH 512 |
221 | #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 | |
c2636dc5 | 222 | |
81629cba | 223 | struct drm_amdgpu_ctx_in { |
675da0dd | 224 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 225 | __u32 op; |
675da0dd | 226 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
227 | __u32 flags; |
228 | __u32 ctx_id; | |
c2636dc5 | 229 | __s32 priority; |
81629cba AD |
230 | }; |
231 | ||
232 | union drm_amdgpu_ctx_out { | |
233 | struct { | |
2ce9dde0 MR |
234 | __u32 ctx_id; |
235 | __u32 _pad; | |
81629cba AD |
236 | } alloc; |
237 | ||
238 | struct { | |
675da0dd | 239 | /** For future use, no flags defined so far */ |
2ce9dde0 | 240 | __u64 flags; |
d94aed5a | 241 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 242 | __u32 hangs; |
d94aed5a | 243 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 244 | __u32 reset_status; |
81629cba AD |
245 | } state; |
246 | }; | |
247 | ||
248 | union drm_amdgpu_ctx { | |
249 | struct drm_amdgpu_ctx_in in; | |
250 | union drm_amdgpu_ctx_out out; | |
251 | }; | |
252 | ||
cfbcacf4 CZ |
253 | /* vm ioctl */ |
254 | #define AMDGPU_VM_OP_RESERVE_VMID 1 | |
255 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 | |
256 | ||
257 | struct drm_amdgpu_vm_in { | |
258 | /** AMDGPU_VM_OP_* */ | |
259 | __u32 op; | |
260 | __u32 flags; | |
261 | }; | |
262 | ||
263 | struct drm_amdgpu_vm_out { | |
264 | /** For future use, no flags defined so far */ | |
265 | __u64 flags; | |
266 | }; | |
267 | ||
268 | union drm_amdgpu_vm { | |
269 | struct drm_amdgpu_vm_in in; | |
270 | struct drm_amdgpu_vm_out out; | |
271 | }; | |
272 | ||
52c6a62c AR |
273 | /* sched ioctl */ |
274 | #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 | |
275 | ||
276 | struct drm_amdgpu_sched_in { | |
277 | /* AMDGPU_SCHED_OP_* */ | |
278 | __u32 op; | |
279 | __u32 fd; | |
280 | __s32 priority; | |
281 | __u32 flags; | |
282 | }; | |
283 | ||
284 | union drm_amdgpu_sched { | |
285 | struct drm_amdgpu_sched_in in; | |
286 | }; | |
287 | ||
81629cba AD |
288 | /* |
289 | * This is not a reliable API and you should expect it to fail for any | |
290 | * number of reasons and have fallback path that do not use userptr to | |
291 | * perform any operation. | |
292 | */ | |
293 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
294 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
295 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
296 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
297 | ||
298 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
299 | __u64 addr; |
300 | __u64 size; | |
675da0dd | 301 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 302 | __u32 flags; |
675da0dd | 303 | /* Resulting GEM handle */ |
2ce9dde0 | 304 | __u32 handle; |
81629cba AD |
305 | }; |
306 | ||
00ac6f6b | 307 | /* SI-CI-VI: */ |
fbd76d59 MO |
308 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
309 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
310 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
311 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
312 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
313 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
314 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
315 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
316 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
317 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
318 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
319 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
320 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
321 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
322 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
323 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
324 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
325 | ||
00ac6f6b AD |
326 | /* GFX9 and later: */ |
327 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
328 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
ce331f8f NK |
329 | #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 |
330 | #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF | |
331 | #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 | |
332 | #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF | |
333 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 | |
334 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 | |
00ac6f6b AD |
335 | |
336 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 337 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 338 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 339 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 340 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
341 | |
342 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
343 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
344 | ||
345 | /** The same structure is shared for input/output */ | |
346 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 347 | /** GEM Object handle */ |
2ce9dde0 | 348 | __u32 handle; |
675da0dd | 349 | /** Do we want get or set metadata */ |
2ce9dde0 | 350 | __u32 op; |
81629cba | 351 | struct { |
675da0dd | 352 | /** For future use, no flags defined so far */ |
2ce9dde0 | 353 | __u64 flags; |
675da0dd | 354 | /** family specific tiling info */ |
2ce9dde0 MR |
355 | __u64 tiling_info; |
356 | __u32 data_size_bytes; | |
357 | __u32 data[64]; | |
81629cba AD |
358 | } data; |
359 | }; | |
360 | ||
361 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 362 | /** the GEM object handle */ |
2ce9dde0 MR |
363 | __u32 handle; |
364 | __u32 _pad; | |
81629cba AD |
365 | }; |
366 | ||
367 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 368 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 369 | __u64 addr_ptr; |
81629cba AD |
370 | }; |
371 | ||
372 | union drm_amdgpu_gem_mmap { | |
373 | struct drm_amdgpu_gem_mmap_in in; | |
374 | struct drm_amdgpu_gem_mmap_out out; | |
375 | }; | |
376 | ||
377 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 378 | /** GEM object handle */ |
2ce9dde0 | 379 | __u32 handle; |
675da0dd | 380 | /** For future use, no flags defined so far */ |
2ce9dde0 | 381 | __u32 flags; |
675da0dd | 382 | /** Absolute timeout to wait */ |
2ce9dde0 | 383 | __u64 timeout; |
81629cba AD |
384 | }; |
385 | ||
386 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 387 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 388 | __u32 status; |
675da0dd | 389 | /** Returned current memory domain */ |
2ce9dde0 | 390 | __u32 domain; |
81629cba AD |
391 | }; |
392 | ||
393 | union drm_amdgpu_gem_wait_idle { | |
394 | struct drm_amdgpu_gem_wait_idle_in in; | |
395 | struct drm_amdgpu_gem_wait_idle_out out; | |
396 | }; | |
397 | ||
398 | struct drm_amdgpu_wait_cs_in { | |
d7b1eeb2 ML |
399 | /* Command submission handle |
400 | * handle equals 0 means none to wait for | |
080b24eb | 401 | * handle equals ~0ull means wait for the latest sequence number |
d7b1eeb2 | 402 | */ |
2ce9dde0 | 403 | __u64 handle; |
675da0dd | 404 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
405 | __u64 timeout; |
406 | __u32 ip_type; | |
407 | __u32 ip_instance; | |
408 | __u32 ring; | |
409 | __u32 ctx_id; | |
81629cba AD |
410 | }; |
411 | ||
412 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 413 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 414 | __u64 status; |
81629cba AD |
415 | }; |
416 | ||
417 | union drm_amdgpu_wait_cs { | |
418 | struct drm_amdgpu_wait_cs_in in; | |
419 | struct drm_amdgpu_wait_cs_out out; | |
420 | }; | |
421 | ||
eef18a82 JZ |
422 | struct drm_amdgpu_fence { |
423 | __u32 ctx_id; | |
424 | __u32 ip_type; | |
425 | __u32 ip_instance; | |
426 | __u32 ring; | |
427 | __u64 seq_no; | |
428 | }; | |
429 | ||
430 | struct drm_amdgpu_wait_fences_in { | |
431 | /** This points to uint64_t * which points to fences */ | |
432 | __u64 fences; | |
433 | __u32 fence_count; | |
434 | __u32 wait_all; | |
435 | __u64 timeout_ns; | |
436 | }; | |
437 | ||
438 | struct drm_amdgpu_wait_fences_out { | |
439 | __u32 status; | |
440 | __u32 first_signaled; | |
441 | }; | |
442 | ||
443 | union drm_amdgpu_wait_fences { | |
444 | struct drm_amdgpu_wait_fences_in in; | |
445 | struct drm_amdgpu_wait_fences_out out; | |
446 | }; | |
447 | ||
675da0dd CK |
448 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
449 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
450 | ||
81629cba AD |
451 | /* Sets or returns a value associated with a buffer. */ |
452 | struct drm_amdgpu_gem_op { | |
675da0dd | 453 | /** GEM object handle */ |
2ce9dde0 | 454 | __u32 handle; |
675da0dd | 455 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 456 | __u32 op; |
675da0dd | 457 | /** Input or return value */ |
2ce9dde0 | 458 | __u64 value; |
81629cba AD |
459 | }; |
460 | ||
81629cba AD |
461 | #define AMDGPU_VA_OP_MAP 1 |
462 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 463 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 464 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 465 | |
fc220f65 CK |
466 | /* Delay the page table update till the next CS */ |
467 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
468 | ||
81629cba AD |
469 | /* Mapping flags */ |
470 | /* readable mapping */ | |
471 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
472 | /* writable mapping */ | |
473 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
474 | /* executable mapping, new for VI */ | |
475 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
476 | /* partially resident texture */ |
477 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
478 | /* MTYPE flags use bit 5 to 8 */ |
479 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
480 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
481 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
482 | /* Use NC MTYPE instead of default MTYPE */ | |
483 | #define AMDGPU_VM_MTYPE_NC (1 << 5) | |
484 | /* Use WC MTYPE instead of default MTYPE */ | |
485 | #define AMDGPU_VM_MTYPE_WC (2 << 5) | |
486 | /* Use CC MTYPE instead of default MTYPE */ | |
487 | #define AMDGPU_VM_MTYPE_CC (3 << 5) | |
488 | /* Use UC MTYPE instead of default MTYPE */ | |
489 | #define AMDGPU_VM_MTYPE_UC (4 << 5) | |
81629cba | 490 | |
34b5f6a6 | 491 | struct drm_amdgpu_gem_va { |
675da0dd | 492 | /** GEM object handle */ |
2ce9dde0 MR |
493 | __u32 handle; |
494 | __u32 _pad; | |
675da0dd | 495 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 496 | __u32 operation; |
675da0dd | 497 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 498 | __u32 flags; |
675da0dd | 499 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 500 | __u64 va_address; |
675da0dd | 501 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 502 | __u64 offset_in_bo; |
675da0dd | 503 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 504 | __u64 map_size; |
81629cba AD |
505 | }; |
506 | ||
81629cba AD |
507 | #define AMDGPU_HW_IP_GFX 0 |
508 | #define AMDGPU_HW_IP_COMPUTE 1 | |
509 | #define AMDGPU_HW_IP_DMA 2 | |
510 | #define AMDGPU_HW_IP_UVD 3 | |
511 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 | 512 | #define AMDGPU_HW_IP_UVD_ENC 5 |
66e236f1 | 513 | #define AMDGPU_HW_IP_VCN_DEC 6 |
fcfc5a90 | 514 | #define AMDGPU_HW_IP_VCN_ENC 7 |
81d35014 BZ |
515 | #define AMDGPU_HW_IP_VCN_JPEG 8 |
516 | #define AMDGPU_HW_IP_NUM 9 | |
81629cba AD |
517 | |
518 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
519 | ||
520 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
521 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 522 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
660e8558 DA |
523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | |
964d0fbf | 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
67dd1a36 | 526 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 |
675da0dd | 527 | |
81629cba | 528 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
529 | __u32 chunk_id; |
530 | __u32 length_dw; | |
531 | __u64 chunk_data; | |
81629cba AD |
532 | }; |
533 | ||
534 | struct drm_amdgpu_cs_in { | |
535 | /** Rendering context id */ | |
2ce9dde0 | 536 | __u32 ctx_id; |
81629cba | 537 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
538 | __u32 bo_list_handle; |
539 | __u32 num_chunks; | |
540 | __u32 _pad; | |
541 | /** this points to __u64 * which point to cs chunks */ | |
542 | __u64 chunks; | |
81629cba AD |
543 | }; |
544 | ||
545 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 546 | __u64 handle; |
81629cba AD |
547 | }; |
548 | ||
549 | union drm_amdgpu_cs { | |
675da0dd CK |
550 | struct drm_amdgpu_cs_in in; |
551 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
552 | }; |
553 | ||
554 | /* Specify flags to be used for IB */ | |
555 | ||
556 | /* This IB should be submitted to CE */ | |
557 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
558 | ||
ed834af2 | 559 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 560 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 561 | |
71aec257 ML |
562 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
563 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) | |
564 | ||
d240cd9e MO |
565 | /* The IB fence should do the L2 writeback but not invalidate any shader |
566 | * caches (L2/vL1/sL1/I$). */ | |
567 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) | |
568 | ||
41cca166 MO |
569 | /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. |
570 | * This will reset wave ID counters for the IB. | |
571 | */ | |
572 | #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) | |
573 | ||
81629cba | 574 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 575 | __u32 _pad; |
675da0dd | 576 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 577 | __u32 flags; |
675da0dd | 578 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 579 | __u64 va_start; |
675da0dd | 580 | /** Size of submission */ |
2ce9dde0 | 581 | __u32 ib_bytes; |
675da0dd | 582 | /** HW IP to submit to */ |
2ce9dde0 | 583 | __u32 ip_type; |
675da0dd | 584 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 585 | __u32 ip_instance; |
675da0dd | 586 | /** Ring index to submit to */ |
2ce9dde0 | 587 | __u32 ring; |
81629cba AD |
588 | }; |
589 | ||
2b48d323 | 590 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
591 | __u32 ip_type; |
592 | __u32 ip_instance; | |
593 | __u32 ring; | |
594 | __u32 ctx_id; | |
595 | __u64 handle; | |
2b48d323 CK |
596 | }; |
597 | ||
81629cba | 598 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
599 | __u32 handle; |
600 | __u32 offset; | |
81629cba AD |
601 | }; |
602 | ||
660e8558 DA |
603 | struct drm_amdgpu_cs_chunk_sem { |
604 | __u32 handle; | |
605 | }; | |
606 | ||
7ca24cf2 MO |
607 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 |
608 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 | |
609 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 | |
610 | ||
611 | union drm_amdgpu_fence_to_handle { | |
612 | struct { | |
613 | struct drm_amdgpu_fence fence; | |
614 | __u32 what; | |
56e0349f | 615 | __u32 pad; |
7ca24cf2 MO |
616 | } in; |
617 | struct { | |
618 | __u32 handle; | |
619 | } out; | |
620 | }; | |
621 | ||
81629cba AD |
622 | struct drm_amdgpu_cs_chunk_data { |
623 | union { | |
624 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
625 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
626 | }; | |
627 | }; | |
628 | ||
629 | /** | |
630 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
631 | * | |
632 | */ | |
633 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 634 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
81629cba AD |
635 | |
636 | /* indicate if acceleration can be working */ | |
637 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
638 | /* get the crtc_id from the mode object id? */ | |
639 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
640 | /* query hw IP info */ | |
641 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
642 | /* query hw IP instance count for the specified type */ | |
643 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
644 | /* timestamp for GL_ARB_timer_query */ | |
645 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
646 | /* Query the firmware version */ | |
647 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
648 | /* Subquery id: Query VCE firmware version */ | |
649 | #define AMDGPU_INFO_FW_VCE 0x1 | |
650 | /* Subquery id: Query UVD firmware version */ | |
651 | #define AMDGPU_INFO_FW_UVD 0x2 | |
652 | /* Subquery id: Query GMC firmware version */ | |
653 | #define AMDGPU_INFO_FW_GMC 0x03 | |
654 | /* Subquery id: Query GFX ME firmware version */ | |
655 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
656 | /* Subquery id: Query GFX PFP firmware version */ | |
657 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
658 | /* Subquery id: Query GFX CE firmware version */ | |
659 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
660 | /* Subquery id: Query GFX RLC firmware version */ | |
661 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
662 | /* Subquery id: Query GFX MEC firmware version */ | |
663 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
664 | /* Subquery id: Query SMC firmware version */ | |
665 | #define AMDGPU_INFO_FW_SMC 0x0a | |
666 | /* Subquery id: Query SDMA firmware version */ | |
667 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
668 | /* Subquery id: Query PSP SOS firmware version */ |
669 | #define AMDGPU_INFO_FW_SOS 0x0c | |
670 | /* Subquery id: Query PSP ASD firmware version */ | |
671 | #define AMDGPU_INFO_FW_ASD 0x0d | |
3ac952b1 AD |
672 | /* Subquery id: Query VCN firmware version */ |
673 | #define AMDGPU_INFO_FW_VCN 0x0e | |
621a6318 HR |
674 | /* Subquery id: Query GFX RLC SRLC firmware version */ |
675 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f | |
676 | /* Subquery id: Query GFX RLC SRLG firmware version */ | |
677 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 | |
678 | /* Subquery id: Query GFX RLC SRLS firmware version */ | |
679 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 | |
4d11b4b2 DF |
680 | /* Subquery id: Query DMCU firmware version */ |
681 | #define AMDGPU_INFO_FW_DMCU 0x12 | |
81629cba AD |
682 | /* number of bytes moved for TTM migration */ |
683 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
684 | /* the used VRAM size */ | |
685 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
686 | /* the used GTT size */ | |
687 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
688 | /* Information about GDS, etc. resource configuration */ | |
689 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
690 | /* Query information about VRAM and GTT domains */ | |
691 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
692 | /* Query information about register in MMR address space*/ | |
693 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
694 | /* Query information about device: rev id, family, etc. */ | |
695 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
696 | /* visible vram usage */ | |
697 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
698 | /* number of TTM buffer evictions */ |
699 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
700 | /* Query memory about VRAM and GTT domains */ |
701 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
702 | /* Query vce clock table */ |
703 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
704 | /* Query vbios related information */ |
705 | #define AMDGPU_INFO_VBIOS 0x1B | |
706 | /* Subquery id: Query vbios size */ | |
707 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
708 | /* Subquery id: Query vbios image */ | |
709 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
44879b62 AN |
710 | /* Query UVD handles */ |
711 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
712 | /* Query sensor related information */ |
713 | #define AMDGPU_INFO_SENSOR 0x1D | |
714 | /* Subquery id: Query GPU shader clock */ | |
715 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
716 | /* Subquery id: Query GPU memory clock */ | |
717 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
718 | /* Subquery id: Query GPU temperature */ | |
719 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
720 | /* Subquery id: Query GPU load */ | |
721 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
722 | /* Subquery id: Query average GPU power */ | |
723 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
724 | /* Subquery id: Query northbridge voltage */ | |
725 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
726 | /* Subquery id: Query graphics voltage */ | |
727 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
60bbade2 RZ |
728 | /* Subquery id: Query GPU stable pstate shader clock */ |
729 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 | |
730 | /* Subquery id: Query GPU stable pstate memory clock */ | |
731 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 | |
68e2c5ff MO |
732 | /* Number of VRAM page faults on CPU access. */ |
733 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | |
1f7251b7 | 734 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
81629cba AD |
735 | |
736 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
737 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
738 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
739 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
740 | ||
000cab9a HR |
741 | struct drm_amdgpu_query_fw { |
742 | /** AMDGPU_INFO_FW_* */ | |
743 | __u32 fw_type; | |
744 | /** | |
745 | * Index of the IP if there are more IPs of | |
746 | * the same type. | |
747 | */ | |
748 | __u32 ip_instance; | |
749 | /** | |
750 | * Index of the engine. Whether this is used depends | |
751 | * on the firmware type. (e.g. MEC, SDMA) | |
752 | */ | |
753 | __u32 index; | |
754 | __u32 _pad; | |
755 | }; | |
756 | ||
81629cba AD |
757 | /* Input structure for the INFO ioctl */ |
758 | struct drm_amdgpu_info { | |
759 | /* Where the return value will be stored */ | |
2ce9dde0 | 760 | __u64 return_pointer; |
81629cba AD |
761 | /* The size of the return value. Just like "size" in "snprintf", |
762 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 763 | __u32 return_size; |
81629cba | 764 | /* The query request id. */ |
2ce9dde0 | 765 | __u32 query; |
81629cba AD |
766 | |
767 | union { | |
768 | struct { | |
2ce9dde0 MR |
769 | __u32 id; |
770 | __u32 _pad; | |
81629cba AD |
771 | } mode_crtc; |
772 | ||
773 | struct { | |
774 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 775 | __u32 type; |
81629cba | 776 | /** |
675da0dd CK |
777 | * Index of the IP if there are more IPs of the same |
778 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 779 | */ |
2ce9dde0 | 780 | __u32 ip_instance; |
81629cba AD |
781 | } query_hw_ip; |
782 | ||
783 | struct { | |
2ce9dde0 | 784 | __u32 dword_offset; |
675da0dd | 785 | /** number of registers to read */ |
2ce9dde0 MR |
786 | __u32 count; |
787 | __u32 instance; | |
675da0dd | 788 | /** For future use, no flags defined so far */ |
2ce9dde0 | 789 | __u32 flags; |
81629cba AD |
790 | } read_mmr_reg; |
791 | ||
000cab9a | 792 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
793 | |
794 | struct { | |
795 | __u32 type; | |
796 | __u32 offset; | |
797 | } vbios_info; | |
5ebbac4b AD |
798 | |
799 | struct { | |
800 | __u32 type; | |
801 | } sensor_info; | |
81629cba AD |
802 | }; |
803 | }; | |
804 | ||
805 | struct drm_amdgpu_info_gds { | |
806 | /** GDS GFX partition size */ | |
2ce9dde0 | 807 | __u32 gds_gfx_partition_size; |
81629cba | 808 | /** GDS compute partition size */ |
2ce9dde0 | 809 | __u32 compute_partition_size; |
81629cba | 810 | /** total GDS memory size */ |
2ce9dde0 | 811 | __u32 gds_total_size; |
81629cba | 812 | /** GWS size per GFX partition */ |
2ce9dde0 | 813 | __u32 gws_per_gfx_partition; |
81629cba | 814 | /** GSW size per compute partition */ |
2ce9dde0 | 815 | __u32 gws_per_compute_partition; |
81629cba | 816 | /** OA size per GFX partition */ |
2ce9dde0 | 817 | __u32 oa_per_gfx_partition; |
81629cba | 818 | /** OA size per compute partition */ |
2ce9dde0 MR |
819 | __u32 oa_per_compute_partition; |
820 | __u32 _pad; | |
81629cba AD |
821 | }; |
822 | ||
823 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
824 | __u64 vram_size; |
825 | __u64 vram_cpu_accessible_size; | |
826 | __u64 gtt_size; | |
81629cba AD |
827 | }; |
828 | ||
e0adf6c8 JZ |
829 | struct drm_amdgpu_heap_info { |
830 | /** max. physical memory */ | |
831 | __u64 total_heap_size; | |
832 | ||
833 | /** Theoretical max. available memory in the given heap */ | |
834 | __u64 usable_heap_size; | |
835 | ||
836 | /** | |
837 | * Number of bytes allocated in the heap. This includes all processes | |
838 | * and private allocations in the kernel. It changes when new buffers | |
839 | * are allocated, freed, and moved. It cannot be larger than | |
840 | * heap_size. | |
841 | */ | |
842 | __u64 heap_usage; | |
843 | ||
844 | /** | |
845 | * Theoretical possible max. size of buffer which | |
846 | * could be allocated in the given heap | |
847 | */ | |
848 | __u64 max_allocation; | |
9f6163e7 JZ |
849 | }; |
850 | ||
e0adf6c8 JZ |
851 | struct drm_amdgpu_memory_info { |
852 | struct drm_amdgpu_heap_info vram; | |
853 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
854 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
855 | }; |
856 | ||
81629cba | 857 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
858 | __u32 ver; |
859 | __u32 feature; | |
81629cba AD |
860 | }; |
861 | ||
81c59f54 KW |
862 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
863 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
864 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
865 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
866 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
867 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
868 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
869 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
1e09b053 | 870 | #define AMDGPU_VRAM_TYPE_DDR4 8 |
81c59f54 | 871 | |
81629cba AD |
872 | struct drm_amdgpu_info_device { |
873 | /** PCI Device ID */ | |
2ce9dde0 | 874 | __u32 device_id; |
81629cba | 875 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
876 | __u32 chip_rev; |
877 | __u32 external_rev; | |
81629cba | 878 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
879 | __u32 pci_rev; |
880 | __u32 family; | |
881 | __u32 num_shader_engines; | |
882 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 883 | /* in KHz */ |
2ce9dde0 MR |
884 | __u32 gpu_counter_freq; |
885 | __u64 max_engine_clock; | |
886 | __u64 max_memory_clock; | |
81629cba | 887 | /* cu information */ |
2ce9dde0 | 888 | __u32 cu_active_number; |
dbfe85ea | 889 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ |
2ce9dde0 MR |
890 | __u32 cu_ao_mask; |
891 | __u32 cu_bitmap[4][4]; | |
81629cba | 892 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
893 | __u32 enabled_rb_pipes_mask; |
894 | __u32 num_rb_pipes; | |
895 | __u32 num_hw_gfx_contexts; | |
896 | __u32 _pad; | |
897 | __u64 ids_flags; | |
81629cba | 898 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 899 | __u64 virtual_address_offset; |
02b70c8c | 900 | /** The maximum virtual address */ |
2ce9dde0 | 901 | __u64 virtual_address_max; |
81629cba | 902 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 903 | __u32 virtual_address_alignment; |
81629cba | 904 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
905 | __u32 pte_fragment_size; |
906 | __u32 gart_page_size; | |
a101a899 | 907 | /** constant engine ram size*/ |
2ce9dde0 | 908 | __u32 ce_ram_size; |
cab6d57c | 909 | /** video memory type info*/ |
2ce9dde0 | 910 | __u32 vram_type; |
81c59f54 | 911 | /** video memory bit width*/ |
2ce9dde0 | 912 | __u32 vram_bit_width; |
fa92754e | 913 | /* vce harvesting instance */ |
2ce9dde0 | 914 | __u32 vce_harvest_config; |
df6e2c4a JZ |
915 | /* gfx double offchip LDS buffers */ |
916 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
917 | /* NGG Primitive Buffer */ |
918 | __u64 prim_buf_gpu_addr; | |
919 | /* NGG Position Buffer */ | |
920 | __u64 pos_buf_gpu_addr; | |
921 | /* NGG Control Sideband */ | |
922 | __u64 cntl_sb_buf_gpu_addr; | |
923 | /* NGG Parameter Cache */ | |
924 | __u64 param_buf_gpu_addr; | |
408bfe7c JZ |
925 | __u32 prim_buf_size; |
926 | __u32 pos_buf_size; | |
927 | __u32 cntl_sb_buf_size; | |
928 | __u32 param_buf_size; | |
929 | /* wavefront size*/ | |
930 | __u32 wave_front_size; | |
931 | /* shader visible vgprs*/ | |
932 | __u32 num_shader_visible_vgprs; | |
933 | /* CU per shader array*/ | |
934 | __u32 num_cu_per_sh; | |
935 | /* number of tcc blocks*/ | |
936 | __u32 num_tcc_blocks; | |
937 | /* gs vgt table depth*/ | |
938 | __u32 gs_vgt_table_depth; | |
939 | /* gs primitive buffer depth*/ | |
940 | __u32 gs_prim_buffer_depth; | |
941 | /* max gs wavefront per vgt*/ | |
942 | __u32 max_gs_waves_per_vgt; | |
943 | __u32 _pad1; | |
dbfe85ea FC |
944 | /* always on cu bitmap */ |
945 | __u32 cu_ao_bitmap[4][4]; | |
5b565e0e CK |
946 | /** Starting high virtual address for UMDs. */ |
947 | __u64 high_va_offset; | |
948 | /** The maximum high virtual address */ | |
949 | __u64 high_va_max; | |
81629cba AD |
950 | }; |
951 | ||
952 | struct drm_amdgpu_info_hw_ip { | |
953 | /** Version of h/w IP */ | |
2ce9dde0 MR |
954 | __u32 hw_ip_version_major; |
955 | __u32 hw_ip_version_minor; | |
81629cba | 956 | /** Capabilities */ |
2ce9dde0 | 957 | __u64 capabilities_flags; |
71062f43 | 958 | /** command buffer address start alignment*/ |
2ce9dde0 | 959 | __u32 ib_start_alignment; |
71062f43 | 960 | /** command buffer size alignment*/ |
2ce9dde0 | 961 | __u32 ib_size_alignment; |
81629cba | 962 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
963 | __u32 available_rings; |
964 | __u32 _pad; | |
81629cba AD |
965 | }; |
966 | ||
44879b62 AN |
967 | struct drm_amdgpu_info_num_handles { |
968 | /** Max handles as supported by firmware for UVD */ | |
969 | __u32 uvd_max_handles; | |
970 | /** Handles currently in use for UVD */ | |
971 | __u32 uvd_used_handles; | |
972 | }; | |
973 | ||
bbe87974 AD |
974 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
975 | ||
976 | struct drm_amdgpu_info_vce_clock_table_entry { | |
977 | /** System clock */ | |
978 | __u32 sclk; | |
979 | /** Memory clock */ | |
980 | __u32 mclk; | |
981 | /** VCE clock */ | |
982 | __u32 eclk; | |
983 | __u32 pad; | |
984 | }; | |
985 | ||
986 | struct drm_amdgpu_info_vce_clock_table { | |
987 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
988 | __u32 num_valid_entries; | |
989 | __u32 pad; | |
990 | }; | |
991 | ||
81629cba AD |
992 | /* |
993 | * Supported GPU families | |
994 | */ | |
995 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 996 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
997 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
998 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
999 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 1000 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 1001 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
2ca8a5d2 | 1002 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
81629cba | 1003 | |
cfa7152f EV |
1004 | #if defined(__cplusplus) |
1005 | } | |
1006 | #endif | |
1007 | ||
81629cba | 1008 | #endif |