projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| 308e5bcb JB |
1 | /* |
| 2 | * Copyright 2011 Intel Corporation | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice (including the next | |
| 12 | * paragraph) shall be included in all copies or substantial portions of the | |
| 13 | * Software. | |
| 14 | * | |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 18 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef DRM_FOURCC_H | |
| 25 | #define DRM_FOURCC_H | |
| 26 | ||
| 47f06c2f | 27 | #include "drm.h" |
| 308e5bcb | 28 | |
| ebbb0e5c EV |
29 | #if defined(__cplusplus) |
| 30 | extern "C" { | |
| 31 | #endif | |
| 32 | ||
| 7e7b68ef BS |
33 | /** |
| 34 | * DOC: overview | |
| 35 | * | |
| 36 | * In the DRM subsystem, framebuffer pixel formats are described using the | |
| 37 | * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the | |
| 38 | * fourcc code, a Format Modifier may optionally be provided, in order to | |
| 39 | * further describe the buffer's format - for example tiling or compression. | |
| 40 | * | |
| 41 | * Format Modifiers | |
| 42 | * ---------------- | |
| 43 | * | |
| 44 | * Format modifiers are used in conjunction with a fourcc code, forming a | |
| 45 | * unique fourcc:modifier pair. This format:modifier pair must fully define the | |
| 46 | * format and data layout of the buffer, and should be the only way to describe | |
| 47 | * that particular buffer. | |
| 48 | * | |
| 49 | * Having multiple fourcc:modifier pairs which describe the same layout should | |
| 50 | * be avoided, as such aliases run the risk of different drivers exposing | |
| 51 | * different names for the same data format, forcing userspace to understand | |
| 52 | * that they are aliases. | |
| 53 | * | |
| 54 | * Format modifiers may change any property of the buffer, including the number | |
| 55 | * of planes and/or the required allocation size. Format modifiers are | |
| 56 | * vendor-namespaced, and as such the relationship between a fourcc code and a | |
| 57 | * modifier is specific to the modifer being used. For example, some modifiers | |
| 58 | * may preserve meaning - such as number of planes - from the fourcc code, | |
| 59 | * whereas others may not. | |
| 60 | * | |
| 61 | * Vendors should document their modifier usage in as much detail as | |
| 62 | * possible, to ensure maximum compatibility across devices, drivers and | |
| 63 | * applications. | |
| 64 | * | |
| 65 | * The authoritative list of format modifier codes is found in | |
| 66 | * `include/uapi/drm/drm_fourcc.h` | |
| 67 | */ | |
| 68 | ||
| 64760a4e VS |
69 | #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ |
| 70 | ((__u32)(c) << 16) | ((__u32)(d) << 24)) | |
| 308e5bcb | 71 | |
| 04b3924d VS |
72 | #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ |
| 73 | ||
| 70109354 CW |
74 | /* Reserve 0 for the invalid format specifier */ |
| 75 | #define DRM_FORMAT_INVALID 0 | |
| 76 | ||
| 04b3924d VS |
77 | /* color index */ |
| 78 | #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ | |
| 79 | ||
| 1055e068 CV |
80 | /* 8 bpp Red */ |
| 81 | #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ | |
| 82 | ||
| fd056f05 RH |
83 | /* 16 bpp Red */ |
| 84 | #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ | |
| 85 | ||
| 1055e068 CV |
86 | /* 16 bpp RG */ |
| 87 | #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ | |
| 88 | #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ | |
| 89 | ||
| fd056f05 RH |
90 | /* 32 bpp RG */ |
| 91 | #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ | |
| 92 | #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ | |
| 93 | ||
| 04b3924d VS |
94 | /* 8 bpp RGB */ |
| 95 | #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ | |
| 96 | #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ | |
| 97 | ||
| 98 | /* 16 bpp RGB */ | |
| 99 | #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ | |
| 100 | #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ | |
| 101 | #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ | |
| 102 | #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ | |
| 103 | ||
| 104 | #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ | |
| 105 | #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ | |
| 106 | #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ | |
| 107 | #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ | |
| 108 | ||
| 109 | #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ | |
| 110 | #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ | |
| 111 | #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ | |
| 112 | #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ | |
| 113 | ||
| 114 | #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ | |
| 115 | #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ | |
| 116 | #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ | |
| 117 | #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ | |
| 118 | ||
| 119 | #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ | |
| 120 | #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ | |
| 308e5bcb | 121 | |
| 04b3924d VS |
122 | /* 24 bpp RGB */ |
| 123 | #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ | |
| 124 | #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ | |
| 308e5bcb | 125 | |
| 04b3924d VS |
126 | /* 32 bpp RGB */ |
| 127 | #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ | |
| 128 | #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ | |
| 129 | #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ | |
| 130 | #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ | |
| 308e5bcb | 131 | |
| 04b3924d VS |
132 | #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ |
| 133 | #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ | |
| 134 | #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ | |
| 135 | #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ | |
| 136 | ||
| 137 | #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ | |
| 138 | #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ | |
| 139 | #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ | |
| 140 | #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ | |
| 141 | ||
| 142 | #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ | |
| 143 | #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ | |
| 144 | #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ | |
| 145 | #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ | |
| 146 | ||
| 147 | /* packed YCbCr */ | |
| 148 | #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ | |
| 149 | #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ | |
| 150 | #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ | |
| 151 | #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ | |
| 152 | ||
| 153 | #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ | |
| 61e49394 | 154 | #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ |
| 04b3924d | 155 | |
| 697b6b85 AG |
156 | /* |
| 157 | * packed YCbCr420 2x2 tiled formats | |
| 158 | * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile | |
| 159 | */ | |
| 160 | /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ | |
| 161 | #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') | |
| 162 | /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ | |
| 163 | #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') | |
| 164 | ||
| 165 | /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ | |
| 166 | #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') | |
| 167 | /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ | |
| 168 | #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') | |
| 169 | ||
| ba2b5277 PZ |
170 | /* |
| 171 | * 2 plane RGB + A | |
| 172 | * index 0 = RGB plane, same format as the corresponding non _A8 format has | |
| 173 | * index 1 = A plane, [7:0] A | |
| 174 | */ | |
| 175 | #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') | |
| 176 | #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') | |
| 177 | #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') | |
| 178 | #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') | |
| 179 | #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') | |
| 180 | #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') | |
| 181 | #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') | |
| 182 | #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') | |
| 183 | ||
| 04b3924d VS |
184 | /* |
| 185 | * 2 plane YCbCr | |
| 186 | * index 0 = Y plane, [7:0] Y | |
| 187 | * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian | |
| 188 | * or | |
| 189 | * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian | |
| 190 | */ | |
| 191 | #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ | |
| 192 | #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ | |
| 193 | #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ | |
| 194 | #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ | |
| ba623f6a LP |
195 | #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ |
| 196 | #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ | |
| 04b3924d VS |
197 | |
| 198 | /* | |
| 199 | * 3 plane YCbCr | |
| 200 | * index 0: Y plane, [7:0] Y | |
| 201 | * index 1: Cb plane, [7:0] Cb | |
| 202 | * index 2: Cr plane, [7:0] Cr | |
| 203 | * or | |
| 204 | * index 1: Cr plane, [7:0] Cr | |
| 205 | * index 2: Cb plane, [7:0] Cb | |
| 206 | */ | |
| 207 | #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ | |
| 208 | #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ | |
| 209 | #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ | |
| 210 | #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ | |
| 211 | #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ | |
| 212 | #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ | |
| 213 | #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ | |
| 214 | #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ | |
| 215 | #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ | |
| 216 | #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ | |
| 308e5bcb | 217 | |
| e3eb3250 RC |
218 | |
| 219 | /* | |
| 220 | * Format Modifiers: | |
| 221 | * | |
| 222 | * Format modifiers describe, typically, a re-ordering or modification | |
| 223 | * of the data in a plane of an FB. This can be used to express tiled/ | |
| 224 | * swizzled formats, or compression, or a combination of the two. | |
| 225 | * | |
| 226 | * The upper 8 bits of the format modifier are a vendor-id as assigned | |
| 227 | * below. The lower 56 bits are assigned as vendor sees fit. | |
| 228 | */ | |
| 229 | ||
| 230 | /* Vendor Ids: */ | |
| 231 | #define DRM_FORMAT_MOD_NONE 0 | |
| af913418 | 232 | #define DRM_FORMAT_MOD_VENDOR_NONE 0 |
| e3eb3250 RC |
233 | #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
| 234 | #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 | |
| 268892cb | 235 | #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 |
| e3eb3250 RC |
236 | #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 |
| 237 | #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 | |
| 73f1a585 | 238 | #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 |
| 98830d91 | 239 | #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 |
| ce605803 | 240 | #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 |
| 08cba016 PK |
241 | #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 |
| 242 | ||
| e3eb3250 RC |
243 | /* add more to the end as needed */ |
| 244 | ||
| e6fc3b68 BW |
245 | #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) |
| 246 | ||
| e3eb3250 | 247 | #define fourcc_mod_code(vendor, val) \ |
| 5843f4e0 | 248 | ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) |
| e3eb3250 RC |
249 | |
| 250 | /* | |
| 251 | * Format Modifier tokens: | |
| 252 | * | |
| 253 | * When adding a new token please document the layout with a code comment, | |
| 254 | * similar to the fourcc codes above. drm_fourcc.h is considered the | |
| 255 | * authoritative source for all of these. | |
| 256 | */ | |
| 257 | ||
| e6fc3b68 BW |
258 | /* |
| 259 | * Invalid Modifier | |
| 260 | * | |
| 261 | * This modifier can be used as a sentinel to terminate the format modifiers | |
| 262 | * list, or to initialize a variable with an invalid modifier. It might also be | |
| 263 | * used to report an error back to userspace for certain APIs. | |
| 264 | */ | |
| 265 | #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) | |
| 266 | ||
| b9fb2a21 DV |
267 | /* |
| 268 | * Linear Layout | |
| 269 | * | |
| 270 | * Just plain linear layout. Note that this is different from no specifying any | |
| 271 | * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), | |
| 272 | * which tells the driver to also take driver-internal information into account | |
| 273 | * and so might actually result in a tiled framebuffer. | |
| 274 | */ | |
| 275 | #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) | |
| 276 | ||
| 93b81f51 TU |
277 | /* Intel framebuffer modifiers */ |
| 278 | ||
| 279 | /* | |
| 280 | * Intel X-tiling layout | |
| 281 | * | |
| 282 | * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) | |
| 283 | * in row-major layout. Within the tile bytes are laid out row-major, with | |
| 284 | * a platform-dependent stride. On top of that the memory can apply | |
| 285 | * platform-depending swizzling of some higher address bits into bit6. | |
| 286 | * | |
| 287 | * This format is highly platforms specific and not useful for cross-driver | |
| 288 | * sharing. It exists since on a given platform it does uniquely identify the | |
| 289 | * layout in a simple way for i915-specific userspace. | |
| 290 | */ | |
| 291 | #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) | |
| 292 | ||
| 293 | /* | |
| 294 | * Intel Y-tiling layout | |
| 295 | * | |
| 296 | * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) | |
| 297 | * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) | |
| 298 | * chunks column-major, with a platform-dependent height. On top of that the | |
| 299 | * memory can apply platform-depending swizzling of some higher address bits | |
| 300 | * into bit6. | |
| 301 | * | |
| 302 | * This format is highly platforms specific and not useful for cross-driver | |
| 303 | * sharing. It exists since on a given platform it does uniquely identify the | |
| 304 | * layout in a simple way for i915-specific userspace. | |
| 305 | */ | |
| 306 | #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) | |
| 307 | ||
| b5ff6e16 TU |
308 | /* |
| 309 | * Intel Yf-tiling layout | |
| 310 | * | |
| 311 | * This is a tiled layout using 4Kb tiles in row-major layout. | |
| 312 | * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which | |
| 313 | * are arranged in four groups (two wide, two high) with column-major layout. | |
| 314 | * Each group therefore consits out of four 256 byte units, which are also laid | |
| 315 | * out as 2x2 column-major. | |
| 316 | * 256 byte units are made out of four 64 byte blocks of pixels, producing | |
| 317 | * either a square block or a 2:1 unit. | |
| 318 | * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width | |
| 319 | * in pixel depends on the pixel depth. | |
| 320 | */ | |
| 321 | #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) | |
| 322 | ||
| bbfb6ce8 VS |
323 | /* |
| 324 | * Intel color control surface (CCS) for render compression | |
| 325 | * | |
| 326 | * The framebuffer format must be one of the 8:8:8:8 RGB formats. | |
| 327 | * The main surface will be plane index 0 and must be Y/Yf-tiled, | |
| 328 | * the CCS will be plane index 1. | |
| 329 | * | |
| 330 | * Each CCS tile matches a 1024x512 pixel area of the main surface. | |
| 331 | * To match certain aspects of the 3D hardware the CCS is | |
| 332 | * considered to be made up of normal 128Bx32 Y tiles, Thus | |
| 333 | * the CCS pitch must be specified in multiples of 128 bytes. | |
| 334 | * | |
| 335 | * In reality the CCS tile appears to be a 64Bx64 Y tile, composed | |
| 336 | * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. | |
| 337 | * But that fact is not relevant unless the memory is accessed | |
| 338 | * directly. | |
| 339 | */ | |
| 340 | #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) | |
| 341 | #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) | |
| 342 | ||
| 570655b0 RC |
343 | /* |
| 344 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks | |
| 345 | * | |
| 346 | * Macroblocks are laid in a Z-shape, and each pixel data is following the | |
| 347 | * standard NV12 style. | |
| 348 | * As for NV12, an image is the result of two frame buffers: one for Y, | |
| 349 | * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). | |
| 350 | * Alignment requirements are (for each buffer): | |
| 351 | * - multiple of 128 pixels for the width | |
| 352 | * - multiple of 32 pixels for the height | |
| 353 | * | |
| 4a3d0cb0 | 354 | * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html |
| 570655b0 RC |
355 | */ |
| 356 | #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) | |
| 357 | ||
| b1c7a574 AP |
358 | /* |
| 359 | * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks | |
| 360 | * | |
| 361 | * This is a simple tiled layout using tiles of 16x16 pixels in a row-major | |
| 362 | * layout. For YCbCr formats Cb/Cr components are taken in such a way that | |
| 363 | * they correspond to their 16x16 luma block. | |
| 364 | */ | |
| 365 | #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) | |
| 366 | ||
| 2a8536f6 JS |
367 | /* |
| 368 | * Qualcomm Compressed Format | |
| 369 | * | |
| 370 | * Refers to a compressed variant of the base format that is compressed. | |
| 371 | * Implementation may be platform and base-format specific. | |
| 372 | * | |
| 373 | * Each macrotile consists of m x n (mostly 4 x 4) tiles. | |
| 374 | * Pixel data pitch/stride is aligned with macrotile width. | |
| 375 | * Pixel data height is aligned with macrotile height. | |
| 376 | * Entire pixel data buffer is aligned with 4k(bytes). | |
| 377 | */ | |
| 378 | #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) | |
| 379 | ||
| 73f1a585 PZ |
380 | /* Vivante framebuffer modifiers */ |
| 381 | ||
| 382 | /* | |
| 383 | * Vivante 4x4 tiling layout | |
| 384 | * | |
| 385 | * This is a simple tiled layout using tiles of 4x4 pixels in a row-major | |
| 386 | * layout. | |
| 387 | */ | |
| 388 | #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) | |
| 389 | ||
| 390 | /* | |
| 391 | * Vivante 64x64 super-tiling layout | |
| 392 | * | |
| 393 | * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile | |
| 394 | * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- | |
| 395 | * major layout. | |
| 396 | * | |
| 397 | * For more information: see | |
| 398 | * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling | |
| 399 | */ | |
| 400 | #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) | |
| 401 | ||
| 402 | /* | |
| 403 | * Vivante 4x4 tiling layout for dual-pipe | |
| 404 | * | |
| 405 | * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a | |
| 406 | * different base address. Offsets from the base addresses are therefore halved | |
| 407 | * compared to the non-split tiled layout. | |
| 408 | */ | |
| 409 | #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) | |
| 410 | ||
| 411 | /* | |
| 412 | * Vivante 64x64 super-tiling layout for dual-pipe | |
| 413 | * | |
| 414 | * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile | |
| 415 | * starts at a different base address. Offsets from the base addresses are | |
| 416 | * therefore halved compared to the non-split super-tiled layout. | |
| 417 | */ | |
| 418 | #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) | |
| 419 | ||
| 268892cb | 420 | /* NVIDIA frame buffer modifiers */ |
| 5e91144d AC |
421 | |
| 422 | /* | |
| 423 | * Tegra Tiled Layout, used by Tegra 2, 3 and 4. | |
| 424 | * | |
| 425 | * Pixels are arranged in simple tiles of 16 x 16 bytes. | |
| 426 | */ | |
| 268892cb | 427 | #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) |
| 5e91144d AC |
428 | |
| 429 | /* | |
| 268892cb | 430 | * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later |
| 5e91144d AC |
431 | * |
| 432 | * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked | |
| 433 | * vertically by a power of 2 (1 to 32 GOBs) to form a block. | |
| 434 | * | |
| 435 | * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. | |
| 436 | * | |
| 437 | * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. | |
| 438 | * Valid values are: | |
| 439 | * | |
| 440 | * 0 == ONE_GOB | |
| 441 | * 1 == TWO_GOBS | |
| 442 | * 2 == FOUR_GOBS | |
| 443 | * 3 == EIGHT_GOBS | |
| 444 | * 4 == SIXTEEN_GOBS | |
| 445 | * 5 == THIRTYTWO_GOBS | |
| 446 | * | |
| 447 | * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format | |
| 448 | * in full detail. | |
| 449 | */ | |
| 268892cb TR |
450 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ |
| 451 | fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) | |
| 452 | ||
| 453 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ | |
| 454 | fourcc_mod_code(NVIDIA, 0x10) | |
| 455 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ | |
| 456 | fourcc_mod_code(NVIDIA, 0x11) | |
| 457 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ | |
| 458 | fourcc_mod_code(NVIDIA, 0x12) | |
| 459 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ | |
| 460 | fourcc_mod_code(NVIDIA, 0x13) | |
| 461 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ | |
| 462 | fourcc_mod_code(NVIDIA, 0x14) | |
| 463 | #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ | |
| 464 | fourcc_mod_code(NVIDIA, 0x15) | |
| 5e91144d | 465 | |
| e065a8dd DS |
466 | /* |
| 467 | * Some Broadcom modifiers take parameters, for example the number of | |
| 468 | * vertical lines in the image. Reserve the lower 32 bits for modifier | |
| 469 | * type, and the next 24 bits for parameters. Top 8 bits are the | |
| 470 | * vendor code. | |
| 471 | */ | |
| 472 | #define __fourcc_mod_broadcom_param_shift 8 | |
| 473 | #define __fourcc_mod_broadcom_param_bits 48 | |
| 474 | #define fourcc_mod_broadcom_code(val, params) \ | |
| 475 | fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) | |
| 476 | #define fourcc_mod_broadcom_param(m) \ | |
| 477 | ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ | |
| 478 | ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) | |
| 479 | #define fourcc_mod_broadcom_mod(m) \ | |
| 480 | ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ | |
| 481 | __fourcc_mod_broadcom_param_shift)) | |
| 482 | ||
| 98830d91 EA |
483 | /* |
| 484 | * Broadcom VC4 "T" format | |
| 485 | * | |
| 486 | * This is the primary layout that the V3D GPU can texture from (it | |
| 487 | * can't do linear). The T format has: | |
| 488 | * | |
| 489 | * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 | |
| 490 | * pixels at 32 bit depth. | |
| 491 | * | |
| 492 | * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually | |
| 493 | * 16x16 pixels). | |
| 494 | * | |
| 495 | * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On | |
| 496 | * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows | |
| 497 | * they're (TR, BR, BL, TL), where bottom left is start of memory. | |
| 498 | * | |
| 499 | * - an image made of 4k tiles in rows either left-to-right (even rows of 4k | |
| 500 | * tiles) or right-to-left (odd rows of 4k tiles). | |
| 501 | */ | |
| 502 | #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) | |
| 503 | ||
| e065a8dd DS |
504 | /* |
| 505 | * Broadcom SAND format | |
| 506 | * | |
| 507 | * This is the native format that the H.264 codec block uses. For VC4 | |
| 508 | * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. | |
| 509 | * | |
| 510 | * The image can be considered to be split into columns, and the | |
| 511 | * columns are placed consecutively into memory. The width of those | |
| 512 | * columns can be either 32, 64, 128, or 256 pixels, but in practice | |
| 513 | * only 128 pixel columns are used. | |
| 514 | * | |
| 515 | * The pitch between the start of each column is set to optimally | |
| 516 | * switch between SDRAM banks. This is passed as the number of lines | |
| 517 | * of column width in the modifier (we can't use the stride value due | |
| 518 | * to various core checks that look at it , so you should set the | |
| 519 | * stride to width*cpp). | |
| 520 | * | |
| 521 | * Note that the column height for this format modifier is the same | |
| 522 | * for all of the planes, assuming that each column contains both Y | |
| 523 | * and UV. Some SAND-using hardware stores UV in a separate tiled | |
| 524 | * image from Y to reduce the column height, which is not supported | |
| 525 | * with these modifiers. | |
| 526 | */ | |
| 527 | ||
| 528 | #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ | |
| 529 | fourcc_mod_broadcom_code(2, v) | |
| 530 | #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ | |
| 531 | fourcc_mod_broadcom_code(3, v) | |
| 532 | #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ | |
| 533 | fourcc_mod_broadcom_code(4, v) | |
| 534 | #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ | |
| 535 | fourcc_mod_broadcom_code(5, v) | |
| 536 | ||
| 537 | #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ | |
| 538 | DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) | |
| 539 | #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ | |
| 540 | DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) | |
| 541 | #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ | |
| 542 | DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) | |
| 543 | #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ | |
| 544 | DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) | |
| 545 | ||
| 14d9deeb EA |
546 | /* Broadcom UIF format |
| 547 | * | |
| 548 | * This is the common format for the current Broadcom multimedia | |
| 549 | * blocks, including V3D 3.x and newer, newer video codecs, and | |
| 550 | * displays. | |
| 551 | * | |
| 552 | * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), | |
| 553 | * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are | |
| 554 | * stored in columns, with padding between the columns to ensure that | |
| 555 | * moving from one column to the next doesn't hit the same SDRAM page | |
| 556 | * bank. | |
| 557 | * | |
| 558 | * To calculate the padding, it is assumed that each hardware block | |
| 559 | * and the software driving it knows the platform's SDRAM page size, | |
| 560 | * number of banks, and XOR address, and that it's identical between | |
| 561 | * all blocks using the format. This tiling modifier will use XOR as | |
| 562 | * necessary to reduce the padding. If a hardware block can't do XOR, | |
| 563 | * the assumption is that a no-XOR tiling modifier will be created. | |
| 564 | */ | |
| 565 | #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) | |
| 566 | ||
| ce605803 AKH |
567 | /* |
| 568 | * Arm Framebuffer Compression (AFBC) modifiers | |
| 569 | * | |
| 570 | * AFBC is a proprietary lossless image compression protocol and format. | |
| 571 | * It provides fine-grained random access and minimizes the amount of data | |
| 572 | * transferred between IP blocks. | |
| 573 | * | |
| 574 | * AFBC has several features which may be supported and/or used, which are | |
| 575 | * represented using bits in the modifier. Not all combinations are valid, | |
| 576 | * and different devices or use-cases may support different combinations. | |
| 3affaa5a BS |
577 | * |
| 578 | * Further information on the use of AFBC modifiers can be found in | |
| 579 | * Documentation/gpu/afbc.rst | |
| ce605803 AKH |
580 | */ |
| 581 | #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) | |
| 582 | ||
| 583 | /* | |
| 584 | * AFBC superblock size | |
| 585 | * | |
| 586 | * Indicates the superblock size(s) used for the AFBC buffer. The buffer | |
| 587 | * size (in pixels) must be aligned to a multiple of the superblock size. | |
| 588 | * Four lowest significant bits(LSBs) are reserved for block size. | |
| 2db8ebca MF |
589 | * |
| 590 | * Where one superblock size is specified, it applies to all planes of the | |
| 591 | * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, | |
| 592 | * the first applies to the Luma plane and the second applies to the Chroma | |
| 593 | * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). | |
| 594 | * Multiple superblock sizes are only valid for multi-plane YCbCr formats. | |
| ce605803 AKH |
595 | */ |
| 596 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf | |
| 597 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) | |
| 598 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) | |
| 2db8ebca MF |
599 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) |
| 600 | #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) | |
| ce605803 AKH |
601 | |
| 602 | /* | |
| 603 | * AFBC lossless colorspace transform | |
| 604 | * | |
| 605 | * Indicates that the buffer makes use of the AFBC lossless colorspace | |
| 606 | * transform. | |
| 607 | */ | |
| 608 | #define AFBC_FORMAT_MOD_YTR (1ULL << 4) | |
| 609 | ||
| 610 | /* | |
| 611 | * AFBC block-split | |
| 612 | * | |
| 613 | * Indicates that the payload of each superblock is split. The second | |
| 614 | * half of the payload is positioned at a predefined offset from the start | |
| 615 | * of the superblock payload. | |
| 616 | */ | |
| 617 | #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) | |
| 618 | ||
| 619 | /* | |
| 620 | * AFBC sparse layout | |
| 621 | * | |
| 622 | * This flag indicates that the payload of each superblock must be stored at a | |
| 623 | * predefined position relative to the other superblocks in the same AFBC | |
| 624 | * buffer. This order is the same order used by the header buffer. In this mode | |
| 625 | * each superblock is given the same amount of space as an uncompressed | |
| 626 | * superblock of the particular format would require, rounding up to the next | |
| 627 | * multiple of 128 bytes in size. | |
| 628 | */ | |
| 629 | #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) | |
| 630 | ||
| 631 | /* | |
| 632 | * AFBC copy-block restrict | |
| 633 | * | |
| 634 | * Buffers with this flag must obey the copy-block restriction. The restriction | |
| 635 | * is such that there are no copy-blocks referring across the border of 8x8 | |
| 636 | * blocks. For the subsampled data the 8x8 limitation is also subsampled. | |
| 637 | */ | |
| 638 | #define AFBC_FORMAT_MOD_CBR (1ULL << 7) | |
| 639 | ||
| 640 | /* | |
| 641 | * AFBC tiled layout | |
| 642 | * | |
| 643 | * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all | |
| 644 | * superblocks inside a tile are stored together in memory. 8x8 tiles are used | |
| 645 | * for pixel formats up to and including 32 bpp while 4x4 tiles are used for | |
| 646 | * larger bpp formats. The order between the tiles is scan line. | |
| 647 | * When the tiled layout is used, the buffer size (in pixels) must be aligned | |
| 648 | * to the tile size. | |
| 649 | */ | |
| 650 | #define AFBC_FORMAT_MOD_TILED (1ULL << 8) | |
| 651 | ||
| 652 | /* | |
| 653 | * AFBC solid color blocks | |
| 654 | * | |
| 655 | * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth | |
| 656 | * can be reduced if a whole superblock is a single color. | |
| 657 | */ | |
| 658 | #define AFBC_FORMAT_MOD_SC (1ULL << 9) | |
| 659 | ||
| 2db8ebca MF |
660 | /* |
| 661 | * AFBC double-buffer | |
| 662 | * | |
| 663 | * Indicates that the buffer is allocated in a layout safe for front-buffer | |
| 664 | * rendering. | |
| 665 | */ | |
| 666 | #define AFBC_FORMAT_MOD_DB (1ULL << 10) | |
| 667 | ||
| 668 | /* | |
| 669 | * AFBC buffer content hints | |
| 670 | * | |
| 671 | * Indicates that the buffer includes per-superblock content hints. | |
| 672 | */ | |
| 673 | #define AFBC_FORMAT_MOD_BCH (1ULL << 11) | |
| 674 | ||
| 08cba016 PK |
675 | /* |
| 676 | * Allwinner tiled modifier | |
| 677 | * | |
| 678 | * This tiling mode is implemented by the VPU found on all Allwinner platforms, | |
| 679 | * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 | |
| 680 | * planes. | |
| 681 | * | |
| 682 | * With this tiling, the luminance samples are disposed in tiles representing | |
| 683 | * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. | |
| 684 | * The pixel order in each tile is linear and the tiles are disposed linearly, | |
| 685 | * both in row-major order. | |
| 686 | */ | |
| 687 | #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) | |
| 688 | ||
| ebbb0e5c EV |
689 | #if defined(__cplusplus) |
| 690 | } | |
| 691 | #endif | |
| 692 | ||
| 308e5bcb | 693 | #endif /* DRM_FOURCC_H */ |