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target/ppc: Fix slbia TLB invalidation gap
[thirdparty/qemu.git] / ioport.c
CommitLineData
32993977
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1/*
2 * QEMU System Emulator
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24/*
25 * splitted out ioport related stuffs from vl.c.
26 */
27
d38ea87a 28#include "qemu/osdep.h"
33c11879 29#include "cpu.h"
022c62cb 30#include "exec/ioport.h"
0ab8ed18 31#include "trace-root.h"
022c62cb 32#include "exec/memory.h"
b40acf99 33#include "exec/address-spaces.h"
32993977 34
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35typedef struct MemoryRegionPortioList {
36 MemoryRegion mr;
37 void *portio_opaque;
38 MemoryRegionPortio ports[];
39} MemoryRegionPortioList;
40
3bb28b72
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41static uint64_t unassigned_io_read(void *opaque, hwaddr addr, unsigned size)
42{
43 return -1ULL;
44}
45
46static void unassigned_io_write(void *opaque, hwaddr addr, uint64_t val,
47 unsigned size)
48{
49}
50
51const MemoryRegionOps unassigned_io_ops = {
52 .read = unassigned_io_read,
53 .write = unassigned_io_write,
54 .endianness = DEVICE_NATIVE_ENDIAN,
55};
56
89a80e74 57void cpu_outb(uint32_t addr, uint8_t val)
32993977 58{
6f94b7d9 59 trace_cpu_out(addr, 'b', val);
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60 address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
61 &val, 1);
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62}
63
89a80e74 64void cpu_outw(uint32_t addr, uint16_t val)
32993977 65{
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66 uint8_t buf[2];
67
6f94b7d9 68 trace_cpu_out(addr, 'w', val);
b40acf99 69 stw_p(buf, val);
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70 address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
71 buf, 2);
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72}
73
89a80e74 74void cpu_outl(uint32_t addr, uint32_t val)
32993977 75{
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76 uint8_t buf[4];
77
6f94b7d9 78 trace_cpu_out(addr, 'l', val);
b40acf99 79 stl_p(buf, val);
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80 address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
81 buf, 4);
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82}
83
89a80e74 84uint8_t cpu_inb(uint32_t addr)
32993977 85{
07323531 86 uint8_t val;
b40acf99 87
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88 address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
89 &val, 1);
6f94b7d9 90 trace_cpu_in(addr, 'b', val);
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91 return val;
92}
93
89a80e74 94uint16_t cpu_inw(uint32_t addr)
32993977 95{
b40acf99 96 uint8_t buf[2];
07323531 97 uint16_t val;
b40acf99 98
5c9eb028 99 address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 2);
b40acf99 100 val = lduw_p(buf);
6f94b7d9 101 trace_cpu_in(addr, 'w', val);
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102 return val;
103}
104
89a80e74 105uint32_t cpu_inl(uint32_t addr)
32993977 106{
b40acf99 107 uint8_t buf[4];
07323531 108 uint32_t val;
b40acf99 109
5c9eb028 110 address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 4);
b40acf99 111 val = ldl_p(buf);
6f94b7d9 112 trace_cpu_in(addr, 'l', val);
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113 return val;
114}
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115
116void portio_list_init(PortioList *piolist,
db10ca90 117 Object *owner,
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118 const MemoryRegionPortio *callbacks,
119 void *opaque, const char *name)
120{
121 unsigned n = 0;
122
123 while (callbacks[n].size) {
124 ++n;
125 }
126
127 piolist->ports = callbacks;
128 piolist->nr = 0;
129 piolist->regions = g_new0(MemoryRegion *, n);
130 piolist->address_space = NULL;
131 piolist->opaque = opaque;
db10ca90 132 piolist->owner = owner;
6bf9fd43 133 piolist->name = name;
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134 piolist->flush_coalesced_mmio = false;
135}
136
137void portio_list_set_flush_coalesced(PortioList *piolist)
138{
139 piolist->flush_coalesced_mmio = true;
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140}
141
142void portio_list_destroy(PortioList *piolist)
143{
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144 MemoryRegionPortioList *mrpio;
145 unsigned i;
146
147 for (i = 0; i < piolist->nr; ++i) {
148 mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
d8d95814 149 object_unparent(OBJECT(&mrpio->mr));
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150 g_free(mrpio);
151 }
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152 g_free(piolist->regions);
153}
154
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155static const MemoryRegionPortio *find_portio(MemoryRegionPortioList *mrpio,
156 uint64_t offset, unsigned size,
157 bool write)
158{
159 const MemoryRegionPortio *mrp;
160
161 for (mrp = mrpio->ports; mrp->size; ++mrp) {
162 if (offset >= mrp->offset && offset < mrp->offset + mrp->len &&
163 size == mrp->size &&
164 (write ? (bool)mrp->write : (bool)mrp->read)) {
165 return mrp;
166 }
167 }
168 return NULL;
169}
170
171static uint64_t portio_read(void *opaque, hwaddr addr, unsigned size)
172{
173 MemoryRegionPortioList *mrpio = opaque;
174 const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, false);
175 uint64_t data;
176
177 data = ((uint64_t)1 << (size * 8)) - 1;
178 if (mrp) {
179 data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
180 } else if (size == 2) {
181 mrp = find_portio(mrpio, addr, 1, false);
147ed379
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182 if (mrp) {
183 data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
184 if (addr + 1 < mrp->offset + mrp->len) {
185 data |= mrp->read(mrpio->portio_opaque, mrp->base + addr + 1) << 8;
186 } else {
187 data |= 0xff00;
188 }
189 }
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190 }
191 return data;
192}
193
194static void portio_write(void *opaque, hwaddr addr, uint64_t data,
195 unsigned size)
196{
197 MemoryRegionPortioList *mrpio = opaque;
198 const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, true);
199
200 if (mrp) {
201 mrp->write(mrpio->portio_opaque, mrp->base + addr, data);
202 } else if (size == 2) {
203 mrp = find_portio(mrpio, addr, 1, true);
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204 if (mrp) {
205 mrp->write(mrpio->portio_opaque, mrp->base + addr, data & 0xff);
206 if (addr + 1 < mrp->offset + mrp->len) {
207 mrp->write(mrpio->portio_opaque, mrp->base + addr + 1, data >> 8);
208 }
209 }
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210 }
211}
212
213static const MemoryRegionOps portio_ops = {
214 .read = portio_read,
215 .write = portio_write,
f36a6382 216 .endianness = DEVICE_LITTLE_ENDIAN,
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217 .valid.unaligned = true,
218 .impl.unaligned = true,
219};
220
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221static void portio_list_add_1(PortioList *piolist,
222 const MemoryRegionPortio *pio_init,
223 unsigned count, unsigned start,
224 unsigned off_low, unsigned off_high)
225{
b40acf99 226 MemoryRegionPortioList *mrpio;
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227 unsigned i;
228
229 /* Copy the sub-list and null-terminate it. */
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230 mrpio = g_malloc0(sizeof(MemoryRegionPortioList) +
231 sizeof(MemoryRegionPortio) * (count + 1));
232 mrpio->portio_opaque = piolist->opaque;
233 memcpy(mrpio->ports, pio_init, sizeof(MemoryRegionPortio) * count);
234 memset(mrpio->ports + count, 0, sizeof(MemoryRegionPortio));
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235
236 /* Adjust the offsets to all be zero-based for the region. */
237 for (i = 0; i < count; ++i) {
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238 mrpio->ports[i].offset -= off_low;
239 mrpio->ports[i].base = start + off_low;
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240 }
241
db10ca90
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242 memory_region_init_io(&mrpio->mr, piolist->owner, &portio_ops, mrpio,
243 piolist->name, off_high - off_low);
c76bc480
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244 if (piolist->flush_coalesced_mmio) {
245 memory_region_set_flush_coalesced(&mrpio->mr);
246 }
6bf9fd43 247 memory_region_add_subregion(piolist->address_space,
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248 start + off_low, &mrpio->mr);
249 piolist->regions[piolist->nr] = &mrpio->mr;
de58ac72 250 ++piolist->nr;
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251}
252
253void portio_list_add(PortioList *piolist,
254 MemoryRegion *address_space,
255 uint32_t start)
256{
257 const MemoryRegionPortio *pio, *pio_start = piolist->ports;
258 unsigned int off_low, off_high, off_last, count;
259
260 piolist->address_space = address_space;
261
262 /* Handle the first entry specially. */
263 off_last = off_low = pio_start->offset;
4080a13c 264 off_high = off_low + pio_start->len + pio_start->size - 1;
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265 count = 1;
266
267 for (pio = pio_start + 1; pio->size != 0; pio++, count++) {
268 /* All entries must be sorted by offset. */
269 assert(pio->offset >= off_last);
270 off_last = pio->offset;
271
272 /* If we see a hole, break the region. */
273 if (off_last > off_high) {
274 portio_list_add_1(piolist, pio_start, count, start, off_low,
275 off_high);
276 /* ... and start collecting anew. */
277 pio_start = pio;
278 off_low = off_last;
4080a13c 279 off_high = off_low + pio->len + pio_start->size - 1;
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280 count = 0;
281 } else if (off_last + pio->len > off_high) {
4080a13c 282 off_high = off_last + pio->len + pio_start->size - 1;
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283 }
284 }
285
286 /* There will always be an open sub-list. */
287 portio_list_add_1(piolist, pio_start, count, start, off_low, off_high);
288}
289
290void portio_list_del(PortioList *piolist)
291{
b40acf99 292 MemoryRegionPortioList *mrpio;
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293 unsigned i;
294
295 for (i = 0; i < piolist->nr; ++i) {
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296 mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
297 memory_region_del_subregion(piolist->address_space, &mrpio->mr);
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298 }
299}