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52a65ff5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
a34db9b2 IM |
3 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
4 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
5 | * |
6 | * This file contains driver APIs to the irq subsystem. | |
7 | */ | |
8 | ||
97fd75b7 AM |
9 | #define pr_fmt(fmt) "genirq: " fmt |
10 | ||
1da177e4 | 11 | #include <linux/irq.h> |
3aa551c9 | 12 | #include <linux/kthread.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/random.h> | |
15 | #include <linux/interrupt.h> | |
1aeb272c | 16 | #include <linux/slab.h> |
3aa551c9 | 17 | #include <linux/sched.h> |
8bd75c77 | 18 | #include <linux/sched/rt.h> |
0881e7bd | 19 | #include <linux/sched/task.h> |
ae7e81c0 | 20 | #include <uapi/linux/sched/types.h> |
4d1d61a6 | 21 | #include <linux/task_work.h> |
1da177e4 LT |
22 | |
23 | #include "internals.h" | |
24 | ||
8d32a307 TG |
25 | #ifdef CONFIG_IRQ_FORCED_THREADING |
26 | __read_mostly bool force_irqthreads; | |
47b82e88 | 27 | EXPORT_SYMBOL_GPL(force_irqthreads); |
8d32a307 TG |
28 | |
29 | static int __init setup_forced_irqthreads(char *arg) | |
30 | { | |
31 | force_irqthreads = true; | |
32 | return 0; | |
33 | } | |
34 | early_param("threadirqs", setup_forced_irqthreads); | |
35 | #endif | |
36 | ||
18258f72 | 37 | static void __synchronize_hardirq(struct irq_desc *desc) |
1da177e4 | 38 | { |
32f4125e | 39 | bool inprogress; |
1da177e4 | 40 | |
a98ce5c6 HX |
41 | do { |
42 | unsigned long flags; | |
43 | ||
44 | /* | |
45 | * Wait until we're out of the critical section. This might | |
46 | * give the wrong answer due to the lack of memory barriers. | |
47 | */ | |
32f4125e | 48 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
49 | cpu_relax(); |
50 | ||
51 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 52 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 53 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
239007b8 | 54 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
55 | |
56 | /* Oops, that failed? */ | |
32f4125e | 57 | } while (inprogress); |
18258f72 TG |
58 | } |
59 | ||
60 | /** | |
61 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
62 | * @irq: interrupt number to wait for | |
63 | * | |
64 | * This function waits for any pending hard IRQ handlers for this | |
65 | * interrupt to complete before returning. If you use this | |
66 | * function while holding a resource the IRQ handler may need you | |
67 | * will deadlock. It does not take associated threaded handlers | |
68 | * into account. | |
69 | * | |
70 | * Do not use this for shutdown scenarios where you must be sure | |
71 | * that all parts (hardirq and threaded handler) have completed. | |
72 | * | |
02cea395 PZ |
73 | * Returns: false if a threaded handler is active. |
74 | * | |
18258f72 TG |
75 | * This function may be called - with care - from IRQ context. |
76 | */ | |
02cea395 | 77 | bool synchronize_hardirq(unsigned int irq) |
18258f72 TG |
78 | { |
79 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 80 | |
02cea395 | 81 | if (desc) { |
18258f72 | 82 | __synchronize_hardirq(desc); |
02cea395 PZ |
83 | return !atomic_read(&desc->threads_active); |
84 | } | |
85 | ||
86 | return true; | |
18258f72 TG |
87 | } |
88 | EXPORT_SYMBOL(synchronize_hardirq); | |
89 | ||
90 | /** | |
91 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
92 | * @irq: interrupt number to wait for | |
93 | * | |
94 | * This function waits for any pending IRQ handlers for this interrupt | |
95 | * to complete before returning. If you use this function while | |
96 | * holding a resource the IRQ handler may need you will deadlock. | |
97 | * | |
98 | * This function may be called - with care - from IRQ context. | |
99 | */ | |
100 | void synchronize_irq(unsigned int irq) | |
101 | { | |
102 | struct irq_desc *desc = irq_to_desc(irq); | |
103 | ||
104 | if (desc) { | |
105 | __synchronize_hardirq(desc); | |
106 | /* | |
107 | * We made sure that no hardirq handler is | |
108 | * running. Now verify that no threaded handlers are | |
109 | * active. | |
110 | */ | |
111 | wait_event(desc->wait_for_threads, | |
112 | !atomic_read(&desc->threads_active)); | |
113 | } | |
1da177e4 | 114 | } |
1da177e4 LT |
115 | EXPORT_SYMBOL(synchronize_irq); |
116 | ||
3aa551c9 TG |
117 | #ifdef CONFIG_SMP |
118 | cpumask_var_t irq_default_affinity; | |
119 | ||
9c255583 | 120 | static bool __irq_can_set_affinity(struct irq_desc *desc) |
e019c249 JL |
121 | { |
122 | if (!desc || !irqd_can_balance(&desc->irq_data) || | |
123 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
9c255583 TG |
124 | return false; |
125 | return true; | |
e019c249 JL |
126 | } |
127 | ||
771ee3b0 TG |
128 | /** |
129 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
130 | * @irq: Interrupt to check | |
131 | * | |
132 | */ | |
133 | int irq_can_set_affinity(unsigned int irq) | |
134 | { | |
e019c249 | 135 | return __irq_can_set_affinity(irq_to_desc(irq)); |
771ee3b0 TG |
136 | } |
137 | ||
9c255583 TG |
138 | /** |
139 | * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space | |
140 | * @irq: Interrupt to check | |
141 | * | |
142 | * Like irq_can_set_affinity() above, but additionally checks for the | |
143 | * AFFINITY_MANAGED flag. | |
144 | */ | |
145 | bool irq_can_set_affinity_usr(unsigned int irq) | |
146 | { | |
147 | struct irq_desc *desc = irq_to_desc(irq); | |
148 | ||
149 | return __irq_can_set_affinity(desc) && | |
150 | !irqd_affinity_is_managed(&desc->irq_data); | |
151 | } | |
152 | ||
591d2fb0 TG |
153 | /** |
154 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
155 | * @desc: irq descriptor which has affitnity changed | |
156 | * | |
157 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
158 | * to the interrupt thread itself. We can not call | |
159 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
160 | * code can be called from hard interrupt context. | |
161 | */ | |
162 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 | 163 | { |
f944b5a7 | 164 | struct irqaction *action; |
3aa551c9 | 165 | |
f944b5a7 | 166 | for_each_action_of_desc(desc, action) |
3aa551c9 | 167 | if (action->thread) |
591d2fb0 | 168 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
169 | } |
170 | ||
19e1d4e9 TG |
171 | static void irq_validate_effective_affinity(struct irq_data *data) |
172 | { | |
173 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK | |
174 | const struct cpumask *m = irq_data_get_effective_affinity_mask(data); | |
175 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
176 | ||
177 | if (!cpumask_empty(m)) | |
178 | return; | |
179 | pr_warn_once("irq_chip %s did not update eff. affinity mask of irq %u\n", | |
180 | chip->name, data->irq); | |
181 | #endif | |
182 | } | |
183 | ||
818b0f3b JL |
184 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
185 | bool force) | |
186 | { | |
187 | struct irq_desc *desc = irq_data_to_desc(data); | |
188 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
189 | int ret; | |
190 | ||
e43b3b58 TG |
191 | if (!chip || !chip->irq_set_affinity) |
192 | return -EINVAL; | |
193 | ||
01f8fa4f | 194 | ret = chip->irq_set_affinity(data, mask, force); |
818b0f3b JL |
195 | switch (ret) { |
196 | case IRQ_SET_MASK_OK: | |
2cb62547 | 197 | case IRQ_SET_MASK_OK_DONE: |
9df872fa | 198 | cpumask_copy(desc->irq_common_data.affinity, mask); |
93417a3f | 199 | /* fall through */ |
818b0f3b | 200 | case IRQ_SET_MASK_OK_NOCOPY: |
19e1d4e9 | 201 | irq_validate_effective_affinity(data); |
818b0f3b JL |
202 | irq_set_thread_affinity(desc); |
203 | ret = 0; | |
204 | } | |
205 | ||
206 | return ret; | |
207 | } | |
208 | ||
12f47073 TG |
209 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
210 | static inline int irq_set_affinity_pending(struct irq_data *data, | |
211 | const struct cpumask *dest) | |
212 | { | |
213 | struct irq_desc *desc = irq_data_to_desc(data); | |
214 | ||
215 | irqd_set_move_pending(data); | |
216 | irq_copy_pending(desc, dest); | |
217 | return 0; | |
218 | } | |
219 | #else | |
220 | static inline int irq_set_affinity_pending(struct irq_data *data, | |
221 | const struct cpumask *dest) | |
222 | { | |
223 | return -EBUSY; | |
224 | } | |
225 | #endif | |
226 | ||
227 | static int irq_try_set_affinity(struct irq_data *data, | |
228 | const struct cpumask *dest, bool force) | |
229 | { | |
230 | int ret = irq_do_set_affinity(data, dest, force); | |
231 | ||
232 | /* | |
233 | * In case that the underlying vector management is busy and the | |
234 | * architecture supports the generic pending mechanism then utilize | |
235 | * this to avoid returning an error to user space. | |
236 | */ | |
237 | if (ret == -EBUSY && !force) | |
238 | ret = irq_set_affinity_pending(data, dest); | |
239 | return ret; | |
240 | } | |
241 | ||
01f8fa4f TG |
242 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
243 | bool force) | |
771ee3b0 | 244 | { |
c2d0c555 DD |
245 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
246 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 247 | int ret = 0; |
771ee3b0 | 248 | |
c2d0c555 | 249 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
250 | return -EINVAL; |
251 | ||
12f47073 TG |
252 | if (irq_can_move_pcntxt(data) && !irqd_is_setaffinity_pending(data)) { |
253 | ret = irq_try_set_affinity(data, mask, force); | |
1fa46f1f | 254 | } else { |
c2d0c555 | 255 | irqd_set_move_pending(data); |
1fa46f1f | 256 | irq_copy_pending(desc, mask); |
57b150cc | 257 | } |
1fa46f1f | 258 | |
cd7eab44 BH |
259 | if (desc->affinity_notify) { |
260 | kref_get(&desc->affinity_notify->kref); | |
261 | schedule_work(&desc->affinity_notify->work); | |
262 | } | |
c2d0c555 DD |
263 | irqd_set(data, IRQD_AFFINITY_SET); |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
01f8fa4f | 268 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
269 | { |
270 | struct irq_desc *desc = irq_to_desc(irq); | |
271 | unsigned long flags; | |
272 | int ret; | |
273 | ||
274 | if (!desc) | |
275 | return -EINVAL; | |
276 | ||
277 | raw_spin_lock_irqsave(&desc->lock, flags); | |
01f8fa4f | 278 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 279 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 280 | return ret; |
771ee3b0 TG |
281 | } |
282 | ||
e7a297b0 PWJ |
283 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
284 | { | |
e7a297b0 | 285 | unsigned long flags; |
31d9d9b6 | 286 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
287 | |
288 | if (!desc) | |
289 | return -EINVAL; | |
e7a297b0 | 290 | desc->affinity_hint = m; |
02725e74 | 291 | irq_put_desc_unlock(desc, flags); |
e2e64a93 | 292 | /* set the initial affinity to prevent every interrupt being on CPU0 */ |
4fe7ffb7 JB |
293 | if (m) |
294 | __irq_set_affinity(irq, m, false); | |
e7a297b0 PWJ |
295 | return 0; |
296 | } | |
297 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
298 | ||
cd7eab44 BH |
299 | static void irq_affinity_notify(struct work_struct *work) |
300 | { | |
301 | struct irq_affinity_notify *notify = | |
302 | container_of(work, struct irq_affinity_notify, work); | |
303 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
304 | cpumask_var_t cpumask; | |
305 | unsigned long flags; | |
306 | ||
1fa46f1f | 307 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
308 | goto out; |
309 | ||
310 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 311 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 312 | irq_get_pending(cpumask, desc); |
cd7eab44 | 313 | else |
9df872fa | 314 | cpumask_copy(cpumask, desc->irq_common_data.affinity); |
cd7eab44 BH |
315 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
316 | ||
317 | notify->notify(notify, cpumask); | |
318 | ||
319 | free_cpumask_var(cpumask); | |
320 | out: | |
321 | kref_put(¬ify->kref, notify->release); | |
322 | } | |
323 | ||
324 | /** | |
325 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
326 | * @irq: Interrupt for which to enable/disable notification | |
327 | * @notify: Context for notification, or %NULL to disable | |
328 | * notification. Function pointers must be initialised; | |
329 | * the other fields will be initialised by this function. | |
330 | * | |
331 | * Must be called in process context. Notification may only be enabled | |
332 | * after the IRQ is allocated and must be disabled before the IRQ is | |
333 | * freed using free_irq(). | |
334 | */ | |
335 | int | |
336 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
337 | { | |
338 | struct irq_desc *desc = irq_to_desc(irq); | |
339 | struct irq_affinity_notify *old_notify; | |
340 | unsigned long flags; | |
341 | ||
342 | /* The release function is promised process context */ | |
343 | might_sleep(); | |
344 | ||
b525903c | 345 | if (!desc || desc->istate & IRQS_NMI) |
cd7eab44 BH |
346 | return -EINVAL; |
347 | ||
348 | /* Complete initialisation of *notify */ | |
349 | if (notify) { | |
350 | notify->irq = irq; | |
351 | kref_init(¬ify->kref); | |
352 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
353 | } | |
354 | ||
355 | raw_spin_lock_irqsave(&desc->lock, flags); | |
356 | old_notify = desc->affinity_notify; | |
357 | desc->affinity_notify = notify; | |
358 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
359 | ||
59c39840 PS |
360 | if (old_notify) { |
361 | cancel_work_sync(&old_notify->work); | |
cd7eab44 | 362 | kref_put(&old_notify->kref, old_notify->release); |
59c39840 | 363 | } |
cd7eab44 BH |
364 | |
365 | return 0; | |
366 | } | |
367 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
368 | ||
18404756 MK |
369 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
370 | /* | |
371 | * Generic version of the affinity autoselector. | |
372 | */ | |
43564bd9 | 373 | int irq_setup_affinity(struct irq_desc *desc) |
18404756 | 374 | { |
569bda8d | 375 | struct cpumask *set = irq_default_affinity; |
cba4235e TG |
376 | int ret, node = irq_desc_get_node(desc); |
377 | static DEFINE_RAW_SPINLOCK(mask_lock); | |
378 | static struct cpumask mask; | |
569bda8d | 379 | |
b008207c | 380 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
e019c249 | 381 | if (!__irq_can_set_affinity(desc)) |
18404756 MK |
382 | return 0; |
383 | ||
cba4235e | 384 | raw_spin_lock(&mask_lock); |
f6d87f4b | 385 | /* |
9332ef9d | 386 | * Preserve the managed affinity setting and a userspace affinity |
06ee6d57 | 387 | * setup, but make sure that one of the targets is online. |
f6d87f4b | 388 | */ |
06ee6d57 TG |
389 | if (irqd_affinity_is_managed(&desc->irq_data) || |
390 | irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { | |
9df872fa | 391 | if (cpumask_intersects(desc->irq_common_data.affinity, |
569bda8d | 392 | cpu_online_mask)) |
9df872fa | 393 | set = desc->irq_common_data.affinity; |
0c6f8a8b | 394 | else |
2bdd1055 | 395 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 396 | } |
18404756 | 397 | |
cba4235e | 398 | cpumask_and(&mask, cpu_online_mask, set); |
bddda606 SR |
399 | if (cpumask_empty(&mask)) |
400 | cpumask_copy(&mask, cpu_online_mask); | |
401 | ||
241fc640 PB |
402 | if (node != NUMA_NO_NODE) { |
403 | const struct cpumask *nodemask = cpumask_of_node(node); | |
404 | ||
405 | /* make sure at least one of the cpus in nodemask is online */ | |
cba4235e TG |
406 | if (cpumask_intersects(&mask, nodemask)) |
407 | cpumask_and(&mask, &mask, nodemask); | |
241fc640 | 408 | } |
cba4235e TG |
409 | ret = irq_do_set_affinity(&desc->irq_data, &mask, false); |
410 | raw_spin_unlock(&mask_lock); | |
411 | return ret; | |
18404756 | 412 | } |
f6d87f4b | 413 | #else |
a8a98eac | 414 | /* Wrapper for ALPHA specific affinity selector magic */ |
cba4235e | 415 | int irq_setup_affinity(struct irq_desc *desc) |
f6d87f4b | 416 | { |
cba4235e | 417 | return irq_select_affinity(irq_desc_get_irq(desc)); |
f6d87f4b | 418 | } |
18404756 MK |
419 | #endif |
420 | ||
f6d87f4b | 421 | /* |
cba4235e | 422 | * Called when a bogus affinity is set via /proc/irq |
f6d87f4b | 423 | */ |
cba4235e | 424 | int irq_select_affinity_usr(unsigned int irq) |
f6d87f4b TG |
425 | { |
426 | struct irq_desc *desc = irq_to_desc(irq); | |
427 | unsigned long flags; | |
428 | int ret; | |
429 | ||
239007b8 | 430 | raw_spin_lock_irqsave(&desc->lock, flags); |
cba4235e | 431 | ret = irq_setup_affinity(desc); |
239007b8 | 432 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
f6d87f4b TG |
433 | return ret; |
434 | } | |
1da177e4 LT |
435 | #endif |
436 | ||
fcf1ae2f FW |
437 | /** |
438 | * irq_set_vcpu_affinity - Set vcpu affinity for the interrupt | |
439 | * @irq: interrupt number to set affinity | |
250a53d6 CD |
440 | * @vcpu_info: vCPU specific data or pointer to a percpu array of vCPU |
441 | * specific data for percpu_devid interrupts | |
fcf1ae2f FW |
442 | * |
443 | * This function uses the vCPU specific data to set the vCPU | |
444 | * affinity for an irq. The vCPU specific data is passed from | |
445 | * outside, such as KVM. One example code path is as below: | |
446 | * KVM -> IOMMU -> irq_set_vcpu_affinity(). | |
447 | */ | |
448 | int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info) | |
449 | { | |
450 | unsigned long flags; | |
451 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
452 | struct irq_data *data; | |
453 | struct irq_chip *chip; | |
454 | int ret = -ENOSYS; | |
455 | ||
456 | if (!desc) | |
457 | return -EINVAL; | |
458 | ||
459 | data = irq_desc_get_irq_data(desc); | |
0abce64a MZ |
460 | do { |
461 | chip = irq_data_get_irq_chip(data); | |
462 | if (chip && chip->irq_set_vcpu_affinity) | |
463 | break; | |
464 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
465 | data = data->parent_data; | |
466 | #else | |
467 | data = NULL; | |
468 | #endif | |
469 | } while (data); | |
470 | ||
471 | if (data) | |
fcf1ae2f FW |
472 | ret = chip->irq_set_vcpu_affinity(data, vcpu_info); |
473 | irq_put_desc_unlock(desc, flags); | |
474 | ||
475 | return ret; | |
476 | } | |
477 | EXPORT_SYMBOL_GPL(irq_set_vcpu_affinity); | |
478 | ||
79ff1cda | 479 | void __disable_irq(struct irq_desc *desc) |
0a0c5168 | 480 | { |
3aae994f | 481 | if (!desc->depth++) |
87923470 | 482 | irq_disable(desc); |
0a0c5168 RW |
483 | } |
484 | ||
02725e74 TG |
485 | static int __disable_irq_nosync(unsigned int irq) |
486 | { | |
487 | unsigned long flags; | |
31d9d9b6 | 488 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
489 | |
490 | if (!desc) | |
491 | return -EINVAL; | |
79ff1cda | 492 | __disable_irq(desc); |
02725e74 TG |
493 | irq_put_desc_busunlock(desc, flags); |
494 | return 0; | |
495 | } | |
496 | ||
1da177e4 LT |
497 | /** |
498 | * disable_irq_nosync - disable an irq without waiting | |
499 | * @irq: Interrupt to disable | |
500 | * | |
501 | * Disable the selected interrupt line. Disables and Enables are | |
502 | * nested. | |
503 | * Unlike disable_irq(), this function does not ensure existing | |
504 | * instances of the IRQ handler have completed before returning. | |
505 | * | |
506 | * This function may be called from IRQ context. | |
507 | */ | |
508 | void disable_irq_nosync(unsigned int irq) | |
509 | { | |
02725e74 | 510 | __disable_irq_nosync(irq); |
1da177e4 | 511 | } |
1da177e4 LT |
512 | EXPORT_SYMBOL(disable_irq_nosync); |
513 | ||
514 | /** | |
515 | * disable_irq - disable an irq and wait for completion | |
516 | * @irq: Interrupt to disable | |
517 | * | |
518 | * Disable the selected interrupt line. Enables and Disables are | |
519 | * nested. | |
520 | * This function waits for any pending IRQ handlers for this interrupt | |
521 | * to complete before returning. If you use this function while | |
522 | * holding a resource the IRQ handler may need you will deadlock. | |
523 | * | |
524 | * This function may be called - with care - from IRQ context. | |
525 | */ | |
526 | void disable_irq(unsigned int irq) | |
527 | { | |
02725e74 | 528 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
529 | synchronize_irq(irq); |
530 | } | |
1da177e4 LT |
531 | EXPORT_SYMBOL(disable_irq); |
532 | ||
02cea395 PZ |
533 | /** |
534 | * disable_hardirq - disables an irq and waits for hardirq completion | |
535 | * @irq: Interrupt to disable | |
536 | * | |
537 | * Disable the selected interrupt line. Enables and Disables are | |
538 | * nested. | |
539 | * This function waits for any pending hard IRQ handlers for this | |
540 | * interrupt to complete before returning. If you use this function while | |
541 | * holding a resource the hard IRQ handler may need you will deadlock. | |
542 | * | |
543 | * When used to optimistically disable an interrupt from atomic context | |
544 | * the return value must be checked. | |
545 | * | |
546 | * Returns: false if a threaded handler is active. | |
547 | * | |
548 | * This function may be called - with care - from IRQ context. | |
549 | */ | |
550 | bool disable_hardirq(unsigned int irq) | |
551 | { | |
552 | if (!__disable_irq_nosync(irq)) | |
553 | return synchronize_hardirq(irq); | |
554 | ||
555 | return false; | |
556 | } | |
557 | EXPORT_SYMBOL_GPL(disable_hardirq); | |
558 | ||
b525903c JT |
559 | /** |
560 | * disable_nmi_nosync - disable an nmi without waiting | |
561 | * @irq: Interrupt to disable | |
562 | * | |
563 | * Disable the selected interrupt line. Disables and enables are | |
564 | * nested. | |
565 | * The interrupt to disable must have been requested through request_nmi. | |
566 | * Unlike disable_nmi(), this function does not ensure existing | |
567 | * instances of the IRQ handler have completed before returning. | |
568 | */ | |
569 | void disable_nmi_nosync(unsigned int irq) | |
570 | { | |
571 | disable_irq_nosync(irq); | |
572 | } | |
573 | ||
79ff1cda | 574 | void __enable_irq(struct irq_desc *desc) |
1adb0850 TG |
575 | { |
576 | switch (desc->depth) { | |
577 | case 0: | |
0a0c5168 | 578 | err_out: |
79ff1cda JL |
579 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", |
580 | irq_desc_get_irq(desc)); | |
1adb0850 TG |
581 | break; |
582 | case 1: { | |
c531e836 | 583 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 584 | goto err_out; |
1adb0850 | 585 | /* Prevent probing on this irq: */ |
1ccb4e61 | 586 | irq_settings_set_noprobe(desc); |
201d7f47 TG |
587 | /* |
588 | * Call irq_startup() not irq_enable() here because the | |
589 | * interrupt might be marked NOAUTOEN. So irq_startup() | |
590 | * needs to be invoked when it gets enabled the first | |
591 | * time. If it was already started up, then irq_startup() | |
592 | * will invoke irq_enable() under the hood. | |
593 | */ | |
c942cee4 | 594 | irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE); |
201d7f47 | 595 | break; |
1adb0850 TG |
596 | } |
597 | default: | |
598 | desc->depth--; | |
599 | } | |
600 | } | |
601 | ||
1da177e4 LT |
602 | /** |
603 | * enable_irq - enable handling of an irq | |
604 | * @irq: Interrupt to enable | |
605 | * | |
606 | * Undoes the effect of one call to disable_irq(). If this | |
607 | * matches the last disable, processing of interrupts on this | |
608 | * IRQ line is re-enabled. | |
609 | * | |
70aedd24 | 610 | * This function may be called from IRQ context only when |
6b8ff312 | 611 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
612 | */ |
613 | void enable_irq(unsigned int irq) | |
614 | { | |
1da177e4 | 615 | unsigned long flags; |
31d9d9b6 | 616 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 617 | |
7d94f7ca | 618 | if (!desc) |
c2b5a251 | 619 | return; |
50f7c032 TG |
620 | if (WARN(!desc->irq_data.chip, |
621 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 622 | goto out; |
2656c366 | 623 | |
79ff1cda | 624 | __enable_irq(desc); |
02725e74 TG |
625 | out: |
626 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 627 | } |
1da177e4 LT |
628 | EXPORT_SYMBOL(enable_irq); |
629 | ||
b525903c JT |
630 | /** |
631 | * enable_nmi - enable handling of an nmi | |
632 | * @irq: Interrupt to enable | |
633 | * | |
634 | * The interrupt to enable must have been requested through request_nmi. | |
635 | * Undoes the effect of one call to disable_nmi(). If this | |
636 | * matches the last disable, processing of interrupts on this | |
637 | * IRQ line is re-enabled. | |
638 | */ | |
639 | void enable_nmi(unsigned int irq) | |
640 | { | |
641 | enable_irq(irq); | |
642 | } | |
643 | ||
0c5d1eb7 | 644 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 645 | { |
08678b08 | 646 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
647 | int ret = -ENXIO; |
648 | ||
60f96b41 SS |
649 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
650 | return 0; | |
651 | ||
2f7e99bb TG |
652 | if (desc->irq_data.chip->irq_set_wake) |
653 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
654 | |
655 | return ret; | |
656 | } | |
657 | ||
ba9a2331 | 658 | /** |
a0cd9ca2 | 659 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
660 | * @irq: interrupt to control |
661 | * @on: enable/disable power management wakeup | |
662 | * | |
15a647eb DB |
663 | * Enable/disable power management wakeup mode, which is |
664 | * disabled by default. Enables and disables must match, | |
665 | * just as they match for non-wakeup mode support. | |
666 | * | |
667 | * Wakeup mode lets this IRQ wake the system from sleep | |
668 | * states like "suspend to RAM". | |
ba9a2331 | 669 | */ |
a0cd9ca2 | 670 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 671 | { |
ba9a2331 | 672 | unsigned long flags; |
31d9d9b6 | 673 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 674 | int ret = 0; |
ba9a2331 | 675 | |
13863a66 JJ |
676 | if (!desc) |
677 | return -EINVAL; | |
678 | ||
b525903c JT |
679 | /* Don't use NMIs as wake up interrupts please */ |
680 | if (desc->istate & IRQS_NMI) { | |
681 | ret = -EINVAL; | |
682 | goto out_unlock; | |
683 | } | |
684 | ||
15a647eb DB |
685 | /* wakeup-capable irqs can be shared between drivers that |
686 | * don't need to have the same sleep mode behaviors. | |
687 | */ | |
15a647eb | 688 | if (on) { |
2db87321 UKK |
689 | if (desc->wake_depth++ == 0) { |
690 | ret = set_irq_wake_real(irq, on); | |
691 | if (ret) | |
692 | desc->wake_depth = 0; | |
693 | else | |
7f94226f | 694 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 695 | } |
15a647eb DB |
696 | } else { |
697 | if (desc->wake_depth == 0) { | |
7a2c4770 | 698 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
699 | } else if (--desc->wake_depth == 0) { |
700 | ret = set_irq_wake_real(irq, on); | |
701 | if (ret) | |
702 | desc->wake_depth = 1; | |
703 | else | |
7f94226f | 704 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 705 | } |
15a647eb | 706 | } |
b525903c JT |
707 | |
708 | out_unlock: | |
02725e74 | 709 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
710 | return ret; |
711 | } | |
a0cd9ca2 | 712 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 713 | |
1da177e4 LT |
714 | /* |
715 | * Internal function that tells the architecture code whether a | |
716 | * particular irq has been exclusively allocated or is available | |
717 | * for driver use. | |
718 | */ | |
719 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
720 | { | |
cc8c3b78 | 721 | unsigned long flags; |
31d9d9b6 | 722 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 723 | int canrequest = 0; |
1da177e4 | 724 | |
7d94f7ca YL |
725 | if (!desc) |
726 | return 0; | |
727 | ||
02725e74 | 728 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
729 | if (!desc->action || |
730 | irqflags & desc->action->flags & IRQF_SHARED) | |
731 | canrequest = 1; | |
02725e74 TG |
732 | } |
733 | irq_put_desc_unlock(desc, flags); | |
734 | return canrequest; | |
1da177e4 LT |
735 | } |
736 | ||
a1ff541a | 737 | int __irq_set_trigger(struct irq_desc *desc, unsigned long flags) |
82736f4d | 738 | { |
6b8ff312 | 739 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 740 | int ret, unmask = 0; |
82736f4d | 741 | |
b2ba2c30 | 742 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
743 | /* |
744 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
745 | * flow-types? | |
746 | */ | |
a1ff541a JL |
747 | pr_debug("No set_type function for IRQ %d (%s)\n", |
748 | irq_desc_get_irq(desc), | |
f5d89470 | 749 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
750 | return 0; |
751 | } | |
752 | ||
d4d5e089 | 753 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { |
32f4125e | 754 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 755 | mask_irq(desc); |
32f4125e | 756 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
757 | unmask = 1; |
758 | } | |
759 | ||
00b992de AK |
760 | /* Mask all flags except trigger mode */ |
761 | flags &= IRQ_TYPE_SENSE_MASK; | |
b2ba2c30 | 762 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 763 | |
876dbd4c TG |
764 | switch (ret) { |
765 | case IRQ_SET_MASK_OK: | |
2cb62547 | 766 | case IRQ_SET_MASK_OK_DONE: |
876dbd4c TG |
767 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); |
768 | irqd_set(&desc->irq_data, flags); | |
44133f7e | 769 | /* fall through */ |
876dbd4c TG |
770 | |
771 | case IRQ_SET_MASK_OK_NOCOPY: | |
772 | flags = irqd_get_trigger_type(&desc->irq_data); | |
773 | irq_settings_set_trigger_mask(desc, flags); | |
774 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
775 | irq_settings_clr_level(desc); | |
776 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
777 | irq_settings_set_level(desc); | |
778 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
779 | } | |
46732475 | 780 | |
d4d5e089 | 781 | ret = 0; |
8fff39e0 | 782 | break; |
876dbd4c | 783 | default: |
d75f773c | 784 | pr_err("Setting trigger mode %lu for irq %u failed (%pS)\n", |
a1ff541a | 785 | flags, irq_desc_get_irq(desc), chip->irq_set_type); |
0c5d1eb7 | 786 | } |
d4d5e089 TG |
787 | if (unmask) |
788 | unmask_irq(desc); | |
82736f4d UKK |
789 | return ret; |
790 | } | |
791 | ||
293a7a0a TG |
792 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
793 | int irq_set_parent(int irq, int parent_irq) | |
794 | { | |
795 | unsigned long flags; | |
796 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
797 | ||
798 | if (!desc) | |
799 | return -EINVAL; | |
800 | ||
801 | desc->parent_irq = parent_irq; | |
802 | ||
803 | irq_put_desc_unlock(desc, flags); | |
804 | return 0; | |
805 | } | |
3118dac5 | 806 | EXPORT_SYMBOL_GPL(irq_set_parent); |
293a7a0a TG |
807 | #endif |
808 | ||
b25c340c TG |
809 | /* |
810 | * Default primary interrupt handler for threaded interrupts. Is | |
811 | * assigned as primary handler when request_threaded_irq is called | |
812 | * with handler == NULL. Useful for oneshot interrupts. | |
813 | */ | |
814 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
815 | { | |
816 | return IRQ_WAKE_THREAD; | |
817 | } | |
818 | ||
399b5da2 TG |
819 | /* |
820 | * Primary handler for nested threaded interrupts. Should never be | |
821 | * called. | |
822 | */ | |
823 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
824 | { | |
825 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
826 | return IRQ_NONE; | |
827 | } | |
828 | ||
2a1d3ab8 TG |
829 | static irqreturn_t irq_forced_secondary_handler(int irq, void *dev_id) |
830 | { | |
831 | WARN(1, "Secondary action handler called for irq %d\n", irq); | |
832 | return IRQ_NONE; | |
833 | } | |
834 | ||
3aa551c9 TG |
835 | static int irq_wait_for_interrupt(struct irqaction *action) |
836 | { | |
519cc865 LW |
837 | for (;;) { |
838 | set_current_state(TASK_INTERRUPTIBLE); | |
550acb19 | 839 | |
519cc865 LW |
840 | if (kthread_should_stop()) { |
841 | /* may need to run one last time */ | |
842 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
843 | &action->thread_flags)) { | |
844 | __set_current_state(TASK_RUNNING); | |
845 | return 0; | |
846 | } | |
847 | __set_current_state(TASK_RUNNING); | |
848 | return -1; | |
849 | } | |
f48fe81e TG |
850 | |
851 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
852 | &action->thread_flags)) { | |
3aa551c9 TG |
853 | __set_current_state(TASK_RUNNING); |
854 | return 0; | |
f48fe81e TG |
855 | } |
856 | schedule(); | |
3aa551c9 | 857 | } |
3aa551c9 TG |
858 | } |
859 | ||
b25c340c TG |
860 | /* |
861 | * Oneshot interrupts keep the irq line masked until the threaded | |
862 | * handler finished. unmask if the interrupt has not been disabled and | |
863 | * is marked MASKED. | |
864 | */ | |
b5faba21 | 865 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 866 | struct irqaction *action) |
b25c340c | 867 | { |
2a1d3ab8 TG |
868 | if (!(desc->istate & IRQS_ONESHOT) || |
869 | action->handler == irq_forced_secondary_handler) | |
b5faba21 | 870 | return; |
0b1adaa0 | 871 | again: |
3876ec9e | 872 | chip_bus_lock(desc); |
239007b8 | 873 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
874 | |
875 | /* | |
876 | * Implausible though it may be we need to protect us against | |
877 | * the following scenario: | |
878 | * | |
879 | * The thread is faster done than the hard interrupt handler | |
880 | * on the other CPU. If we unmask the irq line then the | |
881 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 882 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
883 | * |
884 | * This also serializes the state of shared oneshot handlers | |
885 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
886 | * irq_wake_thread(). See the comment there which explains the | |
887 | * serialization. | |
0b1adaa0 | 888 | */ |
32f4125e | 889 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 890 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 891 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
892 | cpu_relax(); |
893 | goto again; | |
894 | } | |
895 | ||
b5faba21 TG |
896 | /* |
897 | * Now check again, whether the thread should run. Otherwise | |
898 | * we would clear the threads_oneshot bit of this thread which | |
899 | * was just set. | |
900 | */ | |
f3f79e38 | 901 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
902 | goto out_unlock; |
903 | ||
904 | desc->threads_oneshot &= ~action->thread_mask; | |
905 | ||
32f4125e TG |
906 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
907 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 908 | unmask_threaded_irq(desc); |
32f4125e | 909 | |
b5faba21 | 910 | out_unlock: |
239007b8 | 911 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 912 | chip_bus_sync_unlock(desc); |
b25c340c TG |
913 | } |
914 | ||
61f38261 | 915 | #ifdef CONFIG_SMP |
591d2fb0 | 916 | /* |
b04c644e | 917 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
918 | */ |
919 | static void | |
920 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
921 | { | |
922 | cpumask_var_t mask; | |
04aa530e | 923 | bool valid = true; |
591d2fb0 TG |
924 | |
925 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
926 | return; | |
927 | ||
928 | /* | |
929 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
930 | * try again next time | |
931 | */ | |
932 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
933 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
934 | return; | |
935 | } | |
936 | ||
239007b8 | 937 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
938 | /* |
939 | * This code is triggered unconditionally. Check the affinity | |
940 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
941 | */ | |
cbf86999 TG |
942 | if (cpumask_available(desc->irq_common_data.affinity)) { |
943 | const struct cpumask *m; | |
944 | ||
945 | m = irq_data_get_effective_affinity_mask(&desc->irq_data); | |
946 | cpumask_copy(mask, m); | |
947 | } else { | |
04aa530e | 948 | valid = false; |
cbf86999 | 949 | } |
239007b8 | 950 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 951 | |
04aa530e TG |
952 | if (valid) |
953 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
954 | free_cpumask_var(mask); |
955 | } | |
61f38261 BP |
956 | #else |
957 | static inline void | |
958 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
959 | #endif | |
591d2fb0 | 960 | |
8d32a307 | 961 | /* |
c5f48c0a | 962 | * Interrupts which are not explicitly requested as threaded |
8d32a307 TG |
963 | * interrupts rely on the implicit bh/preempt disable of the hard irq |
964 | * context. So we need to disable bh here to avoid deadlocks and other | |
965 | * side effects. | |
966 | */ | |
3a43e05f | 967 | static irqreturn_t |
8d32a307 TG |
968 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
969 | { | |
3a43e05f SAS |
970 | irqreturn_t ret; |
971 | ||
8d32a307 | 972 | local_bh_disable(); |
3a43e05f | 973 | ret = action->thread_fn(action->irq, action->dev_id); |
746a923b LW |
974 | if (ret == IRQ_HANDLED) |
975 | atomic_inc(&desc->threads_handled); | |
976 | ||
f3f79e38 | 977 | irq_finalize_oneshot(desc, action); |
8d32a307 | 978 | local_bh_enable(); |
3a43e05f | 979 | return ret; |
8d32a307 TG |
980 | } |
981 | ||
982 | /* | |
f788e7bf | 983 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
984 | * preemtible - many of them need to sleep and wait for slow busses to |
985 | * complete. | |
986 | */ | |
3a43e05f SAS |
987 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
988 | struct irqaction *action) | |
8d32a307 | 989 | { |
3a43e05f SAS |
990 | irqreturn_t ret; |
991 | ||
992 | ret = action->thread_fn(action->irq, action->dev_id); | |
746a923b LW |
993 | if (ret == IRQ_HANDLED) |
994 | atomic_inc(&desc->threads_handled); | |
995 | ||
f3f79e38 | 996 | irq_finalize_oneshot(desc, action); |
3a43e05f | 997 | return ret; |
8d32a307 TG |
998 | } |
999 | ||
7140ea19 IY |
1000 | static void wake_threads_waitq(struct irq_desc *desc) |
1001 | { | |
c685689f | 1002 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
1003 | wake_up(&desc->wait_for_threads); |
1004 | } | |
1005 | ||
67d12145 | 1006 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
1007 | { |
1008 | struct task_struct *tsk = current; | |
1009 | struct irq_desc *desc; | |
1010 | struct irqaction *action; | |
1011 | ||
1012 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
1013 | return; | |
1014 | ||
1015 | action = kthread_data(tsk); | |
1016 | ||
fb21affa | 1017 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 1018 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
1019 | |
1020 | ||
1021 | desc = irq_to_desc(action->irq); | |
1022 | /* | |
1023 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
1024 | * desc->threads_active and wake possible waiters. | |
1025 | */ | |
1026 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
1027 | wake_threads_waitq(desc); | |
1028 | ||
1029 | /* Prevent a stale desc->threads_oneshot */ | |
1030 | irq_finalize_oneshot(desc, action); | |
1031 | } | |
1032 | ||
2a1d3ab8 TG |
1033 | static void irq_wake_secondary(struct irq_desc *desc, struct irqaction *action) |
1034 | { | |
1035 | struct irqaction *secondary = action->secondary; | |
1036 | ||
1037 | if (WARN_ON_ONCE(!secondary)) | |
1038 | return; | |
1039 | ||
1040 | raw_spin_lock_irq(&desc->lock); | |
1041 | __irq_wake_thread(desc, secondary); | |
1042 | raw_spin_unlock_irq(&desc->lock); | |
1043 | } | |
1044 | ||
3aa551c9 TG |
1045 | /* |
1046 | * Interrupt handler thread | |
1047 | */ | |
1048 | static int irq_thread(void *data) | |
1049 | { | |
67d12145 | 1050 | struct callback_head on_exit_work; |
3aa551c9 TG |
1051 | struct irqaction *action = data; |
1052 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
1053 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
1054 | struct irqaction *action); | |
3aa551c9 | 1055 | |
540b60e2 | 1056 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
1057 | &action->thread_flags)) |
1058 | handler_fn = irq_forced_thread_fn; | |
1059 | else | |
1060 | handler_fn = irq_thread_fn; | |
1061 | ||
41f9d29f | 1062 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 1063 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 1064 | |
f3de44ed SM |
1065 | irq_thread_check_affinity(desc, action); |
1066 | ||
3aa551c9 | 1067 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 1068 | irqreturn_t action_ret; |
3aa551c9 | 1069 | |
591d2fb0 TG |
1070 | irq_thread_check_affinity(desc, action); |
1071 | ||
7140ea19 | 1072 | action_ret = handler_fn(desc, action); |
2a1d3ab8 TG |
1073 | if (action_ret == IRQ_WAKE_THREAD) |
1074 | irq_wake_secondary(desc, action); | |
3aa551c9 | 1075 | |
7140ea19 | 1076 | wake_threads_waitq(desc); |
3aa551c9 TG |
1077 | } |
1078 | ||
7140ea19 IY |
1079 | /* |
1080 | * This is the regular exit path. __free_irq() is stopping the | |
1081 | * thread via kthread_stop() after calling | |
519cc865 | 1082 | * synchronize_hardirq(). So neither IRQTF_RUNTHREAD nor the |
836557bd | 1083 | * oneshot mask bit can be set. |
3aa551c9 | 1084 | */ |
4d1d61a6 | 1085 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
1086 | return 0; |
1087 | } | |
1088 | ||
a92444c6 TG |
1089 | /** |
1090 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
1091 | * @irq: Interrupt line | |
1092 | * @dev_id: Device identity for which the thread should be woken | |
1093 | * | |
1094 | */ | |
1095 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
1096 | { | |
1097 | struct irq_desc *desc = irq_to_desc(irq); | |
1098 | struct irqaction *action; | |
1099 | unsigned long flags; | |
1100 | ||
1101 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1102 | return; | |
1103 | ||
1104 | raw_spin_lock_irqsave(&desc->lock, flags); | |
f944b5a7 | 1105 | for_each_action_of_desc(desc, action) { |
a92444c6 TG |
1106 | if (action->dev_id == dev_id) { |
1107 | if (action->thread) | |
1108 | __irq_wake_thread(desc, action); | |
1109 | break; | |
1110 | } | |
1111 | } | |
1112 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1113 | } | |
1114 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
1115 | ||
2a1d3ab8 | 1116 | static int irq_setup_forced_threading(struct irqaction *new) |
8d32a307 TG |
1117 | { |
1118 | if (!force_irqthreads) | |
2a1d3ab8 | 1119 | return 0; |
8d32a307 | 1120 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) |
2a1d3ab8 | 1121 | return 0; |
8d32a307 | 1122 | |
d1f0301b TG |
1123 | /* |
1124 | * No further action required for interrupts which are requested as | |
1125 | * threaded interrupts already | |
1126 | */ | |
1127 | if (new->handler == irq_default_primary_handler) | |
1128 | return 0; | |
1129 | ||
8d32a307 TG |
1130 | new->flags |= IRQF_ONESHOT; |
1131 | ||
2a1d3ab8 TG |
1132 | /* |
1133 | * Handle the case where we have a real primary handler and a | |
1134 | * thread handler. We force thread them as well by creating a | |
1135 | * secondary action. | |
1136 | */ | |
d1f0301b | 1137 | if (new->handler && new->thread_fn) { |
2a1d3ab8 TG |
1138 | /* Allocate the secondary action */ |
1139 | new->secondary = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1140 | if (!new->secondary) | |
1141 | return -ENOMEM; | |
1142 | new->secondary->handler = irq_forced_secondary_handler; | |
1143 | new->secondary->thread_fn = new->thread_fn; | |
1144 | new->secondary->dev_id = new->dev_id; | |
1145 | new->secondary->irq = new->irq; | |
1146 | new->secondary->name = new->name; | |
8d32a307 | 1147 | } |
2a1d3ab8 TG |
1148 | /* Deal with the primary handler */ |
1149 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
1150 | new->thread_fn = new->handler; | |
1151 | new->handler = irq_default_primary_handler; | |
1152 | return 0; | |
8d32a307 TG |
1153 | } |
1154 | ||
c1bacbae TG |
1155 | static int irq_request_resources(struct irq_desc *desc) |
1156 | { | |
1157 | struct irq_data *d = &desc->irq_data; | |
1158 | struct irq_chip *c = d->chip; | |
1159 | ||
1160 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
1161 | } | |
1162 | ||
1163 | static void irq_release_resources(struct irq_desc *desc) | |
1164 | { | |
1165 | struct irq_data *d = &desc->irq_data; | |
1166 | struct irq_chip *c = d->chip; | |
1167 | ||
1168 | if (c->irq_release_resources) | |
1169 | c->irq_release_resources(d); | |
1170 | } | |
1171 | ||
b525903c JT |
1172 | static bool irq_supports_nmi(struct irq_desc *desc) |
1173 | { | |
1174 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1175 | ||
1176 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1177 | /* Only IRQs directly managed by the root irqchip can be set as NMI */ | |
1178 | if (d->parent_data) | |
1179 | return false; | |
1180 | #endif | |
1181 | /* Don't support NMIs for chips behind a slow bus */ | |
1182 | if (d->chip->irq_bus_lock || d->chip->irq_bus_sync_unlock) | |
1183 | return false; | |
1184 | ||
1185 | return d->chip->flags & IRQCHIP_SUPPORTS_NMI; | |
1186 | } | |
1187 | ||
1188 | static int irq_nmi_setup(struct irq_desc *desc) | |
1189 | { | |
1190 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1191 | struct irq_chip *c = d->chip; | |
1192 | ||
1193 | return c->irq_nmi_setup ? c->irq_nmi_setup(d) : -EINVAL; | |
1194 | } | |
1195 | ||
1196 | static void irq_nmi_teardown(struct irq_desc *desc) | |
1197 | { | |
1198 | struct irq_data *d = irq_desc_get_irq_data(desc); | |
1199 | struct irq_chip *c = d->chip; | |
1200 | ||
1201 | if (c->irq_nmi_teardown) | |
1202 | c->irq_nmi_teardown(d); | |
1203 | } | |
1204 | ||
2a1d3ab8 TG |
1205 | static int |
1206 | setup_irq_thread(struct irqaction *new, unsigned int irq, bool secondary) | |
1207 | { | |
1208 | struct task_struct *t; | |
1209 | struct sched_param param = { | |
1210 | .sched_priority = MAX_USER_RT_PRIO/2, | |
1211 | }; | |
1212 | ||
1213 | if (!secondary) { | |
1214 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1215 | new->name); | |
1216 | } else { | |
1217 | t = kthread_create(irq_thread, new, "irq/%d-s-%s", irq, | |
1218 | new->name); | |
1219 | param.sched_priority -= 1; | |
1220 | } | |
1221 | ||
1222 | if (IS_ERR(t)) | |
1223 | return PTR_ERR(t); | |
1224 | ||
1225 | sched_setscheduler_nocheck(t, SCHED_FIFO, ¶m); | |
1226 | ||
1227 | /* | |
1228 | * We keep the reference to the task struct even if | |
1229 | * the thread dies to avoid that the interrupt code | |
1230 | * references an already freed task_struct. | |
1231 | */ | |
1232 | get_task_struct(t); | |
1233 | new->thread = t; | |
1234 | /* | |
1235 | * Tell the thread to set its affinity. This is | |
1236 | * important for shared interrupt handlers as we do | |
1237 | * not invoke setup_affinity() for the secondary | |
1238 | * handlers as everything is already set up. Even for | |
1239 | * interrupts marked with IRQF_NO_BALANCE this is | |
1240 | * correct as we want the thread to move to the cpu(s) | |
1241 | * on which the requesting code placed the interrupt. | |
1242 | */ | |
1243 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
1244 | return 0; | |
1245 | } | |
1246 | ||
1da177e4 LT |
1247 | /* |
1248 | * Internal function to register an irqaction - typically used to | |
1249 | * allocate special interrupts that are part of the architecture. | |
19d39a38 TG |
1250 | * |
1251 | * Locking rules: | |
1252 | * | |
1253 | * desc->request_mutex Provides serialization against a concurrent free_irq() | |
1254 | * chip_bus_lock Provides serialization for slow bus operations | |
1255 | * desc->lock Provides serialization against hard interrupts | |
1256 | * | |
1257 | * chip_bus_lock and desc->lock are sufficient for all other management and | |
1258 | * interrupt related functions. desc->request_mutex solely serializes | |
1259 | * request/free_irq(). | |
1da177e4 | 1260 | */ |
d3c60047 | 1261 | static int |
327ec569 | 1262 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 1263 | { |
f17c7545 | 1264 | struct irqaction *old, **old_ptr; |
b5faba21 | 1265 | unsigned long flags, thread_mask = 0; |
3b8249e7 | 1266 | int ret, nested, shared = 0; |
1da177e4 | 1267 | |
7d94f7ca | 1268 | if (!desc) |
c2b5a251 MW |
1269 | return -EINVAL; |
1270 | ||
6b8ff312 | 1271 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 1272 | return -ENOSYS; |
b6873807 SAS |
1273 | if (!try_module_get(desc->owner)) |
1274 | return -ENODEV; | |
1da177e4 | 1275 | |
2a1d3ab8 TG |
1276 | new->irq = irq; |
1277 | ||
4b357dae JH |
1278 | /* |
1279 | * If the trigger type is not specified by the caller, | |
1280 | * then use the default for this interrupt. | |
1281 | */ | |
1282 | if (!(new->flags & IRQF_TRIGGER_MASK)) | |
1283 | new->flags |= irqd_get_trigger_type(&desc->irq_data); | |
1284 | ||
3aa551c9 | 1285 | /* |
399b5da2 TG |
1286 | * Check whether the interrupt nests into another interrupt |
1287 | * thread. | |
1288 | */ | |
1ccb4e61 | 1289 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 1290 | if (nested) { |
b6873807 SAS |
1291 | if (!new->thread_fn) { |
1292 | ret = -EINVAL; | |
1293 | goto out_mput; | |
1294 | } | |
399b5da2 TG |
1295 | /* |
1296 | * Replace the primary handler which was provided from | |
1297 | * the driver for non nested interrupt handling by the | |
1298 | * dummy function which warns when called. | |
1299 | */ | |
1300 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 1301 | } else { |
2a1d3ab8 TG |
1302 | if (irq_settings_can_thread(desc)) { |
1303 | ret = irq_setup_forced_threading(new); | |
1304 | if (ret) | |
1305 | goto out_mput; | |
1306 | } | |
399b5da2 TG |
1307 | } |
1308 | ||
3aa551c9 | 1309 | /* |
399b5da2 TG |
1310 | * Create a handler thread when a thread function is supplied |
1311 | * and the interrupt does not nest into another interrupt | |
1312 | * thread. | |
3aa551c9 | 1313 | */ |
399b5da2 | 1314 | if (new->thread_fn && !nested) { |
2a1d3ab8 TG |
1315 | ret = setup_irq_thread(new, irq, false); |
1316 | if (ret) | |
b6873807 | 1317 | goto out_mput; |
2a1d3ab8 TG |
1318 | if (new->secondary) { |
1319 | ret = setup_irq_thread(new->secondary, irq, true); | |
1320 | if (ret) | |
1321 | goto out_thread; | |
b6873807 | 1322 | } |
3aa551c9 TG |
1323 | } |
1324 | ||
dc9b229a TG |
1325 | /* |
1326 | * Drivers are often written to work w/o knowledge about the | |
1327 | * underlying irq chip implementation, so a request for a | |
1328 | * threaded irq without a primary hard irq context handler | |
1329 | * requires the ONESHOT flag to be set. Some irq chips like | |
1330 | * MSI based interrupts are per se one shot safe. Check the | |
1331 | * chip flags, so we can avoid the unmask dance at the end of | |
1332 | * the threaded handler for those. | |
1333 | */ | |
1334 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1335 | new->flags &= ~IRQF_ONESHOT; | |
1336 | ||
19d39a38 TG |
1337 | /* |
1338 | * Protects against a concurrent __free_irq() call which might wait | |
519cc865 | 1339 | * for synchronize_hardirq() to complete without holding the optional |
836557bd LW |
1340 | * chip bus lock and desc->lock. Also protects against handing out |
1341 | * a recycled oneshot thread_mask bit while it's still in use by | |
1342 | * its previous owner. | |
19d39a38 | 1343 | */ |
9114014c | 1344 | mutex_lock(&desc->request_mutex); |
19d39a38 TG |
1345 | |
1346 | /* | |
1347 | * Acquire bus lock as the irq_request_resources() callback below | |
1348 | * might rely on the serialization or the magic power management | |
1349 | * functions which are abusing the irq_bus_lock() callback, | |
1350 | */ | |
1351 | chip_bus_lock(desc); | |
1352 | ||
1353 | /* First installed action requests resources. */ | |
46e48e25 TG |
1354 | if (!desc->action) { |
1355 | ret = irq_request_resources(desc); | |
1356 | if (ret) { | |
1357 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1358 | new->name, irq, desc->irq_data.chip->name); | |
19d39a38 | 1359 | goto out_bus_unlock; |
46e48e25 TG |
1360 | } |
1361 | } | |
9114014c | 1362 | |
1da177e4 LT |
1363 | /* |
1364 | * The following block of code has to be executed atomically | |
19d39a38 TG |
1365 | * protected against a concurrent interrupt and any of the other |
1366 | * management calls which are not serialized via | |
1367 | * desc->request_mutex or the optional bus lock. | |
1da177e4 | 1368 | */ |
239007b8 | 1369 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1370 | old_ptr = &desc->action; |
1371 | old = *old_ptr; | |
06fcb0c6 | 1372 | if (old) { |
e76de9f8 TG |
1373 | /* |
1374 | * Can't share interrupts unless both agree to and are | |
1375 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1376 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1377 | * set the trigger type must match. Also all must |
1378 | * agree on ONESHOT. | |
b525903c | 1379 | * Interrupt lines used for NMIs cannot be shared. |
e76de9f8 | 1380 | */ |
4f8413a3 MZ |
1381 | unsigned int oldtype; |
1382 | ||
b525903c JT |
1383 | if (desc->istate & IRQS_NMI) { |
1384 | pr_err("Invalid attempt to share NMI for %s (irq %d) on irqchip %s.\n", | |
1385 | new->name, irq, desc->irq_data.chip->name); | |
1386 | ret = -EINVAL; | |
1387 | goto out_unlock; | |
1388 | } | |
1389 | ||
4f8413a3 MZ |
1390 | /* |
1391 | * If nobody did set the configuration before, inherit | |
1392 | * the one provided by the requester. | |
1393 | */ | |
1394 | if (irqd_trigger_type_was_set(&desc->irq_data)) { | |
1395 | oldtype = irqd_get_trigger_type(&desc->irq_data); | |
1396 | } else { | |
1397 | oldtype = new->flags & IRQF_TRIGGER_MASK; | |
1398 | irqd_set_trigger_type(&desc->irq_data, oldtype); | |
1399 | } | |
382bd4de | 1400 | |
3cca53b0 | 1401 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
382bd4de | 1402 | (oldtype != (new->flags & IRQF_TRIGGER_MASK)) || |
f5d89470 | 1403 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1404 | goto mismatch; |
1405 | ||
f5163427 | 1406 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1407 | if ((old->flags & IRQF_PERCPU) != |
1408 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1409 | goto mismatch; |
1da177e4 LT |
1410 | |
1411 | /* add new interrupt at end of irq queue */ | |
1412 | do { | |
52abb700 TG |
1413 | /* |
1414 | * Or all existing action->thread_mask bits, | |
1415 | * so we can find the next zero bit for this | |
1416 | * new action. | |
1417 | */ | |
b5faba21 | 1418 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1419 | old_ptr = &old->next; |
1420 | old = *old_ptr; | |
1da177e4 LT |
1421 | } while (old); |
1422 | shared = 1; | |
1423 | } | |
1424 | ||
b5faba21 | 1425 | /* |
52abb700 TG |
1426 | * Setup the thread mask for this irqaction for ONESHOT. For |
1427 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1428 | * conditional in irq_wake_thread(). | |
b5faba21 | 1429 | */ |
52abb700 TG |
1430 | if (new->flags & IRQF_ONESHOT) { |
1431 | /* | |
1432 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1433 | * but who knows. | |
1434 | */ | |
1435 | if (thread_mask == ~0UL) { | |
1436 | ret = -EBUSY; | |
cba4235e | 1437 | goto out_unlock; |
52abb700 TG |
1438 | } |
1439 | /* | |
1440 | * The thread_mask for the action is or'ed to | |
1441 | * desc->thread_active to indicate that the | |
1442 | * IRQF_ONESHOT thread handler has been woken, but not | |
1443 | * yet finished. The bit is cleared when a thread | |
1444 | * completes. When all threads of a shared interrupt | |
1445 | * line have completed desc->threads_active becomes | |
1446 | * zero and the interrupt line is unmasked. See | |
1447 | * handle.c:irq_wake_thread() for further information. | |
1448 | * | |
1449 | * If no thread is woken by primary (hard irq context) | |
1450 | * interrupt handlers, then desc->threads_active is | |
1451 | * also checked for zero to unmask the irq line in the | |
1452 | * affected hard irq flow handlers | |
1453 | * (handle_[fasteoi|level]_irq). | |
1454 | * | |
1455 | * The new action gets the first zero bit of | |
1456 | * thread_mask assigned. See the loop above which or's | |
1457 | * all existing action->thread_mask bits. | |
1458 | */ | |
ffc661c9 | 1459 | new->thread_mask = 1UL << ffz(thread_mask); |
1c6c6952 | 1460 | |
dc9b229a TG |
1461 | } else if (new->handler == irq_default_primary_handler && |
1462 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1463 | /* |
1464 | * The interrupt was requested with handler = NULL, so | |
1465 | * we use the default primary handler for it. But it | |
1466 | * does not have the oneshot flag set. In combination | |
1467 | * with level interrupts this is deadly, because the | |
1468 | * default primary handler just wakes the thread, then | |
1469 | * the irq lines is reenabled, but the device still | |
1470 | * has the level irq asserted. Rinse and repeat.... | |
1471 | * | |
1472 | * While this works for edge type interrupts, we play | |
1473 | * it safe and reject unconditionally because we can't | |
1474 | * say for sure which type this interrupt really | |
1475 | * has. The type flags are unreliable as the | |
1476 | * underlying chip implementation can override them. | |
1477 | */ | |
97fd75b7 | 1478 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for irq %d\n", |
1c6c6952 TG |
1479 | irq); |
1480 | ret = -EINVAL; | |
cba4235e | 1481 | goto out_unlock; |
b5faba21 | 1482 | } |
b5faba21 | 1483 | |
1da177e4 | 1484 | if (!shared) { |
3aa551c9 TG |
1485 | init_waitqueue_head(&desc->wait_for_threads); |
1486 | ||
e76de9f8 | 1487 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1488 | if (new->flags & IRQF_TRIGGER_MASK) { |
a1ff541a JL |
1489 | ret = __irq_set_trigger(desc, |
1490 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1491 | |
19d39a38 | 1492 | if (ret) |
cba4235e | 1493 | goto out_unlock; |
091738a2 | 1494 | } |
6a6de9ef | 1495 | |
c942cee4 TG |
1496 | /* |
1497 | * Activate the interrupt. That activation must happen | |
1498 | * independently of IRQ_NOAUTOEN. request_irq() can fail | |
1499 | * and the callers are supposed to handle | |
1500 | * that. enable_irq() of an interrupt requested with | |
1501 | * IRQ_NOAUTOEN is not supposed to fail. The activation | |
1502 | * keeps it in shutdown mode, it merily associates | |
1503 | * resources if necessary and if that's not possible it | |
1504 | * fails. Interrupts which are in managed shutdown mode | |
1505 | * will simply ignore that activation request. | |
1506 | */ | |
1507 | ret = irq_activate(desc); | |
1508 | if (ret) | |
1509 | goto out_unlock; | |
1510 | ||
009b4c3b | 1511 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1512 | IRQS_ONESHOT | IRQS_WAITING); |
1513 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1514 | |
a005677b TG |
1515 | if (new->flags & IRQF_PERCPU) { |
1516 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1517 | irq_settings_set_per_cpu(desc); | |
1518 | } | |
6a58fb3b | 1519 | |
b25c340c | 1520 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1521 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1522 | |
2e051552 TG |
1523 | /* Exclude IRQ from balancing if requested */ |
1524 | if (new->flags & IRQF_NOBALANCING) { | |
1525 | irq_settings_set_no_balancing(desc); | |
1526 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1527 | } | |
1528 | ||
04c848d3 | 1529 | if (irq_settings_can_autoenable(desc)) { |
4cde9c6b | 1530 | irq_startup(desc, IRQ_RESEND, IRQ_START_COND); |
04c848d3 TG |
1531 | } else { |
1532 | /* | |
1533 | * Shared interrupts do not go well with disabling | |
1534 | * auto enable. The sharing interrupt might request | |
1535 | * it while it's still disabled and then wait for | |
1536 | * interrupts forever. | |
1537 | */ | |
1538 | WARN_ON_ONCE(new->flags & IRQF_SHARED); | |
e76de9f8 TG |
1539 | /* Undo nested disables: */ |
1540 | desc->depth = 1; | |
04c848d3 | 1541 | } |
18404756 | 1542 | |
876dbd4c TG |
1543 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1544 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
7ee7e87d | 1545 | unsigned int omsk = irqd_get_trigger_type(&desc->irq_data); |
876dbd4c TG |
1546 | |
1547 | if (nmsk != omsk) | |
1548 | /* hope the handler works with current trigger mode */ | |
a395d6a7 | 1549 | pr_warn("irq %d uses trigger mode %u; requested %u\n", |
7ee7e87d | 1550 | irq, omsk, nmsk); |
1da177e4 | 1551 | } |
82736f4d | 1552 | |
f17c7545 | 1553 | *old_ptr = new; |
82736f4d | 1554 | |
cab303be TG |
1555 | irq_pm_install_action(desc, new); |
1556 | ||
8528b0f1 LT |
1557 | /* Reset broken irq detection when installing new handler */ |
1558 | desc->irq_count = 0; | |
1559 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1560 | |
1561 | /* | |
1562 | * Check whether we disabled the irq via the spurious handler | |
1563 | * before. Reenable it and give it another chance. | |
1564 | */ | |
7acdd53e TG |
1565 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1566 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
79ff1cda | 1567 | __enable_irq(desc); |
1adb0850 TG |
1568 | } |
1569 | ||
239007b8 | 1570 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a90795e | 1571 | chip_bus_sync_unlock(desc); |
9114014c | 1572 | mutex_unlock(&desc->request_mutex); |
1da177e4 | 1573 | |
b2d3d61a DL |
1574 | irq_setup_timings(desc, new); |
1575 | ||
69ab8494 TG |
1576 | /* |
1577 | * Strictly no need to wake it up, but hung_task complains | |
1578 | * when no hard interrupt wakes the thread up. | |
1579 | */ | |
1580 | if (new->thread) | |
1581 | wake_up_process(new->thread); | |
2a1d3ab8 TG |
1582 | if (new->secondary) |
1583 | wake_up_process(new->secondary->thread); | |
69ab8494 | 1584 | |
2c6927a3 | 1585 | register_irq_proc(irq, desc); |
1da177e4 LT |
1586 | new->dir = NULL; |
1587 | register_handler_proc(irq, new); | |
1da177e4 | 1588 | return 0; |
f5163427 DS |
1589 | |
1590 | mismatch: | |
3cca53b0 | 1591 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1592 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1593 | irq, new->flags, new->name, old->flags, old->name); |
1594 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1595 | dump_stack(); |
3f050447 | 1596 | #endif |
f5d89470 | 1597 | } |
3aa551c9 TG |
1598 | ret = -EBUSY; |
1599 | ||
cba4235e | 1600 | out_unlock: |
1c389795 | 1601 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 | 1602 | |
46e48e25 TG |
1603 | if (!desc->action) |
1604 | irq_release_resources(desc); | |
19d39a38 TG |
1605 | out_bus_unlock: |
1606 | chip_bus_sync_unlock(desc); | |
9114014c TG |
1607 | mutex_unlock(&desc->request_mutex); |
1608 | ||
3aa551c9 | 1609 | out_thread: |
3aa551c9 TG |
1610 | if (new->thread) { |
1611 | struct task_struct *t = new->thread; | |
1612 | ||
1613 | new->thread = NULL; | |
05d74efa | 1614 | kthread_stop(t); |
3aa551c9 TG |
1615 | put_task_struct(t); |
1616 | } | |
2a1d3ab8 TG |
1617 | if (new->secondary && new->secondary->thread) { |
1618 | struct task_struct *t = new->secondary->thread; | |
1619 | ||
1620 | new->secondary->thread = NULL; | |
1621 | kthread_stop(t); | |
1622 | put_task_struct(t); | |
1623 | } | |
b6873807 SAS |
1624 | out_mput: |
1625 | module_put(desc->owner); | |
3aa551c9 | 1626 | return ret; |
1da177e4 LT |
1627 | } |
1628 | ||
d3c60047 TG |
1629 | /** |
1630 | * setup_irq - setup an interrupt | |
1631 | * @irq: Interrupt line to setup | |
1632 | * @act: irqaction for the interrupt | |
1633 | * | |
1634 | * Used to statically setup interrupts in the early boot process. | |
1635 | */ | |
1636 | int setup_irq(unsigned int irq, struct irqaction *act) | |
1637 | { | |
986c011d | 1638 | int retval; |
d3c60047 TG |
1639 | struct irq_desc *desc = irq_to_desc(irq); |
1640 | ||
9b5d585d | 1641 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
31d9d9b6 | 1642 | return -EINVAL; |
be45beb2 JH |
1643 | |
1644 | retval = irq_chip_pm_get(&desc->irq_data); | |
1645 | if (retval < 0) | |
1646 | return retval; | |
1647 | ||
986c011d | 1648 | retval = __setup_irq(irq, desc, act); |
986c011d | 1649 | |
be45beb2 JH |
1650 | if (retval) |
1651 | irq_chip_pm_put(&desc->irq_data); | |
1652 | ||
986c011d | 1653 | return retval; |
d3c60047 | 1654 | } |
eb53b4e8 | 1655 | EXPORT_SYMBOL_GPL(setup_irq); |
d3c60047 | 1656 | |
31d9d9b6 | 1657 | /* |
cbf94f06 MD |
1658 | * Internal function to unregister an irqaction - used to free |
1659 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1660 | */ |
83ac4ca9 | 1661 | static struct irqaction *__free_irq(struct irq_desc *desc, void *dev_id) |
1da177e4 | 1662 | { |
83ac4ca9 | 1663 | unsigned irq = desc->irq_data.irq; |
f17c7545 | 1664 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1665 | unsigned long flags; |
1666 | ||
ae88a23b | 1667 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1668 | |
9114014c | 1669 | mutex_lock(&desc->request_mutex); |
abc7e40c | 1670 | chip_bus_lock(desc); |
239007b8 | 1671 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1672 | |
1673 | /* | |
1674 | * There can be multiple actions per IRQ descriptor, find the right | |
1675 | * one based on the dev_id: | |
1676 | */ | |
f17c7545 | 1677 | action_ptr = &desc->action; |
1da177e4 | 1678 | for (;;) { |
f17c7545 | 1679 | action = *action_ptr; |
1da177e4 | 1680 | |
ae88a23b IM |
1681 | if (!action) { |
1682 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1683 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
abc7e40c | 1684 | chip_bus_sync_unlock(desc); |
19d39a38 | 1685 | mutex_unlock(&desc->request_mutex); |
f21cfb25 | 1686 | return NULL; |
ae88a23b | 1687 | } |
1da177e4 | 1688 | |
8316e381 IM |
1689 | if (action->dev_id == dev_id) |
1690 | break; | |
f17c7545 | 1691 | action_ptr = &action->next; |
ae88a23b | 1692 | } |
dbce706e | 1693 | |
ae88a23b | 1694 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1695 | *action_ptr = action->next; |
ae88a23b | 1696 | |
cab303be TG |
1697 | irq_pm_remove_action(desc, action); |
1698 | ||
ae88a23b | 1699 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1700 | if (!desc->action) { |
e9849777 | 1701 | irq_settings_clr_disable_unlazy(desc); |
46999238 | 1702 | irq_shutdown(desc); |
c1bacbae | 1703 | } |
3aa551c9 | 1704 | |
e7a297b0 PWJ |
1705 | #ifdef CONFIG_SMP |
1706 | /* make sure affinity_hint is cleaned up */ | |
1707 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1708 | desc->affinity_hint = NULL; | |
1709 | #endif | |
1710 | ||
239007b8 | 1711 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
19d39a38 TG |
1712 | /* |
1713 | * Drop bus_lock here so the changes which were done in the chip | |
1714 | * callbacks above are synced out to the irq chips which hang | |
519cc865 | 1715 | * behind a slow bus (I2C, SPI) before calling synchronize_hardirq(). |
19d39a38 TG |
1716 | * |
1717 | * Aside of that the bus_lock can also be taken from the threaded | |
1718 | * handler in irq_finalize_oneshot() which results in a deadlock | |
519cc865 | 1719 | * because kthread_stop() would wait forever for the thread to |
19d39a38 TG |
1720 | * complete, which is blocked on the bus lock. |
1721 | * | |
1722 | * The still held desc->request_mutex() protects against a | |
1723 | * concurrent request_irq() of this irq so the release of resources | |
1724 | * and timing data is properly serialized. | |
1725 | */ | |
abc7e40c | 1726 | chip_bus_sync_unlock(desc); |
ae88a23b IM |
1727 | |
1728 | unregister_handler_proc(irq, action); | |
1729 | ||
1730 | /* Make sure it's not being used on another CPU: */ | |
519cc865 | 1731 | synchronize_hardirq(irq); |
1da177e4 | 1732 | |
70edcd77 | 1733 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1734 | /* |
1735 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1736 | * event to happen even now it's being freed, so let's make sure that | |
1737 | * is so by doing an extra call to the handler .... | |
1738 | * | |
1739 | * ( We do this after actually deregistering it, to make sure that a | |
0a13ec0b | 1740 | * 'real' IRQ doesn't run in parallel with our fake. ) |
ae88a23b IM |
1741 | */ |
1742 | if (action->flags & IRQF_SHARED) { | |
1743 | local_irq_save(flags); | |
1744 | action->handler(irq, dev_id); | |
1745 | local_irq_restore(flags); | |
1da177e4 | 1746 | } |
ae88a23b | 1747 | #endif |
2d860ad7 | 1748 | |
519cc865 LW |
1749 | /* |
1750 | * The action has already been removed above, but the thread writes | |
1751 | * its oneshot mask bit when it completes. Though request_mutex is | |
1752 | * held across this which prevents __setup_irq() from handing out | |
1753 | * the same bit to a newly requested action. | |
1754 | */ | |
2d860ad7 | 1755 | if (action->thread) { |
05d74efa | 1756 | kthread_stop(action->thread); |
2d860ad7 | 1757 | put_task_struct(action->thread); |
2a1d3ab8 TG |
1758 | if (action->secondary && action->secondary->thread) { |
1759 | kthread_stop(action->secondary->thread); | |
1760 | put_task_struct(action->secondary->thread); | |
1761 | } | |
2d860ad7 LT |
1762 | } |
1763 | ||
19d39a38 | 1764 | /* Last action releases resources */ |
2343877f | 1765 | if (!desc->action) { |
19d39a38 TG |
1766 | /* |
1767 | * Reaquire bus lock as irq_release_resources() might | |
1768 | * require it to deallocate resources over the slow bus. | |
1769 | */ | |
1770 | chip_bus_lock(desc); | |
46e48e25 | 1771 | irq_release_resources(desc); |
19d39a38 | 1772 | chip_bus_sync_unlock(desc); |
2343877f TG |
1773 | irq_remove_timings(desc); |
1774 | } | |
46e48e25 | 1775 | |
9114014c TG |
1776 | mutex_unlock(&desc->request_mutex); |
1777 | ||
be45beb2 | 1778 | irq_chip_pm_put(&desc->irq_data); |
b6873807 | 1779 | module_put(desc->owner); |
2a1d3ab8 | 1780 | kfree(action->secondary); |
f21cfb25 MD |
1781 | return action; |
1782 | } | |
1783 | ||
cbf94f06 MD |
1784 | /** |
1785 | * remove_irq - free an interrupt | |
1786 | * @irq: Interrupt line to free | |
1787 | * @act: irqaction for the interrupt | |
1788 | * | |
1789 | * Used to remove interrupts statically setup by the early boot process. | |
1790 | */ | |
1791 | void remove_irq(unsigned int irq, struct irqaction *act) | |
1792 | { | |
31d9d9b6 MZ |
1793 | struct irq_desc *desc = irq_to_desc(irq); |
1794 | ||
1795 | if (desc && !WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
83ac4ca9 | 1796 | __free_irq(desc, act->dev_id); |
cbf94f06 | 1797 | } |
eb53b4e8 | 1798 | EXPORT_SYMBOL_GPL(remove_irq); |
cbf94f06 | 1799 | |
f21cfb25 MD |
1800 | /** |
1801 | * free_irq - free an interrupt allocated with request_irq | |
1802 | * @irq: Interrupt line to free | |
1803 | * @dev_id: Device identity to free | |
1804 | * | |
1805 | * Remove an interrupt handler. The handler is removed and if the | |
1806 | * interrupt line is no longer in use by any driver it is disabled. | |
1807 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1808 | * on the card it drives before calling this function. The function | |
1809 | * does not return until any executing interrupts for this IRQ | |
1810 | * have completed. | |
1811 | * | |
1812 | * This function must not be called from interrupt context. | |
25ce4be7 CH |
1813 | * |
1814 | * Returns the devname argument passed to request_irq. | |
f21cfb25 | 1815 | */ |
25ce4be7 | 1816 | const void *free_irq(unsigned int irq, void *dev_id) |
f21cfb25 | 1817 | { |
70aedd24 | 1818 | struct irq_desc *desc = irq_to_desc(irq); |
25ce4be7 CH |
1819 | struct irqaction *action; |
1820 | const char *devname; | |
70aedd24 | 1821 | |
31d9d9b6 | 1822 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
25ce4be7 | 1823 | return NULL; |
70aedd24 | 1824 | |
cd7eab44 BH |
1825 | #ifdef CONFIG_SMP |
1826 | if (WARN_ON(desc->affinity_notify)) | |
1827 | desc->affinity_notify = NULL; | |
1828 | #endif | |
1829 | ||
83ac4ca9 | 1830 | action = __free_irq(desc, dev_id); |
2827a418 AM |
1831 | |
1832 | if (!action) | |
1833 | return NULL; | |
1834 | ||
25ce4be7 CH |
1835 | devname = action->name; |
1836 | kfree(action); | |
1837 | return devname; | |
1da177e4 | 1838 | } |
1da177e4 LT |
1839 | EXPORT_SYMBOL(free_irq); |
1840 | ||
b525903c JT |
1841 | /* This function must be called with desc->lock held */ |
1842 | static const void *__cleanup_nmi(unsigned int irq, struct irq_desc *desc) | |
1843 | { | |
1844 | const char *devname = NULL; | |
1845 | ||
1846 | desc->istate &= ~IRQS_NMI; | |
1847 | ||
1848 | if (!WARN_ON(desc->action == NULL)) { | |
1849 | irq_pm_remove_action(desc, desc->action); | |
1850 | devname = desc->action->name; | |
1851 | unregister_handler_proc(irq, desc->action); | |
1852 | ||
1853 | kfree(desc->action); | |
1854 | desc->action = NULL; | |
1855 | } | |
1856 | ||
1857 | irq_settings_clr_disable_unlazy(desc); | |
1858 | irq_shutdown(desc); | |
1859 | ||
1860 | irq_release_resources(desc); | |
1861 | ||
1862 | irq_chip_pm_put(&desc->irq_data); | |
1863 | module_put(desc->owner); | |
1864 | ||
1865 | return devname; | |
1866 | } | |
1867 | ||
1868 | const void *free_nmi(unsigned int irq, void *dev_id) | |
1869 | { | |
1870 | struct irq_desc *desc = irq_to_desc(irq); | |
1871 | unsigned long flags; | |
1872 | const void *devname; | |
1873 | ||
1874 | if (!desc || WARN_ON(!(desc->istate & IRQS_NMI))) | |
1875 | return NULL; | |
1876 | ||
1877 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1878 | return NULL; | |
1879 | ||
1880 | /* NMI still enabled */ | |
1881 | if (WARN_ON(desc->depth == 0)) | |
1882 | disable_nmi_nosync(irq); | |
1883 | ||
1884 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1885 | ||
1886 | irq_nmi_teardown(desc); | |
1887 | devname = __cleanup_nmi(irq, desc); | |
1888 | ||
1889 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1890 | ||
1891 | return devname; | |
1892 | } | |
1893 | ||
1da177e4 | 1894 | /** |
3aa551c9 | 1895 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1896 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1897 | * @handler: Function to be called when the IRQ occurs. |
1898 | * Primary handler for threaded interrupts | |
b25c340c TG |
1899 | * If NULL and thread_fn != NULL the default |
1900 | * primary handler is installed | |
f48fe81e TG |
1901 | * @thread_fn: Function called from the irq handler thread |
1902 | * If NULL, no irq thread is created | |
1da177e4 LT |
1903 | * @irqflags: Interrupt type flags |
1904 | * @devname: An ascii name for the claiming device | |
1905 | * @dev_id: A cookie passed back to the handler function | |
1906 | * | |
1907 | * This call allocates interrupt resources and enables the | |
1908 | * interrupt line and IRQ handling. From the point this | |
1909 | * call is made your handler function may be invoked. Since | |
1910 | * your handler function must clear any interrupt the board | |
1911 | * raises, you must take care both to initialise your hardware | |
1912 | * and to set up the interrupt handler in the right order. | |
1913 | * | |
3aa551c9 | 1914 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1915 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1916 | * still called in hard interrupt context and has to check |
1917 | * whether the interrupt originates from the device. If yes it | |
1918 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1919 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1920 | * @thread_fn. This split handler design is necessary to support |
1921 | * shared interrupts. | |
1922 | * | |
1da177e4 LT |
1923 | * Dev_id must be globally unique. Normally the address of the |
1924 | * device data structure is used as the cookie. Since the handler | |
1925 | * receives this value it makes sense to use it. | |
1926 | * | |
1927 | * If your interrupt is shared you must pass a non NULL dev_id | |
1928 | * as this is required when freeing the interrupt. | |
1929 | * | |
1930 | * Flags: | |
1931 | * | |
3cca53b0 | 1932 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1933 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1934 | * |
1935 | */ | |
3aa551c9 TG |
1936 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1937 | irq_handler_t thread_fn, unsigned long irqflags, | |
1938 | const char *devname, void *dev_id) | |
1da177e4 | 1939 | { |
06fcb0c6 | 1940 | struct irqaction *action; |
08678b08 | 1941 | struct irq_desc *desc; |
d3c60047 | 1942 | int retval; |
1da177e4 | 1943 | |
e237a551 CF |
1944 | if (irq == IRQ_NOTCONNECTED) |
1945 | return -ENOTCONN; | |
1946 | ||
1da177e4 LT |
1947 | /* |
1948 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1949 | * otherwise we'll have trouble later trying to figure out | |
1950 | * which interrupt is which (messes up the interrupt freeing | |
1951 | * logic etc). | |
17f48034 RW |
1952 | * |
1953 | * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and | |
1954 | * it cannot be set along with IRQF_NO_SUSPEND. | |
1da177e4 | 1955 | */ |
17f48034 RW |
1956 | if (((irqflags & IRQF_SHARED) && !dev_id) || |
1957 | (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) || | |
1958 | ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND))) | |
1da177e4 | 1959 | return -EINVAL; |
7d94f7ca | 1960 | |
cb5bc832 | 1961 | desc = irq_to_desc(irq); |
7d94f7ca | 1962 | if (!desc) |
1da177e4 | 1963 | return -EINVAL; |
7d94f7ca | 1964 | |
31d9d9b6 MZ |
1965 | if (!irq_settings_can_request(desc) || |
1966 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 1967 | return -EINVAL; |
b25c340c TG |
1968 | |
1969 | if (!handler) { | |
1970 | if (!thread_fn) | |
1971 | return -EINVAL; | |
1972 | handler = irq_default_primary_handler; | |
1973 | } | |
1da177e4 | 1974 | |
45535732 | 1975 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
1976 | if (!action) |
1977 | return -ENOMEM; | |
1978 | ||
1979 | action->handler = handler; | |
3aa551c9 | 1980 | action->thread_fn = thread_fn; |
1da177e4 | 1981 | action->flags = irqflags; |
1da177e4 | 1982 | action->name = devname; |
1da177e4 LT |
1983 | action->dev_id = dev_id; |
1984 | ||
be45beb2 | 1985 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
1986 | if (retval < 0) { |
1987 | kfree(action); | |
be45beb2 | 1988 | return retval; |
4396f46c | 1989 | } |
be45beb2 | 1990 | |
d3c60047 | 1991 | retval = __setup_irq(irq, desc, action); |
70aedd24 | 1992 | |
2a1d3ab8 | 1993 | if (retval) { |
be45beb2 | 1994 | irq_chip_pm_put(&desc->irq_data); |
2a1d3ab8 | 1995 | kfree(action->secondary); |
377bf1e4 | 1996 | kfree(action); |
2a1d3ab8 | 1997 | } |
377bf1e4 | 1998 | |
6d83f94d | 1999 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 2000 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
2001 | /* |
2002 | * It's a shared IRQ -- the driver ought to be prepared for it | |
2003 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
2004 | * We disable the irq to make sure that a 'real' IRQ doesn't |
2005 | * run in parallel with our fake. | |
a304e1b8 | 2006 | */ |
59845b1f | 2007 | unsigned long flags; |
a304e1b8 | 2008 | |
377bf1e4 | 2009 | disable_irq(irq); |
59845b1f | 2010 | local_irq_save(flags); |
377bf1e4 | 2011 | |
59845b1f | 2012 | handler(irq, dev_id); |
377bf1e4 | 2013 | |
59845b1f | 2014 | local_irq_restore(flags); |
377bf1e4 | 2015 | enable_irq(irq); |
a304e1b8 DW |
2016 | } |
2017 | #endif | |
1da177e4 LT |
2018 | return retval; |
2019 | } | |
3aa551c9 | 2020 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
2021 | |
2022 | /** | |
2023 | * request_any_context_irq - allocate an interrupt line | |
2024 | * @irq: Interrupt line to allocate | |
2025 | * @handler: Function to be called when the IRQ occurs. | |
2026 | * Threaded handler for threaded interrupts. | |
2027 | * @flags: Interrupt type flags | |
2028 | * @name: An ascii name for the claiming device | |
2029 | * @dev_id: A cookie passed back to the handler function | |
2030 | * | |
2031 | * This call allocates interrupt resources and enables the | |
2032 | * interrupt line and IRQ handling. It selects either a | |
2033 | * hardirq or threaded handling method depending on the | |
2034 | * context. | |
2035 | * | |
2036 | * On failure, it returns a negative value. On success, | |
2037 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
2038 | */ | |
2039 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
2040 | unsigned long flags, const char *name, void *dev_id) | |
2041 | { | |
e237a551 | 2042 | struct irq_desc *desc; |
ae731f8d MZ |
2043 | int ret; |
2044 | ||
e237a551 CF |
2045 | if (irq == IRQ_NOTCONNECTED) |
2046 | return -ENOTCONN; | |
2047 | ||
2048 | desc = irq_to_desc(irq); | |
ae731f8d MZ |
2049 | if (!desc) |
2050 | return -EINVAL; | |
2051 | ||
1ccb4e61 | 2052 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
2053 | ret = request_threaded_irq(irq, NULL, handler, |
2054 | flags, name, dev_id); | |
2055 | return !ret ? IRQC_IS_NESTED : ret; | |
2056 | } | |
2057 | ||
2058 | ret = request_irq(irq, handler, flags, name, dev_id); | |
2059 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
2060 | } | |
2061 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 2062 | |
b525903c JT |
2063 | /** |
2064 | * request_nmi - allocate an interrupt line for NMI delivery | |
2065 | * @irq: Interrupt line to allocate | |
2066 | * @handler: Function to be called when the IRQ occurs. | |
2067 | * Threaded handler for threaded interrupts. | |
2068 | * @irqflags: Interrupt type flags | |
2069 | * @name: An ascii name for the claiming device | |
2070 | * @dev_id: A cookie passed back to the handler function | |
2071 | * | |
2072 | * This call allocates interrupt resources and enables the | |
2073 | * interrupt line and IRQ handling. It sets up the IRQ line | |
2074 | * to be handled as an NMI. | |
2075 | * | |
2076 | * An interrupt line delivering NMIs cannot be shared and IRQ handling | |
2077 | * cannot be threaded. | |
2078 | * | |
2079 | * Interrupt lines requested for NMI delivering must produce per cpu | |
2080 | * interrupts and have auto enabling setting disabled. | |
2081 | * | |
2082 | * Dev_id must be globally unique. Normally the address of the | |
2083 | * device data structure is used as the cookie. Since the handler | |
2084 | * receives this value it makes sense to use it. | |
2085 | * | |
2086 | * If the interrupt line cannot be used to deliver NMIs, function | |
2087 | * will fail and return a negative value. | |
2088 | */ | |
2089 | int request_nmi(unsigned int irq, irq_handler_t handler, | |
2090 | unsigned long irqflags, const char *name, void *dev_id) | |
2091 | { | |
2092 | struct irqaction *action; | |
2093 | struct irq_desc *desc; | |
2094 | unsigned long flags; | |
2095 | int retval; | |
2096 | ||
2097 | if (irq == IRQ_NOTCONNECTED) | |
2098 | return -ENOTCONN; | |
2099 | ||
2100 | /* NMI cannot be shared, used for Polling */ | |
2101 | if (irqflags & (IRQF_SHARED | IRQF_COND_SUSPEND | IRQF_IRQPOLL)) | |
2102 | return -EINVAL; | |
2103 | ||
2104 | if (!(irqflags & IRQF_PERCPU)) | |
2105 | return -EINVAL; | |
2106 | ||
2107 | if (!handler) | |
2108 | return -EINVAL; | |
2109 | ||
2110 | desc = irq_to_desc(irq); | |
2111 | ||
2112 | if (!desc || irq_settings_can_autoenable(desc) || | |
2113 | !irq_settings_can_request(desc) || | |
2114 | WARN_ON(irq_settings_is_per_cpu_devid(desc)) || | |
2115 | !irq_supports_nmi(desc)) | |
2116 | return -EINVAL; | |
2117 | ||
2118 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2119 | if (!action) | |
2120 | return -ENOMEM; | |
2121 | ||
2122 | action->handler = handler; | |
2123 | action->flags = irqflags | IRQF_NO_THREAD | IRQF_NOBALANCING; | |
2124 | action->name = name; | |
2125 | action->dev_id = dev_id; | |
2126 | ||
2127 | retval = irq_chip_pm_get(&desc->irq_data); | |
2128 | if (retval < 0) | |
2129 | goto err_out; | |
2130 | ||
2131 | retval = __setup_irq(irq, desc, action); | |
2132 | if (retval) | |
2133 | goto err_irq_setup; | |
2134 | ||
2135 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2136 | ||
2137 | /* Setup NMI state */ | |
2138 | desc->istate |= IRQS_NMI; | |
2139 | retval = irq_nmi_setup(desc); | |
2140 | if (retval) { | |
2141 | __cleanup_nmi(irq, desc); | |
2142 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2143 | return -EINVAL; | |
2144 | } | |
2145 | ||
2146 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2147 | ||
2148 | return 0; | |
2149 | ||
2150 | err_irq_setup: | |
2151 | irq_chip_pm_put(&desc->irq_data); | |
2152 | err_out: | |
2153 | kfree(action); | |
2154 | ||
2155 | return retval; | |
2156 | } | |
2157 | ||
1e7c5fd2 | 2158 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
2159 | { |
2160 | unsigned int cpu = smp_processor_id(); | |
2161 | unsigned long flags; | |
2162 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2163 | ||
2164 | if (!desc) | |
2165 | return; | |
2166 | ||
f35ad083 MZ |
2167 | /* |
2168 | * If the trigger type is not specified by the caller, then | |
2169 | * use the default for this interrupt. | |
2170 | */ | |
1e7c5fd2 | 2171 | type &= IRQ_TYPE_SENSE_MASK; |
f35ad083 MZ |
2172 | if (type == IRQ_TYPE_NONE) |
2173 | type = irqd_get_trigger_type(&desc->irq_data); | |
2174 | ||
1e7c5fd2 MZ |
2175 | if (type != IRQ_TYPE_NONE) { |
2176 | int ret; | |
2177 | ||
a1ff541a | 2178 | ret = __irq_set_trigger(desc, type); |
1e7c5fd2 MZ |
2179 | |
2180 | if (ret) { | |
32cffdde | 2181 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
2182 | goto out; |
2183 | } | |
2184 | } | |
2185 | ||
31d9d9b6 | 2186 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 2187 | out: |
31d9d9b6 MZ |
2188 | irq_put_desc_unlock(desc, flags); |
2189 | } | |
36a5df85 | 2190 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 | 2191 | |
4b078c3f JT |
2192 | void enable_percpu_nmi(unsigned int irq, unsigned int type) |
2193 | { | |
2194 | enable_percpu_irq(irq, type); | |
2195 | } | |
2196 | ||
f0cb3220 TP |
2197 | /** |
2198 | * irq_percpu_is_enabled - Check whether the per cpu irq is enabled | |
2199 | * @irq: Linux irq number to check for | |
2200 | * | |
2201 | * Must be called from a non migratable context. Returns the enable | |
2202 | * state of a per cpu interrupt on the current cpu. | |
2203 | */ | |
2204 | bool irq_percpu_is_enabled(unsigned int irq) | |
2205 | { | |
2206 | unsigned int cpu = smp_processor_id(); | |
2207 | struct irq_desc *desc; | |
2208 | unsigned long flags; | |
2209 | bool is_enabled; | |
2210 | ||
2211 | desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2212 | if (!desc) | |
2213 | return false; | |
2214 | ||
2215 | is_enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); | |
2216 | irq_put_desc_unlock(desc, flags); | |
2217 | ||
2218 | return is_enabled; | |
2219 | } | |
2220 | EXPORT_SYMBOL_GPL(irq_percpu_is_enabled); | |
2221 | ||
31d9d9b6 MZ |
2222 | void disable_percpu_irq(unsigned int irq) |
2223 | { | |
2224 | unsigned int cpu = smp_processor_id(); | |
2225 | unsigned long flags; | |
2226 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
2227 | ||
2228 | if (!desc) | |
2229 | return; | |
2230 | ||
2231 | irq_percpu_disable(desc, cpu); | |
2232 | irq_put_desc_unlock(desc, flags); | |
2233 | } | |
36a5df85 | 2234 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 | 2235 | |
4b078c3f JT |
2236 | void disable_percpu_nmi(unsigned int irq) |
2237 | { | |
2238 | disable_percpu_irq(irq); | |
2239 | } | |
2240 | ||
31d9d9b6 MZ |
2241 | /* |
2242 | * Internal function to unregister a percpu irqaction. | |
2243 | */ | |
2244 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
2245 | { | |
2246 | struct irq_desc *desc = irq_to_desc(irq); | |
2247 | struct irqaction *action; | |
2248 | unsigned long flags; | |
2249 | ||
2250 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
2251 | ||
2252 | if (!desc) | |
2253 | return NULL; | |
2254 | ||
2255 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2256 | ||
2257 | action = desc->action; | |
2258 | if (!action || action->percpu_dev_id != dev_id) { | |
2259 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
2260 | goto bad; | |
2261 | } | |
2262 | ||
2263 | if (!cpumask_empty(desc->percpu_enabled)) { | |
2264 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
2265 | irq, cpumask_first(desc->percpu_enabled)); | |
2266 | goto bad; | |
2267 | } | |
2268 | ||
2269 | /* Found it - now remove it from the list of entries: */ | |
2270 | desc->action = NULL; | |
2271 | ||
4b078c3f JT |
2272 | desc->istate &= ~IRQS_NMI; |
2273 | ||
31d9d9b6 MZ |
2274 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
2275 | ||
2276 | unregister_handler_proc(irq, action); | |
2277 | ||
be45beb2 | 2278 | irq_chip_pm_put(&desc->irq_data); |
31d9d9b6 MZ |
2279 | module_put(desc->owner); |
2280 | return action; | |
2281 | ||
2282 | bad: | |
2283 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2284 | return NULL; | |
2285 | } | |
2286 | ||
2287 | /** | |
2288 | * remove_percpu_irq - free a per-cpu interrupt | |
2289 | * @irq: Interrupt line to free | |
2290 | * @act: irqaction for the interrupt | |
2291 | * | |
2292 | * Used to remove interrupts statically setup by the early boot process. | |
2293 | */ | |
2294 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
2295 | { | |
2296 | struct irq_desc *desc = irq_to_desc(irq); | |
2297 | ||
2298 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
2299 | __free_percpu_irq(irq, act->percpu_dev_id); | |
2300 | } | |
2301 | ||
2302 | /** | |
2303 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
2304 | * @irq: Interrupt line to free | |
2305 | * @dev_id: Device identity to free | |
2306 | * | |
2307 | * Remove a percpu interrupt handler. The handler is removed, but | |
2308 | * the interrupt line is not disabled. This must be done on each | |
2309 | * CPU before calling this function. The function does not return | |
2310 | * until any executing interrupts for this IRQ have completed. | |
2311 | * | |
2312 | * This function must not be called from interrupt context. | |
2313 | */ | |
2314 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
2315 | { | |
2316 | struct irq_desc *desc = irq_to_desc(irq); | |
2317 | ||
2318 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2319 | return; | |
2320 | ||
2321 | chip_bus_lock(desc); | |
2322 | kfree(__free_percpu_irq(irq, dev_id)); | |
2323 | chip_bus_sync_unlock(desc); | |
2324 | } | |
aec2e2ad | 2325 | EXPORT_SYMBOL_GPL(free_percpu_irq); |
31d9d9b6 | 2326 | |
4b078c3f JT |
2327 | void free_percpu_nmi(unsigned int irq, void __percpu *dev_id) |
2328 | { | |
2329 | struct irq_desc *desc = irq_to_desc(irq); | |
2330 | ||
2331 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2332 | return; | |
2333 | ||
2334 | if (WARN_ON(!(desc->istate & IRQS_NMI))) | |
2335 | return; | |
2336 | ||
2337 | kfree(__free_percpu_irq(irq, dev_id)); | |
2338 | } | |
2339 | ||
31d9d9b6 MZ |
2340 | /** |
2341 | * setup_percpu_irq - setup a per-cpu interrupt | |
2342 | * @irq: Interrupt line to setup | |
2343 | * @act: irqaction for the interrupt | |
2344 | * | |
2345 | * Used to statically setup per-cpu interrupts in the early boot process. | |
2346 | */ | |
2347 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
2348 | { | |
2349 | struct irq_desc *desc = irq_to_desc(irq); | |
2350 | int retval; | |
2351 | ||
2352 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
2353 | return -EINVAL; | |
be45beb2 JH |
2354 | |
2355 | retval = irq_chip_pm_get(&desc->irq_data); | |
2356 | if (retval < 0) | |
2357 | return retval; | |
2358 | ||
31d9d9b6 | 2359 | retval = __setup_irq(irq, desc, act); |
31d9d9b6 | 2360 | |
be45beb2 JH |
2361 | if (retval) |
2362 | irq_chip_pm_put(&desc->irq_data); | |
2363 | ||
31d9d9b6 MZ |
2364 | return retval; |
2365 | } | |
2366 | ||
2367 | /** | |
c80081b9 | 2368 | * __request_percpu_irq - allocate a percpu interrupt line |
31d9d9b6 MZ |
2369 | * @irq: Interrupt line to allocate |
2370 | * @handler: Function to be called when the IRQ occurs. | |
c80081b9 | 2371 | * @flags: Interrupt type flags (IRQF_TIMER only) |
31d9d9b6 MZ |
2372 | * @devname: An ascii name for the claiming device |
2373 | * @dev_id: A percpu cookie passed back to the handler function | |
2374 | * | |
a1b7febd MR |
2375 | * This call allocates interrupt resources and enables the |
2376 | * interrupt on the local CPU. If the interrupt is supposed to be | |
2377 | * enabled on other CPUs, it has to be done on each CPU using | |
2378 | * enable_percpu_irq(). | |
31d9d9b6 MZ |
2379 | * |
2380 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
2381 | * the handler gets called with the interrupted CPU's instance of | |
2382 | * that variable. | |
2383 | */ | |
c80081b9 DL |
2384 | int __request_percpu_irq(unsigned int irq, irq_handler_t handler, |
2385 | unsigned long flags, const char *devname, | |
2386 | void __percpu *dev_id) | |
31d9d9b6 MZ |
2387 | { |
2388 | struct irqaction *action; | |
2389 | struct irq_desc *desc; | |
2390 | int retval; | |
2391 | ||
2392 | if (!dev_id) | |
2393 | return -EINVAL; | |
2394 | ||
2395 | desc = irq_to_desc(irq); | |
2396 | if (!desc || !irq_settings_can_request(desc) || | |
2397 | !irq_settings_is_per_cpu_devid(desc)) | |
2398 | return -EINVAL; | |
2399 | ||
c80081b9 DL |
2400 | if (flags && flags != IRQF_TIMER) |
2401 | return -EINVAL; | |
2402 | ||
31d9d9b6 MZ |
2403 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
2404 | if (!action) | |
2405 | return -ENOMEM; | |
2406 | ||
2407 | action->handler = handler; | |
c80081b9 | 2408 | action->flags = flags | IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
2409 | action->name = devname; |
2410 | action->percpu_dev_id = dev_id; | |
2411 | ||
be45beb2 | 2412 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
2413 | if (retval < 0) { |
2414 | kfree(action); | |
be45beb2 | 2415 | return retval; |
4396f46c | 2416 | } |
be45beb2 | 2417 | |
31d9d9b6 | 2418 | retval = __setup_irq(irq, desc, action); |
31d9d9b6 | 2419 | |
be45beb2 JH |
2420 | if (retval) { |
2421 | irq_chip_pm_put(&desc->irq_data); | |
31d9d9b6 | 2422 | kfree(action); |
be45beb2 | 2423 | } |
31d9d9b6 MZ |
2424 | |
2425 | return retval; | |
2426 | } | |
c80081b9 | 2427 | EXPORT_SYMBOL_GPL(__request_percpu_irq); |
1b7047ed | 2428 | |
4b078c3f JT |
2429 | /** |
2430 | * request_percpu_nmi - allocate a percpu interrupt line for NMI delivery | |
2431 | * @irq: Interrupt line to allocate | |
2432 | * @handler: Function to be called when the IRQ occurs. | |
2433 | * @name: An ascii name for the claiming device | |
2434 | * @dev_id: A percpu cookie passed back to the handler function | |
2435 | * | |
2436 | * This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs | |
a5186694 JT |
2437 | * have to be setup on each CPU by calling prepare_percpu_nmi() before |
2438 | * being enabled on the same CPU by using enable_percpu_nmi(). | |
4b078c3f JT |
2439 | * |
2440 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
2441 | * the handler gets called with the interrupted CPU's instance of | |
2442 | * that variable. | |
2443 | * | |
2444 | * Interrupt lines requested for NMI delivering should have auto enabling | |
2445 | * setting disabled. | |
2446 | * | |
2447 | * If the interrupt line cannot be used to deliver NMIs, function | |
2448 | * will fail returning a negative value. | |
2449 | */ | |
2450 | int request_percpu_nmi(unsigned int irq, irq_handler_t handler, | |
2451 | const char *name, void __percpu *dev_id) | |
2452 | { | |
2453 | struct irqaction *action; | |
2454 | struct irq_desc *desc; | |
2455 | unsigned long flags; | |
2456 | int retval; | |
2457 | ||
2458 | if (!handler) | |
2459 | return -EINVAL; | |
2460 | ||
2461 | desc = irq_to_desc(irq); | |
2462 | ||
2463 | if (!desc || !irq_settings_can_request(desc) || | |
2464 | !irq_settings_is_per_cpu_devid(desc) || | |
2465 | irq_settings_can_autoenable(desc) || | |
2466 | !irq_supports_nmi(desc)) | |
2467 | return -EINVAL; | |
2468 | ||
2469 | /* The line cannot already be NMI */ | |
2470 | if (desc->istate & IRQS_NMI) | |
2471 | return -EINVAL; | |
2472 | ||
2473 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2474 | if (!action) | |
2475 | return -ENOMEM; | |
2476 | ||
2477 | action->handler = handler; | |
2478 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND | IRQF_NO_THREAD | |
2479 | | IRQF_NOBALANCING; | |
2480 | action->name = name; | |
2481 | action->percpu_dev_id = dev_id; | |
2482 | ||
2483 | retval = irq_chip_pm_get(&desc->irq_data); | |
2484 | if (retval < 0) | |
2485 | goto err_out; | |
2486 | ||
2487 | retval = __setup_irq(irq, desc, action); | |
2488 | if (retval) | |
2489 | goto err_irq_setup; | |
2490 | ||
2491 | raw_spin_lock_irqsave(&desc->lock, flags); | |
2492 | desc->istate |= IRQS_NMI; | |
2493 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
2494 | ||
2495 | return 0; | |
2496 | ||
2497 | err_irq_setup: | |
2498 | irq_chip_pm_put(&desc->irq_data); | |
2499 | err_out: | |
2500 | kfree(action); | |
2501 | ||
2502 | return retval; | |
2503 | } | |
2504 | ||
2505 | /** | |
2506 | * prepare_percpu_nmi - performs CPU local setup for NMI delivery | |
2507 | * @irq: Interrupt line to prepare for NMI delivery | |
2508 | * | |
2509 | * This call prepares an interrupt line to deliver NMI on the current CPU, | |
2510 | * before that interrupt line gets enabled with enable_percpu_nmi(). | |
2511 | * | |
2512 | * As a CPU local operation, this should be called from non-preemptible | |
2513 | * context. | |
2514 | * | |
2515 | * If the interrupt line cannot be used to deliver NMIs, function | |
2516 | * will fail returning a negative value. | |
2517 | */ | |
2518 | int prepare_percpu_nmi(unsigned int irq) | |
2519 | { | |
2520 | unsigned long flags; | |
2521 | struct irq_desc *desc; | |
2522 | int ret = 0; | |
2523 | ||
2524 | WARN_ON(preemptible()); | |
2525 | ||
2526 | desc = irq_get_desc_lock(irq, &flags, | |
2527 | IRQ_GET_DESC_CHECK_PERCPU); | |
2528 | if (!desc) | |
2529 | return -EINVAL; | |
2530 | ||
2531 | if (WARN(!(desc->istate & IRQS_NMI), | |
2532 | KERN_ERR "prepare_percpu_nmi called for a non-NMI interrupt: irq %u\n", | |
2533 | irq)) { | |
2534 | ret = -EINVAL; | |
2535 | goto out; | |
2536 | } | |
2537 | ||
2538 | ret = irq_nmi_setup(desc); | |
2539 | if (ret) { | |
2540 | pr_err("Failed to setup NMI delivery: irq %u\n", irq); | |
2541 | goto out; | |
2542 | } | |
2543 | ||
2544 | out: | |
2545 | irq_put_desc_unlock(desc, flags); | |
2546 | return ret; | |
2547 | } | |
2548 | ||
2549 | /** | |
2550 | * teardown_percpu_nmi - undoes NMI setup of IRQ line | |
2551 | * @irq: Interrupt line from which CPU local NMI configuration should be | |
2552 | * removed | |
2553 | * | |
2554 | * This call undoes the setup done by prepare_percpu_nmi(). | |
2555 | * | |
2556 | * IRQ line should not be enabled for the current CPU. | |
2557 | * | |
2558 | * As a CPU local operation, this should be called from non-preemptible | |
2559 | * context. | |
2560 | */ | |
2561 | void teardown_percpu_nmi(unsigned int irq) | |
2562 | { | |
2563 | unsigned long flags; | |
2564 | struct irq_desc *desc; | |
2565 | ||
2566 | WARN_ON(preemptible()); | |
2567 | ||
2568 | desc = irq_get_desc_lock(irq, &flags, | |
2569 | IRQ_GET_DESC_CHECK_PERCPU); | |
2570 | if (!desc) | |
2571 | return; | |
2572 | ||
2573 | if (WARN_ON(!(desc->istate & IRQS_NMI))) | |
2574 | goto out; | |
2575 | ||
2576 | irq_nmi_teardown(desc); | |
2577 | out: | |
2578 | irq_put_desc_unlock(desc, flags); | |
2579 | } | |
2580 | ||
1b7047ed MZ |
2581 | /** |
2582 | * irq_get_irqchip_state - returns the irqchip state of a interrupt. | |
2583 | * @irq: Interrupt line that is forwarded to a VM | |
2584 | * @which: One of IRQCHIP_STATE_* the caller wants to know about | |
2585 | * @state: a pointer to a boolean where the state is to be storeed | |
2586 | * | |
2587 | * This call snapshots the internal irqchip state of an | |
2588 | * interrupt, returning into @state the bit corresponding to | |
2589 | * stage @which | |
2590 | * | |
2591 | * This function should be called with preemption disabled if the | |
2592 | * interrupt controller has per-cpu registers. | |
2593 | */ | |
2594 | int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2595 | bool *state) | |
2596 | { | |
2597 | struct irq_desc *desc; | |
2598 | struct irq_data *data; | |
2599 | struct irq_chip *chip; | |
2600 | unsigned long flags; | |
2601 | int err = -EINVAL; | |
2602 | ||
2603 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2604 | if (!desc) | |
2605 | return err; | |
2606 | ||
2607 | data = irq_desc_get_irq_data(desc); | |
2608 | ||
2609 | do { | |
2610 | chip = irq_data_get_irq_chip(data); | |
2611 | if (chip->irq_get_irqchip_state) | |
2612 | break; | |
2613 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2614 | data = data->parent_data; | |
2615 | #else | |
2616 | data = NULL; | |
2617 | #endif | |
2618 | } while (data); | |
2619 | ||
2620 | if (data) | |
2621 | err = chip->irq_get_irqchip_state(data, which, state); | |
2622 | ||
2623 | irq_put_desc_busunlock(desc, flags); | |
2624 | return err; | |
2625 | } | |
1ee4fb3e | 2626 | EXPORT_SYMBOL_GPL(irq_get_irqchip_state); |
1b7047ed MZ |
2627 | |
2628 | /** | |
2629 | * irq_set_irqchip_state - set the state of a forwarded interrupt. | |
2630 | * @irq: Interrupt line that is forwarded to a VM | |
2631 | * @which: State to be restored (one of IRQCHIP_STATE_*) | |
2632 | * @val: Value corresponding to @which | |
2633 | * | |
2634 | * This call sets the internal irqchip state of an interrupt, | |
2635 | * depending on the value of @which. | |
2636 | * | |
2637 | * This function should be called with preemption disabled if the | |
2638 | * interrupt controller has per-cpu registers. | |
2639 | */ | |
2640 | int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2641 | bool val) | |
2642 | { | |
2643 | struct irq_desc *desc; | |
2644 | struct irq_data *data; | |
2645 | struct irq_chip *chip; | |
2646 | unsigned long flags; | |
2647 | int err = -EINVAL; | |
2648 | ||
2649 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2650 | if (!desc) | |
2651 | return err; | |
2652 | ||
2653 | data = irq_desc_get_irq_data(desc); | |
2654 | ||
2655 | do { | |
2656 | chip = irq_data_get_irq_chip(data); | |
2657 | if (chip->irq_set_irqchip_state) | |
2658 | break; | |
2659 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2660 | data = data->parent_data; | |
2661 | #else | |
2662 | data = NULL; | |
2663 | #endif | |
2664 | } while (data); | |
2665 | ||
2666 | if (data) | |
2667 | err = chip->irq_set_irqchip_state(data, which, val); | |
2668 | ||
2669 | irq_put_desc_busunlock(desc, flags); | |
2670 | return err; | |
2671 | } | |
1ee4fb3e | 2672 | EXPORT_SYMBOL_GPL(irq_set_irqchip_state); |