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d9a5d113 MF |
1 | /* |
2 | * U-boot - u-boot.lds.S | |
3 | * | |
4 | * Copyright (c) 2005-2008 Analog Device Inc. | |
5 | * | |
6 | * (C) Copyright 2000-2004 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <config.h> | |
29 | #include <asm/blackfin.h> | |
30 | #undef ALIGN | |
31 | #undef ENTRY | |
32 | #undef bfin | |
33 | ||
9ff67e5e MF |
34 | #ifndef LDS_BOARD_TEXT |
35 | # define LDS_BOARD_TEXT | |
36 | #endif | |
37 | ||
d9a5d113 MF |
38 | /* If we don't actually load anything into L1 data, this will avoid |
39 | * a syntax error. If we do actually load something into L1 data, | |
40 | * we'll get a linker memory load error (which is what we'd want). | |
41 | * This is here in the first place so we can quickly test building | |
42 | * for different CPU's which may lack non-cache L1 data. | |
43 | */ | |
44 | #ifndef L1_DATA_B_SRAM | |
45 | # define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE | |
46 | # define L1_DATA_B_SRAM_SIZE 0 | |
47 | #endif | |
48 | ||
f51e0011 MF |
49 | /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ |
50 | #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 | |
51 | # define L1_CODE_ORIGIN L1_INST_SRAM | |
52 | #else | |
53 | # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC | |
54 | #endif | |
55 | ||
d9a5d113 MF |
56 | OUTPUT_ARCH(bfin) |
57 | ||
58 | MEMORY | |
59 | { | |
7527feef | 60 | #if CONFIG_MEM_SIZE |
d9a5d113 | 61 | ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
7527feef MF |
62 | # define ram_code ram |
63 | # define ram_data ram | |
64 | #else | |
65 | # define ram_code l1_code | |
66 | # define ram_data l1_data | |
67 | #endif | |
f51e0011 | 68 | l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE |
d9a5d113 MF |
69 | l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
70 | } | |
71 | ||
72 | ENTRY(_start) | |
73 | SECTIONS | |
74 | { | |
b1e2c551 | 75 | .text.pre : |
d9a5d113 MF |
76 | { |
77 | cpu/blackfin/start.o (.text .text.*) | |
9ff67e5e MF |
78 | |
79 | LDS_BOARD_TEXT | |
b1e2c551 | 80 | } >ram_code |
9ff67e5e | 81 | |
b1e2c551 MF |
82 | .text.init : |
83 | { | |
d9a5d113 | 84 | cpu/blackfin/initcode.o (.text .text.*) |
b1e2c551 MF |
85 | } >ram_code |
86 | __initcode_lma = LOADADDR(.text.init); | |
87 | __initcode_len = SIZEOF(.text.init); | |
9ff67e5e | 88 | |
b1e2c551 MF |
89 | .text : |
90 | { | |
d9a5d113 | 91 | *(.text .text.*) |
7527feef | 92 | } >ram_code |
d9a5d113 MF |
93 | |
94 | .rodata : | |
95 | { | |
96 | . = ALIGN(4); | |
ed912d4d | 97 | *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
d9a5d113 | 98 | . = ALIGN(4); |
7527feef | 99 | } >ram_data |
d9a5d113 MF |
100 | |
101 | .data : | |
102 | { | |
103 | . = ALIGN(256); | |
104 | *(.data .data.*) | |
105 | *(.data1) | |
106 | *(.sdata) | |
107 | *(.sdata2) | |
108 | *(.dynamic) | |
109 | CONSTRUCTORS | |
7527feef | 110 | } >ram_data |
d9a5d113 MF |
111 | |
112 | .u_boot_cmd : | |
113 | { | |
114 | ___u_boot_cmd_start = .; | |
115 | *(.u_boot_cmd) | |
116 | ___u_boot_cmd_end = .; | |
7527feef | 117 | } >ram_data |
d9a5d113 MF |
118 | |
119 | .text_l1 : | |
120 | { | |
121 | . = ALIGN(4); | |
122 | __stext_l1 = .; | |
123 | *(.l1.text) | |
124 | . = ALIGN(4); | |
125 | __etext_l1 = .; | |
7527feef | 126 | } >l1_code AT>ram_code |
b1e2c551 MF |
127 | __text_l1_lma = LOADADDR(.text_l1); |
128 | __text_l1_len = SIZEOF(.text_l1); | |
129 | ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!") | |
d9a5d113 MF |
130 | |
131 | .data_l1 : | |
132 | { | |
133 | . = ALIGN(4); | |
134 | __sdata_l1 = .; | |
135 | *(.l1.data) | |
136 | *(.l1.bss) | |
137 | . = ALIGN(4); | |
138 | __edata_l1 = .; | |
7527feef | 139 | } >l1_data AT>ram_data |
b1e2c551 MF |
140 | __data_l1_lma = LOADADDR(.data_l1); |
141 | __data_l1_len = SIZEOF(.data_l1); | |
142 | ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") | |
d9a5d113 MF |
143 | |
144 | .bss : | |
145 | { | |
146 | . = ALIGN(4); | |
d9a5d113 MF |
147 | *(.sbss) *(.scommon) |
148 | *(.dynbss) | |
149 | *(.bss .bss.*) | |
150 | *(COMMON) | |
7527feef | 151 | } >ram_data |
b1e2c551 MF |
152 | __bss_vma = ADDR(.bss); |
153 | __bss_len = SIZEOF(.bss); | |
d9a5d113 | 154 | } |