[people/ms/u-boot.git] / lib_m68k / time.c

/*
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#include <asm/mcftimer.h>

#ifdef	CONFIG_M5271
#include <asm/m5271.h>
#include <asm/immap_5271.h>
#endif

#ifdef	CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif

#ifdef	CONFIG_M5282
#include <asm/m5282.h>
#endif

#ifdef	CONFIG_M5249
#include <asm/m5249.h>
#include <asm/immap_5249.h>
#endif


static ulong timestamp;
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
static unsigned short lastinc;
#endif


#if defined(CONFIG_M5272)
/*
 * We use timer 3 which is running with a period of 1 us
 */
void udelay(unsigned long usec)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
		timerp->timer_tcn = 0;
		/* set period to 1 us */
		timerp->timer_tmr = (((CFG_CLK / 1000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
				     MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;

		start = now = timerp->timer_tcn;
		while (now < start + tmp)
			now = timerp->timer_tcn;
	}
}

void mcf_timer_interrupt (void * not_used){
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
	volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);

	/* check for timer 4 interrupts */
	if ((intp->int_isr & 0x01000000) != 0) {
		return;
	}

	/* reset timer */
	timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
	timestamp ++;
}

void timer_init (void) {
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
	volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);

	timestamp = 0;

	/* Set up TIMER 4 as clock */
	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;

	/* initialize and enable timer 4 interrupt */
	irq_install_handler (72, mcf_timer_interrupt, 0);
	intp->int_icr1 |= 0x0000000d;

	timerp->timer_tcn = 0;
	timerp->timer_trr = 1000;	/* Interrupt every ms */
	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	timerp->timer_tmr = (((CFG_CLK / 1000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}

void reset_timer (void)
{
	timestamp = 0;
}

ulong get_timer (ulong base)
{
	return (timestamp - base);
}

void set_timer (ulong t)
{
	timestamp = t;
}
#endif

#if defined(CONFIG_M5282) || defined(CONFIG_M5271)

void udelay(unsigned long usec)
{
	volatile unsigned short *timerp;
	uint tmp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 3 as timebase clock */
		timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
		timerp[MCFTIMER_PMR] = 0;
		/* set period to 1 us */
		timerp[MCFTIMER_PCSR] =
			(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;

		timerp[MCFTIMER_PMR] = tmp;
		while (timerp[MCFTIMER_PCNTR] > 0);
	}
}

void timer_init (void)
{
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	timestamp = 0;

	/* Set up TIMER 4 as poll clock */
	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	timerp[MCFTIMER_PMR] = lastinc = 0;
	timerp[MCFTIMER_PCSR] =
		(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
}

void set_timer (ulong t)
{
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	timestamp = 0;
	timerp[MCFTIMER_PMR] = lastinc = 0;
}

ulong get_timer (ulong base)
{
	unsigned short now, diff;
	volatile unsigned short *timerp;

	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	now = timerp[MCFTIMER_PCNTR];
	diff = -(now - lastinc);

	timestamp += diff;
	lastinc = now;
	return timestamp - base;
}

void wait_ticks (unsigned long ticks)
{
	set_timer (0);
	while (get_timer (0) < ticks);
}
#endif


#if defined(CONFIG_M5249)
/*
 * We use timer 1 which is running with a period of 1 us
 */
void udelay(unsigned long usec)
{
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
	uint start, now, tmp;

	while (usec > 0) {
		if (usec > 65000)
			tmp = 65000;
		else
			tmp = usec;
		usec = usec - tmp;

		/* Set up TIMER 1 as timebase clock */
		timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
		timerp->timer_tcn = 0;
		/* set period to 1 us */
		/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
		timerp->timer_tmr = (((CFG_CLK / 2000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
				     MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;

		start = now = timerp->timer_tcn;
		while (now < start + tmp)
			now = timerp->timer_tcn;
	}
}

void mcf_timer_interrupt (void * not_used){
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);

	/* check for timer 2 interrupts */
	if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
		return;
	}

	/* reset timer */
	timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
	timestamp ++;
}

void timer_init (void) {
	volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);

	timestamp = 0;

	/* Set up TIMER 2 as clock */
	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;

	/* initialize and enable timer 2 interrupt */
	irq_install_handler (31, mcf_timer_interrupt, 0);
	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
	mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);

	timerp->timer_tcn = 0;
	timerp->timer_trr = 1000;	/* Interrupt every ms */
	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	timerp->timer_tmr = (((CFG_CLK / 2000000) - 1)	<< 8) | MCFTIMER_TMR_CLK1 |
		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}

void reset_timer (void)
{
	timestamp = 0;
}

ulong get_timer (ulong base)
{
	return (timestamp - base);
}

void set_timer (ulong t)
{
	timestamp = t;
}
#endif


/*
 * This function is derived from PowerPC code (read timebase as long long).
 * On M68K it just returns the timer value.
 */
unsigned long long get_ticks(void)
{
	return get_timer(0);
}

/*
 * This function is derived from PowerPC code (timebase clock frequency).
 * On M68K it returns the number of timer ticks per second.
 */
ulong get_tbclk (void)
{
	ulong tbclk;
	tbclk = CFG_HZ;
	return tbclk;
}
Commit	Line	Data
4e5ca3eb	1	/*
bf9e3b38 WD	2	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	3	*
	4	* (C) Copyright 2000
4e5ca3eb WD	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
bf9e3b38	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4e5ca3eb WD	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27
bf9e3b38 WD	28	#include <asm/mcftimer.h>
bf9e3b38 WD	29
eacbd317 ZL	30	#ifdef CONFIG_M5271
	31	#include <asm/m5271.h>
	32	#include <asm/immap_5271.h>
	33	#endif
	34
bf9e3b38 WD	35	#ifdef CONFIG_M5272
	36	#include <asm/m5272.h>
	37	#include <asm/immap_5272.h>
	38	#endif
	39
	40	#ifdef CONFIG_M5282
	41	#include <asm/m5282.h>
	42	#endif
	43
cd42deeb SR	44	#ifdef CONFIG_M5249
	45	#include <asm/m5249.h>
	46	#include <asm/immap_5249.h>
	47	#endif
	48
bf9e3b38 WD	49
bf9e3b38 WD	50	static ulong timestamp;
eacbd317	51	#if defined(CONFIG_M5282) \|\| defined(CONFIG_M5271)
bf9e3b38 WD	52	static unsigned short lastinc;
bf9e3b38 WD	53	#endif
4e5ca3eb	54
4e5ca3eb	55
bf9e3b38	56	#if defined(CONFIG_M5272)
4e5ca3eb	57	/*
bf9e3b38	58	* We use timer 3 which is running with a period of 1 us
4e5ca3eb	59	*/
bf9e3b38	60	void udelay(unsigned long usec)
4e5ca3eb	61	{
bf9e3b38 WD	62	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE3);
	63	uint start, now, tmp;
	64
	65	while (usec > 0) {
	66	if (usec > 65000)
	67	tmp = 65000;
	68	else
	69	tmp = usec;
	70	usec = usec - tmp;
	71
	72	/* Set up TIMER 3 as timebase clock */
	73	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	74	timerp->timer_tcn = 0;
	75	/* set period to 1 us */
	76	timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	77	MCFTIMER_TMR_FREERUN \| MCFTIMER_TMR_ENABLE;
	78
	79	start = now = timerp->timer_tcn;
	80	while (now < start + tmp)
	81	now = timerp->timer_tcn;
	82	}
	83	}
	84
	85	void mcf_timer_interrupt (void * not_used){
	86	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE4);
	87	volatile intctrl_t intp = (intctrl_t ) (CFG_MBAR + MCFSIM_ICR1);
4e5ca3eb	88
bf9e3b38 WD	89	/* check for timer 4 interrupts */
	90	if ((intp->int_isr & 0x01000000) != 0) {
	91	return;
4e5ca3eb WD	92	}
4e5ca3eb WD	93
bf9e3b38 WD	94	/* reset timer */
	95	timerp->timer_ter = MCFTIMER_TER_CAP \| MCFTIMER_TER_REF;
	96	timestamp ++;
4e5ca3eb WD	97	}
4e5ca3eb WD	98
bf9e3b38 WD	99	void timer_init (void) {
	100	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE4);
	101	volatile intctrl_t intp = (intctrl_t ) (CFG_MBAR + MCFSIM_ICR1);
4e5ca3eb	102
bf9e3b38 WD	103	timestamp = 0;
	104
	105	/* Set up TIMER 4 as clock */
	106	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	107
	108	/* initialize and enable timer 4 interrupt */
	109	irq_install_handler (72, mcf_timer_interrupt, 0);
	110	intp->int_icr1 \|= 0x0000000d;
	111
	112	timerp->timer_tcn = 0;
	113	timerp->timer_trr = 1000; /* Interrupt every ms */
	114	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	115	timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	116	MCFTIMER_TMR_RESTART \| MCFTIMER_TMR_ENORI \| MCFTIMER_TMR_ENABLE;
	117	}
	118
	119	void reset_timer (void)
4e5ca3eb	120	{
bf9e3b38 WD	121	timestamp = 0;
bf9e3b38 WD	122	}
4e5ca3eb	123
bf9e3b38 WD	124	ulong get_timer (ulong base)
	125	{
	126	return (timestamp - base);
4e5ca3eb WD	127	}
4e5ca3eb WD	128
bf9e3b38 WD	129	void set_timer (ulong t)
	130	{
	131	timestamp = t;
	132	}
	133	#endif
4e5ca3eb	134
eacbd317	135	#if defined(CONFIG_M5282) \|\| defined(CONFIG_M5271)
bf9e3b38 WD	136
bf9e3b38 WD	137	void udelay(unsigned long usec)
4e5ca3eb	138	{
50712ba1 WD	139	volatile unsigned short *timerp;
	140	uint tmp;
	141
	142	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
3c2b3d45	143
50712ba1 WD	144	while (usec > 0) {
	145	if (usec > 65000)
	146	tmp = 65000;
	147	else
	148	tmp = usec;
	149	usec = usec - tmp;
	150
	151	/* Set up TIMER 3 as timebase clock */
	152	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	153	timerp[MCFTIMER_PMR] = 0;
	154	/* set period to 1 us */
	155	timerp[MCFTIMER_PCSR] =
	156	(5 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	157
3c2b3d45	158	timerp[MCFTIMER_PMR] = tmp;
50712ba1 WD	159	while (timerp[MCFTIMER_PCNTR] > 0);
50712ba1 WD	160	}
4e5ca3eb WD	161	}
4e5ca3eb WD	162
bf9e3b38 WD	163	void timer_init (void)
	164	{
	165	volatile unsigned short *timerp;
	166
	167	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	168	timestamp = 0;
	169
	170	/* Set up TIMER 4 as poll clock */
	171	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
	172	timerp[MCFTIMER_PMR] = lastinc = 0;
	173	timerp[MCFTIMER_PCSR] =
	174	(5 << 8) \| MCFTIMER_PCSR_EN \| MCFTIMER_PCSR_OVW;
	175	}
4e5ca3eb	176
bf9e3b38	177	void set_timer (ulong t)
4e5ca3eb	178	{
bf9e3b38 WD	179	volatile unsigned short *timerp;
	180
	181	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	182	timestamp = 0;
	183	timerp[MCFTIMER_PMR] = lastinc = 0;
	184	}
	185
	186	ulong get_timer (ulong base)
	187	{
	188	unsigned short now, diff;
	189	volatile unsigned short *timerp;
	190
	191	timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
	192	now = timerp[MCFTIMER_PCNTR];
	193	diff = -(now - lastinc);
	194
	195	timestamp += diff;
	196	lastinc = now;
	197	return timestamp - base;
4e5ca3eb WD	198	}
4e5ca3eb WD	199
bf9e3b38 WD	200	void wait_ticks (unsigned long ticks)
	201	{
	202	set_timer (0);
	203	while (get_timer (0) < ticks);
	204	}
	205	#endif
70f05ac3 WD	206
70f05ac3 WD	207
cd42deeb SR	208	#if defined(CONFIG_M5249)
	209	/*
	210	* We use timer 1 which is running with a period of 1 us
	211	*/
	212	void udelay(unsigned long usec)
	213	{
	214	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE1);
	215	uint start, now, tmp;
	216
	217	while (usec > 0) {
	218	if (usec > 65000)
	219	tmp = 65000;
	220	else
	221	tmp = usec;
	222	usec = usec - tmp;
	223
	224	/* Set up TIMER 1 as timebase clock */
	225	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	226	timerp->timer_tcn = 0;
	227	/* set period to 1 us */
	228	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	229	timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	230	MCFTIMER_TMR_FREERUN \| MCFTIMER_TMR_ENABLE;
	231
	232	start = now = timerp->timer_tcn;
	233	while (now < start + tmp)
	234	now = timerp->timer_tcn;
	235	}
	236	}
	237
	238	void mcf_timer_interrupt (void * not_used){
	239	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE2);
	240
	241	/* check for timer 2 interrupts */
	242	if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
	243	return;
	244	}
	245
	246	/* reset timer */
	247	timerp->timer_ter = MCFTIMER_TER_CAP \| MCFTIMER_TER_REF;
	248	timestamp ++;
	249	}
	250
	251	void timer_init (void) {
	252	volatile timer_t timerp = (timer_t ) (CFG_MBAR + MCFTIMER_BASE2);
	253
	254	timestamp = 0;
	255
	256	/* Set up TIMER 2 as clock */
	257	timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
	258
	259	/* initialize and enable timer 2 interrupt */
	260	irq_install_handler (31, mcf_timer_interrupt, 0);
	261	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
	262	mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL7 \| MCFSIM_ICR_PRI3);
	263
	264	timerp->timer_tcn = 0;
	265	timerp->timer_trr = 1000; /* Interrupt every ms */
	266	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
	267	/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
	268	timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) \| MCFTIMER_TMR_CLK1 \|
	269	MCFTIMER_TMR_RESTART \| MCFTIMER_TMR_ENORI \| MCFTIMER_TMR_ENABLE;
	270	}
	271
272	void reset_timer (void)
273	{
274	timestamp = 0;
275	}
276
277	ulong get_timer (ulong base)
278	{
279	return (timestamp - base);
280	}
281
282	void set_timer (ulong t)
283	{
284	timestamp = t;
285	}
286	#endif
287
288
70f05ac3 WD	289	/*
	290	* This function is derived from PowerPC code (read timebase as long long).
	291	* On M68K it just returns the timer value.
	292	*/
	293	unsigned long long get_ticks(void)
	294	{
	295	return get_timer(0);
	296	}
	297
	298	/*
	299	* This function is derived from PowerPC code (timebase clock frequency).
	300	* On M68K it returns the number of timer ticks per second.
	301	*/
	302	ulong get_tbclk (void)
	303	{
	304	ulong tbclk;
	305	tbclk = CFG_HZ;
	306	return tbclk;
	307	}