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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
28#include <devices.h>
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
WD
32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
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36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
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39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
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42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
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45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
281e00a3 51#include <serial.h>
fe8c2806 52#ifdef CFG_ALLOC_DPRAM
9c4c5ae3 53#if !defined(CONFIG_CPM2)
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54#include <commproc.h>
55#endif
7aa78614 56#endif
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57#include <version.h>
58#if defined(CONFIG_BAB7xx)
59#include <w83c553f.h>
60#endif
61#include <dtt.h>
62#if defined(CONFIG_POST)
63#include <post.h>
64#endif
56f94be3
WD
65#if defined(CONFIG_LOGBUFFER)
66#include <logbuff.h>
67#endif
42d1f039
WD
68#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
69#include <asm/cache.h>
70#endif
1c43771b
WD
71#ifdef CONFIG_PS2KBD
72#include <keyboard.h>
73#endif
fe8c2806 74
fa230445
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75#ifdef CFG_UPDATE_FLASH_SIZE
76extern int update_flash_size (int flash_size);
77#endif
78
9045f33c 79#if defined(CONFIG_SC3)
ca43ba18
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80extern void sc3_read_eeprom(void);
81#endif
82
7def6b34 83#if defined(CONFIG_CMD_DOC)
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84void doc_init (void);
85#endif
86#if defined(CONFIG_HARD_I2C) || \
87 defined(CONFIG_SOFT_I2C)
88#include <i2c.h>
89#endif
04a9e118
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90#if defined(CONFIG_HARD_SPI)
91#include <spi.h>
92#endif
7def6b34 93#if defined(CONFIG_CMD_NAND)
bedc4970
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94void nand_init (void);
95#endif
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96
97static char *failed = "*** failed ***\n";
98
17d704eb 99#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 100extern flash_info_t flash_info[];
17d704eb 101#endif
fe8c2806 102
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103#if defined(CONFIG_START_IDE)
104extern int board_start_ide(void);
105#endif
fe8c2806 106#include <environment.h>
d87080b7 107
bce84c4d 108DECLARE_GLOBAL_DATA_PTR;
fe8c2806 109
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110#if defined(CFG_ENV_IS_EMBEDDED)
111#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
112#elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
04a85b3b 113 (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
7e780369 114 defined(CFG_ENV_IS_IN_NVRAM)
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115#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
116#else
117#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
118#endif
119
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120extern ulong __init_end;
121extern ulong _end;
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122ulong monitor_flash_len;
123
7def6b34 124#if defined(CONFIG_CMD_BEDBUG)
8bde7f77
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125#include <bedbug/type.h>
126#endif
127
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128/*
129 * Begin and End of memory area for malloc(), and current "brk"
130 */
131static ulong mem_malloc_start = 0;
132static ulong mem_malloc_end = 0;
133static ulong mem_malloc_brk = 0;
134
135/************************************************************************
136 * Utilities *
137 ************************************************************************
138 */
139
140/*
141 * The Malloc area is immediately below the monitor copy in DRAM
142 */
143static void mem_malloc_init (void)
144{
e9514751
SR
145#if !defined(CONFIG_RELOC_FIXUP_WORKS)
146 mem_malloc_end = CFG_MONITOR_BASE + gd->reloc_off;
147#endif
148 mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
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149 mem_malloc_brk = mem_malloc_start;
150
151 memset ((void *) mem_malloc_start,
152 0,
153 mem_malloc_end - mem_malloc_start);
154}
155
156void *sbrk (ptrdiff_t increment)
157{
158 ulong old = mem_malloc_brk;
159 ulong new = old + increment;
160
161 if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
162 return (NULL);
163 }
164 mem_malloc_brk = new;
165 return ((void *) old);
166}
167
168char *strmhz (char *buf, long hz)
169{
170 long l, n;
171 long m;
172
173 n = hz / 1000000L;
174 l = sprintf (buf, "%ld", n);
175 m = (hz % 1000000L) / 1000L;
176 if (m != 0)
177 sprintf (buf + l, ".%03ld", m);
178 return (buf);
179}
180
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181/*
182 * All attempts to come up with a "common" initialization sequence
183 * that works for all boards and architectures failed: some of the
184 * requirements are just _too_ different. To get rid of the resulting
185 * mess of board dependend #ifdef'ed code we now make the whole
186 * initialization sequence configurable to the user.
187 *
188 * The requirements for any new initalization function is simple: it
189 * receives a pointer to the "global data" structure as it's only
190 * argument, and returns an integer return code, where 0 means
191 * "continue" and != 0 means "fatal error, hang the system".
192 */
193typedef int (init_fnc_t) (void);
194
195/************************************************************************
196 * Init Utilities *
197 ************************************************************************
198 * Some of this code should be moved into the core functions,
199 * but let's get it working (again) first...
200 */
201
202static int init_baudrate (void)
203{
77ddac94 204 char tmp[64]; /* long enough for environment variables */
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205 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
206
207 gd->baudrate = (i > 0)
208 ? (int) simple_strtoul (tmp, NULL, 10)
209 : CONFIG_BAUDRATE;
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210 return (0);
211}
212
213/***********************************************************************/
214
79f240f7
KP
215void __board_add_ram_info(int use_default)
216{
217 /* please define platform specific board_add_ram_info() */
218}
219void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
220
d96f41e0 221
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222static int init_func_ram (void)
223{
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224#ifdef CONFIG_BOARD_TYPES
225 int board_type = gd->board_type;
226#else
227 int board_type = 0; /* use dummy arg */
228#endif
229 puts ("DRAM: ");
230
231 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 232 print_size (gd->ram_size, "");
d96f41e0 233 board_add_ram_info(0);
d96f41e0 234 putc('\n');
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235 return (0);
236 }
237 puts (failed);
238 return (1);
239}
240
241/***********************************************************************/
242
243#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
244static int init_func_i2c (void)
245{
246 puts ("I2C: ");
247 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
248 puts ("ready\n");
249 return (0);
250}
251#endif
252
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253#if defined(CONFIG_HARD_SPI)
254static int init_func_spi (void)
255{
256 puts ("SPI: ");
257 spi_init ();
258 puts ("ready\n");
259 return (0);
260}
261#endif
262
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263/***********************************************************************/
264
265#if defined(CONFIG_WATCHDOG)
266static int init_func_watchdog_init (void)
267{
268 puts (" Watchdog enabled\n");
269 WATCHDOG_RESET ();
270 return (0);
271}
272# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
273
274static int init_func_watchdog_reset (void)
275{
276 WATCHDOG_RESET ();
277 return (0);
278}
279# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
280#else
281# define INIT_FUNC_WATCHDOG_INIT /* undef */
282# define INIT_FUNC_WATCHDOG_RESET /* undef */
283#endif /* CONFIG_WATCHDOG */
284
285/************************************************************************
286 * Initialization sequence *
287 ************************************************************************
288 */
289
290init_fnc_t *init_sequence[] = {
291
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292#if defined(CONFIG_BOARD_EARLY_INIT_F)
293 board_early_init_f,
fe8c2806 294#endif
c178d3da 295
66ca92a5 296#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 297 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
298#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
299 && !defined(CONFIG_TQM885D)
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WD
300 adjust_sdram_tbs_8xx,
301#endif
fe8c2806 302 init_timebase,
c178d3da 303#endif
fe8c2806 304#ifdef CFG_ALLOC_DPRAM
9c4c5ae3 305#if !defined(CONFIG_CPM2)
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306 dpram_init,
307#endif
7aa78614 308#endif
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309#if defined(CONFIG_BOARD_POSTCLK_INIT)
310 board_postclk_init,
311#endif
312 env_init,
66ca92a5 313#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
c178d3da
WD
314 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
315 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
316 init_timebase,
317#endif
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WD
318 init_baudrate,
319 serial_init,
320 console_init_f,
321 display_options,
322#if defined(CONFIG_8260)
323 prt_8260_rsr,
324 prt_8260_clks,
325#endif /* CONFIG_8260 */
9be39a67
DL
326#if defined(CONFIG_MPC83XX)
327 prt_83xx_rsr,
328#endif
fe8c2806 329 checkcpu,
cbd8a35c 330#if defined(CONFIG_MPC5xxx)
945af8d7 331 prt_mpc5xxx_clks,
cbd8a35c 332#endif /* CONFIG_MPC5xxx */
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WD
333#if defined(CONFIG_MPC8220)
334 prt_mpc8220_clks,
335#endif
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336 checkboard,
337 INIT_FUNC_WATCHDOG_INIT
c837dcb1 338#if defined(CONFIG_MISC_INIT_F)
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339 misc_init_f,
340#endif
341 INIT_FUNC_WATCHDOG_RESET
342#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
343 init_func_i2c,
344#endif
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345#if defined(CONFIG_HARD_SPI)
346 init_func_spi,
347#endif
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348#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
349 dtt_init,
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WD
350#endif
351#ifdef CONFIG_POST
352 post_init_f,
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WD
353#endif
354 INIT_FUNC_WATCHDOG_RESET
355 init_func_ram,
356#if defined(CFG_DRAM_TEST)
357 testdram,
358#endif /* CFG_DRAM_TEST */
359 INIT_FUNC_WATCHDOG_RESET
360
361 NULL, /* Terminate this list */
362};
363
364/************************************************************************
365 *
366 * This is the first part of the initialization sequence that is
367 * implemented in C, but still running from ROM.
368 *
369 * The main purpose is to provide a (serial) console interface as
370 * soon as possible (so we can see any error messages), and to
371 * initialize the RAM so that we can relocate the monitor code to
372 * RAM.
373 *
374 * Be aware of the restrictions: global data is read-only, BSS is not
375 * initialized, and stack space is limited to a few kB.
376 *
377 ************************************************************************
378 */
379
380void board_init_f (ulong bootflag)
381{
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WD
382 bd_t *bd;
383 ulong len, addr, addr_sp;
7bc5ee07 384 ulong *s;
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385 gd_t *id;
386 init_fnc_t **init_fnc_ptr;
387#ifdef CONFIG_PRAM
388 int i;
389 ulong reg;
390 uchar tmp[64]; /* long enough for environment variables */
391#endif
392
393 /* Pointer is writable since we allocated a register for it */
394 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
93f6a677
WD
395 /* compiler optimization barrier needed for GCC >= 3.4 */
396 __asm__ __volatile__("": : :"memory");
fe8c2806 397
9be39a67 398#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX)
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WD
399 /* Clear initial global data */
400 memset ((void *) gd, 0, sizeof (gd_t));
401#endif
402
403 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
404 if ((*init_fnc_ptr) () != 0) {
405 hang ();
406 }
407 }
408
409 /*
410 * Now that we have DRAM mapped and working, we can
411 * relocate the code and continue running from DRAM.
412 *
413 * Reserve memory at end of RAM for (top down in that order):
8bde7f77 414 * - kernel log buffer
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WD
415 * - protected RAM
416 * - LCD framebuffer
417 * - monitor code
418 * - board info struct
419 */
3b57fe0a 420 len = (ulong)&_end - CFG_MONITOR_BASE;
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WD
421
422#ifndef CONFIG_VERY_BIG_RAM
423 addr = CFG_SDRAM_BASE + gd->ram_size;
424#else
425 /* only allow stack below 256M */
426 addr = CFG_SDRAM_BASE +
427 (gd->ram_size > 256 << 20) ? 256 << 20 : gd->ram_size;
428#endif
429
228f29ac
WD
430#ifdef CONFIG_LOGBUFFER
431 /* reserve kernel log buffer */
432 addr -= (LOGBUFF_RESERVE);
9d2b18a0 433 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac
WD
434#endif
435
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WD
436#ifdef CONFIG_PRAM
437 /*
438 * reserve protected RAM
439 */
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WD
440 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
441 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 442 addr -= (reg << 10); /* size is in kB */
9d2b18a0 443 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
fe8c2806
WD
444#endif /* CONFIG_PRAM */
445
446 /* round down to next 4 kB limit */
447 addr &= ~(4096 - 1);
9d2b18a0 448 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
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WD
449
450#ifdef CONFIG_LCD
451 /* reserve memory for LCD display (always full pages) */
452 addr = lcd_setmem (addr);
453 gd->fb_base = addr;
454#endif /* CONFIG_LCD */
455
456#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
457 /* reserve memory for video display (always full pages) */
458 addr = video_setmem (addr);
459 gd->fb_base = addr;
460#endif /* CONFIG_VIDEO */
461
462 /*
463 * reserve memory for U-Boot code, data & bss
682011ff 464 * round down to next 4 kB limit
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WD
465 */
466 addr -= len;
682011ff 467 addr &= ~(4096 - 1);
7d314992
WD
468#ifdef CONFIG_E500
469 /* round down to next 64 kB limit so that IVPR stays aligned */
470 addr &= ~(65536 - 1);
471#endif
fe8c2806 472
9d2b18a0 473 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 474
c7de829c
WD
475#ifdef CONFIG_AMIGAONEG3SE
476 gd->relocaddr = addr;
477#endif
478
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479 /*
480 * reserve memory for malloc() arena
481 */
482 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 483 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 484 TOTAL_MALLOC_LEN >> 10, addr_sp);
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WD
485
486 /*
487 * (permanently) allocate a Board Info struct
488 * and a permanent copy of the "global" data
489 */
490 addr_sp -= sizeof (bd_t);
491 bd = (bd_t *) addr_sp;
492 gd->bd = bd;
9d2b18a0 493 debug ("Reserving %d Bytes for Board Info at: %08lx\n",
fe8c2806 494 sizeof (bd_t), addr_sp);
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WD
495 addr_sp -= sizeof (gd_t);
496 id = (gd_t *) addr_sp;
9d2b18a0 497 debug ("Reserving %d Bytes for Global Data at: %08lx\n",
fe8c2806 498 sizeof (gd_t), addr_sp);
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WD
499
500 /*
501 * Finally, we set up a new (bigger) stack.
502 *
503 * Leave some safety gap for SP, force alignment on 16 byte boundary
504 * Clear initial stack frame
505 */
506 addr_sp -= 16;
507 addr_sp &= ~0xF;
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WD
508 s = (ulong *)addr_sp;
509 *s-- = 0;
510 *s-- = 0;
511 addr_sp = (ulong)s;
9d2b18a0 512 debug ("Stack Pointer at: %08lx\n", addr_sp);
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WD
513
514 /*
515 * Save local variables to board info struct
516 */
517
c837dcb1 518 bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
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519 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
520
521#ifdef CONFIG_IP860
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522 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
523 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
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WD
524#elif defined CONFIG_MPC8220
525 bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */
526 bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 527#else
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528 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
529 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
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WD
530#endif
531
42d1f039 532#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 533 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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534 bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
535#endif
cbd8a35c 536#if defined(CONFIG_MPC5xxx)
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WD
537 bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
538#endif
f046ccd1 539#if defined(CONFIG_MPC83XX)
d239d74b 540 bd->bi_immrbar = CFG_IMMR;
f046ccd1 541#endif
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WD
542#if defined(CONFIG_MPC8220)
543 bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
544 bd->bi_inpfreq = gd->inp_clk;
545 bd->bi_pcifreq = gd->pci_clk;
546 bd->bi_vcofreq = gd->vco_clk;
547 bd->bi_pevfreq = gd->pev_clk;
548 bd->bi_flbfreq = gd->flb_clk;
549
dd520bf3
WD
550 /* store bootparam to sram (backward compatible), here? */
551 {
552 u32 *sram = (u32 *)CFG_SRAM_BASE;
553 *sram++ = gd->ram_size;
554 *sram++ = gd->bus_clk;
555 *sram++ = gd->inp_clk;
556 *sram++ = gd->cpu_clk;
557 *sram++ = gd->vco_clk;
558 *sram++ = gd->flb_clk;
559 *sram++ = 0xb8c3ba11; /* boot signature */
560 }
983fda83 561#endif
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WD
562
563 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
564
565 WATCHDOG_RESET ();
566 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
567 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 568#if defined(CONFIG_CPM2)
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WD
569 bd->bi_cpmfreq = gd->cpm_clk;
570 bd->bi_brgfreq = gd->brg_clk;
571 bd->bi_sccfreq = gd->scc_clk;
572 bd->bi_vco = gd->vco_out;
9c4c5ae3 573#endif /* CONFIG_CPM2 */
281ff9a4 574#if defined(CONFIG_MPC512X)
5d49e0e1 575 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 576#endif /* CONFIG_MPC512X */
cbd8a35c 577#if defined(CONFIG_MPC5xxx)
945af8d7
WD
578 bd->bi_ipbfreq = gd->ipb_clk;
579 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 580#endif /* CONFIG_MPC5xxx */
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WD
581 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
582
583#ifdef CFG_EXTBDINFO
77ddac94
WD
584 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
585 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
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WD
586
587 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
588 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
589#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
590 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
591 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 592 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 593 bd->bi_opbfreq = get_OPB_freq ();
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WD
594#elif defined(CONFIG_XILINX_ML300)
595 bd->bi_pci_busfreq = get_PCI_freq ();
fe8c2806
WD
596#endif
597#endif
598
9d2b18a0 599 debug ("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806
WD
600
601 WATCHDOG_RESET ();
602
603#ifdef CONFIG_POST
604 post_bootmode_init();
6dff5529 605 post_run (NULL, POST_ROM | post_bootmode_get(0));
fe8c2806
WD
606#endif
607
608 WATCHDOG_RESET();
609
27b207fd 610 memcpy (id, (void *)gd, sizeof (gd_t));
fe8c2806
WD
611
612 relocate_code (addr_sp, id, addr);
613
614 /* NOTREACHED - relocate_code() does not return */
615}
616
fe8c2806
WD
617/************************************************************************
618 *
619 * This is the next part if the initialization sequence: we are now
620 * running from RAM and have a "normal" C environment, i. e. global
621 * data can be written, BSS has been cleared, the stack size in not
622 * that critical any more, etc.
623 *
624 ************************************************************************
625 */
fe8c2806
WD
626void board_init_r (gd_t *id, ulong dest_addr)
627{
fe8c2806
WD
628 cmd_tbl_t *cmdtp;
629 char *s, *e;
630 bd_t *bd;
631 int i;
632 extern void malloc_bin_reloc (void);
633#ifndef CFG_ENV_IS_NOWHERE
634 extern char * env_name_spec;
635#endif
636
637#ifndef CFG_NO_FLASH
638 ulong flash_size;
639#endif
640
641 gd = id; /* initialize RAM version of global data */
642 bd = gd->bd;
643
644 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63
GL
645
646#if defined(CONFIG_RELOC_FIXUP_WORKS)
647 gd->reloc_off = 0;
e9514751 648 mem_malloc_end = dest_addr;
f82b3b63 649#else
bb105f24 650 gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
f82b3b63 651#endif
bb105f24
MB
652
653#ifdef CONFIG_SERIAL_MULTI
654 serial_initialize();
655#endif
fe8c2806 656
9d2b18a0 657 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806
WD
658
659 WATCHDOG_RESET ();
660
c837dcb1
WD
661#if defined(CONFIG_BOARD_EARLY_INIT_R)
662 board_early_init_r ();
663#endif
664
3b57fe0a 665 monitor_flash_len = (ulong)&__init_end - dest_addr;
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WD
666
667 /*
668 * We have to relocate the command table manually
669 */
8bde7f77 670 for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
fe8c2806 671 ulong addr;
fe8c2806
WD
672 addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
673#if 0
674 printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
675 cmdtp->name, (ulong) (cmdtp->cmd), addr);
676#endif
677 cmdtp->cmd =
678 (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
679
680 addr = (ulong)(cmdtp->name) + gd->reloc_off;
681 cmdtp->name = (char *)addr;
682
683 if (cmdtp->usage) {
684 addr = (ulong)(cmdtp->usage) + gd->reloc_off;
685 cmdtp->usage = (char *)addr;
686 }
687#ifdef CFG_LONGHELP
688 if (cmdtp->help) {
689 addr = (ulong)(cmdtp->help) + gd->reloc_off;
690 cmdtp->help = (char *)addr;
691 }
692#endif
693 }
694 /* there are some other pointer constants we must deal with */
695#ifndef CFG_ENV_IS_NOWHERE
696 env_name_spec += gd->reloc_off;
697#endif
698
699 WATCHDOG_RESET ();
700
56f94be3 701#ifdef CONFIG_LOGBUFFER
228f29ac 702 logbuff_init_ptrs ();
56f94be3 703#endif
fe8c2806 704#ifdef CONFIG_POST
228f29ac 705 post_output_backlog ();
fe8c2806
WD
706 post_reloc ();
707#endif
708
709 WATCHDOG_RESET();
710
2688e2f9
KG
711#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
712 defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
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WD
713 icache_enable (); /* it's time to enable the instruction cache */
714#endif
715
1c8f6d8f 716#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
c837dcb1 717 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
718#endif
719
3bac3513 720#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 721 /*
3bac3513
WD
722 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
723 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
724 * bridge there.
fe8c2806
WD
725 */
726 pci_init ();
3bac3513
WD
727#endif
728#if defined(CONFIG_BAB7xx)
fe8c2806
WD
729 /*
730 * Initialise the ISA bridge
731 */
732 initialise_w83c553f ();
733#endif
734
735 asm ("sync ; isync");
736
737 /*
738 * Setup trap handlers
739 */
740 trap_init (dest_addr);
741
742#if !defined(CFG_NO_FLASH)
743 puts ("FLASH: ");
744
745 if ((flash_size = flash_init ()) > 0) {
0cb61d7d 746# ifdef CFG_FLASH_CHECKSUM
fe8c2806
WD
747 print_size (flash_size, "");
748 /*
749 * Compute and print flash CRC if flashchecksum is set to 'y'
750 *
751 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
752 */
753 s = getenv ("flashchecksum");
754 if (s && (*s == 'y')) {
755 printf (" CRC: %08lX",
7e780369
WD
756 crc32 (0, (const unsigned char *) CFG_FLASH_BASE, flash_size)
757 );
fe8c2806
WD
758 }
759 putc ('\n');
0cb61d7d 760# else /* !CFG_FLASH_CHECKSUM */
fe8c2806 761 print_size (flash_size, "\n");
0cb61d7d 762# endif /* CFG_FLASH_CHECKSUM */
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WD
763 } else {
764 puts (failed);
765 hang ();
766 }
767
768 bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
769 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445
HS
770
771#if defined(CFG_UPDATE_FLASH_SIZE)
772 /* Make a update of the Memctrl. */
773 update_flash_size (flash_size);
774#endif
775
776
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WD
777# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
778 /* flash mapped at end of memory map */
779 bd->bi_flashoffset = TEXT_BASE + flash_size;
0cb61d7d 780# elif CFG_MONITOR_BASE == CFG_FLASH_BASE
3b57fe0a 781 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 782# else
fe8c2806 783 bd->bi_flashoffset = 0;
0cb61d7d
WD
784# endif
785#else /* CFG_NO_FLASH */
fe8c2806
WD
786
787 bd->bi_flashsize = 0;
788 bd->bi_flashstart = 0;
789 bd->bi_flashoffset = 0;
790#endif /* !CFG_NO_FLASH */
791
792 WATCHDOG_RESET ();
793
794 /* initialize higher level parts of CPU like time base and timers */
795 cpu_init_r ();
796
797 WATCHDOG_RESET ();
798
799 /* initialize malloc() area */
800 mem_malloc_init ();
801 malloc_bin_reloc ();
802
803#ifdef CONFIG_SPI
804# if !defined(CFG_ENV_IS_IN_EEPROM)
805 spi_init_f ();
806# endif
807 spi_init_r ();
808#endif
809
7def6b34 810#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
811 WATCHDOG_RESET ();
812 puts ("NAND: ");
813 nand_init(); /* go init the NAND */
814#endif
815
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WD
816 /* relocate environment function pointers etc. */
817 env_relocate ();
818
819 /*
820 * Fill in missing fields of bd_info.
8bde7f77
WD
821 * We do this here, where we have "normal" access to the
822 * environment; we used to do this still running from ROM,
823 * where had to use getenv_r(), which can be pretty slow when
824 * the environment is in EEPROM.
fe8c2806 825 */
7abf0c58
WD
826
827#if defined(CFG_EXTBDINFO)
828#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
829#if defined(CONFIG_I2CFAST)
830 /*
831 * set bi_iic_fast for linux taking environment variable
832 * "i2cfast" into account
833 */
834 {
835 char *s = getenv ("i2cfast");
836 if (s && ((*s == 'y') || (*s == 'Y'))) {
837 bd->bi_iic_fast[0] = 1;
838 bd->bi_iic_fast[1] = 1;
839 } else {
840 bd->bi_iic_fast[0] = 0;
841 bd->bi_iic_fast[1] = 0;
842 }
843 }
844#else
845 bd->bi_iic_fast[0] = 0;
846 bd->bi_iic_fast[1] = 0;
847#endif /* CONFIG_I2CFAST */
848#endif /* CONFIG_405GP, CONFIG_405EP */
849#endif /* CFG_EXTBDINFO */
850
9045f33c 851#if defined(CONFIG_SC3)
ca43ba18
HS
852 sc3_read_eeprom();
853#endif
d59feffb
HW
854
855#ifdef CFG_ID_EEPROM
856 mac_read_from_eeprom();
857#endif
858
fe8c2806 859 s = getenv ("ethaddr");
4707fb50
BS
860#if defined (CONFIG_MBX) || \
861 defined (CONFIG_RPXCLASSIC) || \
862 defined(CONFIG_IAD210) || \
863 defined(CONFIG_V38B)
fe8c2806
WD
864 if (s == NULL)
865 board_get_enetaddr (bd->bi_enetaddr);
866 else
867#endif
868 for (i = 0; i < 6; ++i) {
869 bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
870 if (s)
871 s = (*e) ? e + 1 : e;
872 }
873#ifdef CONFIG_HERMES
874 if ((gd->board_type >> 16) == 2)
875 bd->bi_ethspeed = gd->board_type & 0xFFFF;
876 else
877 bd->bi_ethspeed = 0xFFFF;
878#endif
879
880#ifdef CONFIG_NX823
881 load_sernum_ethaddr ();
882#endif
883
e2ffd59b 884#ifdef CONFIG_HAS_ETH1
fe8c2806
WD
885 /* handle the 2nd ethernet address */
886
887 s = getenv ("eth1addr");
888
889 for (i = 0; i < 6; ++i) {
890 bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
891 if (s)
892 s = (*e) ? e + 1 : e;
893 }
894#endif
e2ffd59b 895#ifdef CONFIG_HAS_ETH2
fe8c2806
WD
896 /* handle the 3rd ethernet address */
897
898 s = getenv ("eth2addr");
b79316f2 899#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
900 if (s == NULL)
901 board_get_enetaddr(bd->bi_enet2addr);
902 else
903#endif
fe8c2806
WD
904 for (i = 0; i < 6; ++i) {
905 bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
906 if (s)
907 s = (*e) ? e + 1 : e;
908 }
909#endif
910
e2ffd59b 911#ifdef CONFIG_HAS_ETH3
ba56f625
WD
912 /* handle 4th ethernet address */
913 s = getenv("eth3addr");
b79316f2 914#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
915 if (s == NULL)
916 board_get_enetaddr(bd->bi_enet3addr);
917 else
918#endif
919 for (i = 0; i < 6; ++i) {
920 bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
921 if (s)
922 s = (*e) ? e + 1 : e;
923 }
924#endif
fe8c2806
WD
925
926#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
fa230445 927 defined(CONFIG_TQM8272) || \
566a494f
HS
928 defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \
929 defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP)
fe8c2806
WD
930 load_sernum_ethaddr ();
931#endif
932 /* IP Address */
933 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
934
935 WATCHDOG_RESET ();
936
979bdbc7 937#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
938 /*
939 * Do pci configuration
940 */
941 pci_init ();
942#endif
943
944/** leave this here (after malloc(), environment and PCI are working) **/
945 /* Initialize devices */
946 devices_init ();
947
27b207fd
WD
948 /* Initialize the jump table for applications */
949 jumptable_init ();
fe8c2806 950
500856eb
RJ
951#if defined(CONFIG_API)
952 /* Initialize API */
953 api_init ();
954#endif
955
fe8c2806
WD
956 /* Initialize the console (after the relocation and devices init) */
957 console_init_r ();
fe8c2806
WD
958
959#if defined(CONFIG_CCM) || \
960 defined(CONFIG_COGENT) || \
961 defined(CONFIG_CPCI405) || \
962 defined(CONFIG_EVB64260) || \
56f94be3 963 defined(CONFIG_KUP4K) || \
0608e04d 964 defined(CONFIG_KUP4X) || \
fe8c2806
WD
965 defined(CONFIG_LWMON) || \
966 defined(CONFIG_PCU_E) || \
9045f33c 967 defined(CONFIG_SC3) || \
fe8c2806
WD
968 defined(CONFIG_W7O) || \
969 defined(CONFIG_MISC_INIT_R)
970 /* miscellaneous platform dependent initialisations */
971 misc_init_r ();
972#endif
973
974#ifdef CONFIG_HERMES
975 if (bd->bi_ethspeed != 0xFFFF)
976 hermes_start_lxt980 ((int) bd->bi_ethspeed);
977#endif
978
7def6b34 979#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
980 WATCHDOG_RESET ();
981 puts ("KGDB: ");
982 kgdb_init ();
983#endif
984
9d2b18a0 985 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
986
987 /*
988 * Enable Interrupts
989 */
990 interrupt_init ();
991
992 /* Must happen after interrupts are initialized since
993 * an irq handler gets installed
994 */
42dfe7a1 995#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
996 serial_buffered_init();
997#endif
998
566a494f 999#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
1000 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
1001#endif
1002
1003 udelay (20);
1004
1005 set_timer (0);
1006
fe8c2806
WD
1007 /* Initialize from environment */
1008 if ((s = getenv ("loadaddr")) != NULL) {
1009 load_addr = simple_strtoul (s, NULL, 16);
1010 }
7def6b34 1011#if defined(CONFIG_CMD_NET)
fe8c2806
WD
1012 if ((s = getenv ("bootfile")) != NULL) {
1013 copy_filename (BootFile, s, sizeof (BootFile));
1014 }
b3aff0cb 1015#endif
fe8c2806
WD
1016
1017 WATCHDOG_RESET ();
1018
7def6b34 1019#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
1020 WATCHDOG_RESET ();
1021 puts ("SCSI: ");
1022 scsi_init ();
1023#endif
1024
7def6b34 1025#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
1026 WATCHDOG_RESET ();
1027 puts ("DOC: ");
1028 doc_init ();
1029#endif
1030
7def6b34 1031#if defined(CONFIG_CMD_NET)
63ff004c 1032#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
1033 WATCHDOG_RESET ();
1034 puts ("Net: ");
63ff004c 1035#endif
fe8c2806
WD
1036 eth_initialize (bd);
1037#endif
1038
7def6b34 1039#if defined(CONFIG_CMD_NET) && ( \
63ff004c
MB
1040 defined(CONFIG_CCM) || \
1041 defined(CONFIG_ELPT860) || \
1042 defined(CONFIG_EP8260) || \
1043 defined(CONFIG_IP860) || \
1044 defined(CONFIG_IVML24) || \
1045 defined(CONFIG_IVMS8) || \
1046 defined(CONFIG_MPC8260ADS) || \
1047 defined(CONFIG_MPC8266ADS) || \
1048 defined(CONFIG_MPC8560ADS) || \
1049 defined(CONFIG_PCU_E) || \
1050 defined(CONFIG_RPXSUPER) || \
1051 defined(CONFIG_STXGP3) || \
1052 defined(CONFIG_SPD823TS) || \
1053 defined(CONFIG_RESET_PHY_R) )
1054
1055 WATCHDOG_RESET ();
1056 debug ("Reset Ethernet PHY\n");
1057 reset_phy ();
1058#endif
1059
fe8c2806 1060#ifdef CONFIG_POST
6dff5529 1061 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
1062#endif
1063
7def6b34
JL
1064#if defined(CONFIG_CMD_PCMCIA) \
1065 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
1066 WATCHDOG_RESET ();
1067 puts ("PCMCIA:");
1068 pcmcia_init ();
1069#endif
1070
7def6b34 1071#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
1072 WATCHDOG_RESET ();
1073# ifdef CONFIG_IDE_8xx_PCCARD
1074 puts ("PCMCIA:");
1075# else
1076 puts ("IDE: ");
1077#endif
ca43ba18
HS
1078#if defined(CONFIG_START_IDE)
1079 if (board_start_ide())
1080 ide_init ();
1081#else
fe8c2806 1082 ide_init ();
ca43ba18 1083#endif
b3aff0cb 1084#endif
fe8c2806
WD
1085
1086#ifdef CONFIG_LAST_STAGE_INIT
1087 WATCHDOG_RESET ();
1088 /*
1089 * Some parts can be only initialized if all others (like
1090 * Interrupts) are up and running (i.e. the PC-style ISA
1091 * keyboard).
1092 */
1093 last_stage_init ();
1094#endif
1095
7def6b34 1096#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1097 WATCHDOG_RESET ();
1098 bedbug_init ();
1099#endif
1100
228f29ac 1101#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1102 /*
1103 * Export available size of memory for Linux,
1104 * taking into account the protected RAM at top of memory
1105 */
1106 {
1107 ulong pram;
fe8c2806 1108 uchar memsz[32];
228f29ac
WD
1109#ifdef CONFIG_PRAM
1110 char *s;
fe8c2806
WD
1111
1112 if ((s = getenv ("pram")) != NULL) {
1113 pram = simple_strtoul (s, NULL, 10);
1114 } else {
1115 pram = CONFIG_PRAM;
1116 }
228f29ac
WD
1117#else
1118 pram=0;
1119#endif
1120#ifdef CONFIG_LOGBUFFER
1121 /* Also take the logbuffer into account (pram is in kB) */
1122 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
1123#endif
77ddac94
WD
1124 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1125 setenv ("mem", (char *)memsz);
fe8c2806
WD
1126 }
1127#endif
1128
1c43771b
WD
1129#ifdef CONFIG_PS2KBD
1130 puts ("PS/2: ");
1131 kbd_init();
1132#endif
1133
4532cb69
WD
1134#ifdef CONFIG_MODEM_SUPPORT
1135 {
1136 extern int do_mdm_init;
1137 do_mdm_init = gd->do_mdm_init;
1138 }
1139#endif
1140
fe8c2806
WD
1141 /* Initialization complete - start the monitor */
1142
1143 /* main_loop() can return to retry autoboot, if so just run it again. */
1144 for (;;) {
1145 WATCHDOG_RESET ();
1146 main_loop ();
1147 }
1148
1149 /* NOTREACHED - no way out of command loop except booting */
1150}
1151
1152void hang (void)
1153{
1154 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1155 show_boot_progress(-30);
fe8c2806
WD
1156 for (;;);
1157}
1158
4532cb69
WD
1159#ifdef CONFIG_MODEM_SUPPORT
1160/* called from main loop (common/main.c) */
77ddac94
WD
1161/* 'inline' - We have to do it fast */
1162static inline void mdm_readline(char *buf, int bufsiz)
1163{
1164 char c;
1165 char *p;
1166 int n;
1167
1168 n = 0;
1169 p = buf;
1170 for(;;) {
1171 c = serial_getc();
1172
1173 /* dbg("(%c)", c); */
1174
1175 switch(c) {
1176 case '\r':
1177 break;
1178 case '\n':
1179 *p = '\0';
1180 return;
1181
1182 default:
1183 if(n++ > bufsiz) {
1184 *p = '\0';
1185 return; /* sanity check */
1186 }
1187 *p = c;
1188 p++;
1189 break;
1190 }
1191 }
1192}
1193
4532cb69
WD
1194extern void dbg(const char *fmt, ...);
1195int mdm_init (void)
1196{
1197 char env_str[16];
1198 char *init_str;
1199 int i;
1200 extern char console_buffer[];
4532cb69
WD
1201 extern void enable_putc(void);
1202 extern int hwflow_onoff(int);
1203
1204 enable_putc(); /* enable serial_putc() */
1205
1206#ifdef CONFIG_HWFLOW
1207 init_str = getenv("mdm_flow_control");
1208 if (init_str && (strcmp(init_str, "rts/cts") == 0))
1209 hwflow_onoff (1);
1210 else
1211 hwflow_onoff(-1);
1212#endif
1213
1214 for (i = 1;;i++) {
1215 sprintf(env_str, "mdm_init%d", i);
1216 if ((init_str = getenv(env_str)) != NULL) {
1217 serial_puts(init_str);
1218 serial_puts("\n");
1219 for(;;) {
1220 mdm_readline(console_buffer, CFG_CBSIZE);
1221 dbg("ini%d: [%s]", i, console_buffer);
1222
1223 if ((strcmp(console_buffer, "OK") == 0) ||
1224 (strcmp(console_buffer, "ERROR") == 0)) {
1225 dbg("ini%d: cmd done", i);
1226 break;
1227 } else /* in case we are originating call ... */
1228 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1229 dbg("ini%d: connect", i);
1230 return 0;
1231 }
1232 }
1233 } else
1234 break; /* no init string - stop modem init */
1235
1236 udelay(100000);
1237 }
1238
1239 udelay(100000);
1240
1241 /* final stage - wait for connect */
1242 for(;i > 1;) { /* if 'i' > 1 - wait for connection
1243 message from modem */
1244 mdm_readline(console_buffer, CFG_CBSIZE);
1245 dbg("ini_f: [%s]", console_buffer);
1246 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1247 dbg("ini_f: connected");
1248 return 0;
1249 }
1250 }
1251
1252 return 0;
1253}
1254
4532cb69
WD
1255#endif
1256
fe8c2806
WD
1257#if 0 /* We could use plain global data, but the resulting code is bigger */
1258/*
1259 * Pointer to initial global data area
1260 *
1261 * Here we initialize it.
1262 */
1263#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1264#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
1265DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
1266#endif /* 0 */
1267
1268/************************************************************************/