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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
28#include <devices.h>
fe8c2806
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
WD
32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
WD
36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
fe8c2806
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39#include <ide.h>
40#endif
cd54081c
DL
41#if defined(CONFIG_CMD_SATA)
42#include <sata.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_SCSI)
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45#include <scsi.h>
46#endif
7def6b34 47#if defined(CONFIG_CMD_KGDB)
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48#include <kgdb.h>
49#endif
50#ifdef CONFIG_STATUS_LED
51#include <status_led.h>
52#endif
53#include <net.h>
281e00a3 54#include <serial.h>
fe8c2806 55#ifdef CFG_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
fe8c2806
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57#include <commproc.h>
58#endif
7aa78614 59#endif
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
56f94be3
WD
68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
42d1f039
WD
71#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
72#include <asm/cache.h>
73#endif
1c43771b
WD
74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
fa230445
HS
78#ifdef CFG_UPDATE_FLASH_SIZE
79extern int update_flash_size (int flash_size);
80#endif
81
9045f33c 82#if defined(CONFIG_SC3)
ca43ba18
HS
83extern void sc3_read_eeprom(void);
84#endif
85
7def6b34 86#if defined(CONFIG_CMD_DOC)
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87void doc_init (void);
88#endif
89#if defined(CONFIG_HARD_I2C) || \
90 defined(CONFIG_SOFT_I2C)
91#include <i2c.h>
92#endif
04a9e118
BW
93#if defined(CONFIG_HARD_SPI)
94#include <spi.h>
95#endif
d6ac2ed8 96#include <nand.h>
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97
98static char *failed = "*** failed ***\n";
99
17d704eb 100#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 101extern flash_info_t flash_info[];
17d704eb 102#endif
fe8c2806 103
ca43ba18
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104#if defined(CONFIG_START_IDE)
105extern int board_start_ide(void);
106#endif
fe8c2806 107#include <environment.h>
d87080b7 108
bce84c4d 109DECLARE_GLOBAL_DATA_PTR;
fe8c2806 110
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WD
111#if defined(CFG_ENV_IS_EMBEDDED)
112#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
113#elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
04a85b3b 114 (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
7e780369 115 defined(CFG_ENV_IS_IN_NVRAM)
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116#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
117#else
118#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
119#endif
120
6fb4b640
SR
121#if !defined(CFG_MEM_TOP_HIDE)
122#define CFG_MEM_TOP_HIDE 0
123#endif
124
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WD
125extern ulong __init_end;
126extern ulong _end;
3b57fe0a
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127ulong monitor_flash_len;
128
7def6b34 129#if defined(CONFIG_CMD_BEDBUG)
8bde7f77
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130#include <bedbug/type.h>
131#endif
132
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133/*
134 * Begin and End of memory area for malloc(), and current "brk"
135 */
136static ulong mem_malloc_start = 0;
137static ulong mem_malloc_end = 0;
138static ulong mem_malloc_brk = 0;
139
140/************************************************************************
141 * Utilities *
142 ************************************************************************
143 */
144
145/*
146 * The Malloc area is immediately below the monitor copy in DRAM
147 */
148static void mem_malloc_init (void)
149{
e9514751
SR
150#if !defined(CONFIG_RELOC_FIXUP_WORKS)
151 mem_malloc_end = CFG_MONITOR_BASE + gd->reloc_off;
152#endif
153 mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
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154 mem_malloc_brk = mem_malloc_start;
155
156 memset ((void *) mem_malloc_start,
157 0,
158 mem_malloc_end - mem_malloc_start);
159}
160
161void *sbrk (ptrdiff_t increment)
162{
163 ulong old = mem_malloc_brk;
164 ulong new = old + increment;
165
166 if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
167 return (NULL);
168 }
169 mem_malloc_brk = new;
170 return ((void *) old);
171}
172
173char *strmhz (char *buf, long hz)
174{
175 long l, n;
176 long m;
177
178 n = hz / 1000000L;
179 l = sprintf (buf, "%ld", n);
180 m = (hz % 1000000L) / 1000L;
181 if (m != 0)
182 sprintf (buf + l, ".%03ld", m);
183 return (buf);
184}
185
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WD
186/*
187 * All attempts to come up with a "common" initialization sequence
188 * that works for all boards and architectures failed: some of the
189 * requirements are just _too_ different. To get rid of the resulting
190 * mess of board dependend #ifdef'ed code we now make the whole
191 * initialization sequence configurable to the user.
192 *
193 * The requirements for any new initalization function is simple: it
194 * receives a pointer to the "global data" structure as it's only
195 * argument, and returns an integer return code, where 0 means
196 * "continue" and != 0 means "fatal error, hang the system".
197 */
198typedef int (init_fnc_t) (void);
199
200/************************************************************************
201 * Init Utilities *
202 ************************************************************************
203 * Some of this code should be moved into the core functions,
204 * but let's get it working (again) first...
205 */
206
207static int init_baudrate (void)
208{
77ddac94 209 char tmp[64]; /* long enough for environment variables */
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210 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
211
212 gd->baudrate = (i > 0)
213 ? (int) simple_strtoul (tmp, NULL, 10)
214 : CONFIG_BAUDRATE;
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215 return (0);
216}
217
218/***********************************************************************/
219
79f240f7
KP
220void __board_add_ram_info(int use_default)
221{
222 /* please define platform specific board_add_ram_info() */
223}
224void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
225
d96f41e0 226
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227static int init_func_ram (void)
228{
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WD
229#ifdef CONFIG_BOARD_TYPES
230 int board_type = gd->board_type;
231#else
232 int board_type = 0; /* use dummy arg */
233#endif
234 puts ("DRAM: ");
235
236 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 237 print_size (gd->ram_size, "");
d96f41e0 238 board_add_ram_info(0);
d96f41e0 239 putc('\n');
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WD
240 return (0);
241 }
242 puts (failed);
243 return (1);
244}
245
246/***********************************************************************/
247
248#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
249static int init_func_i2c (void)
250{
251 puts ("I2C: ");
252 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
253 puts ("ready\n");
254 return (0);
255}
256#endif
257
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258#if defined(CONFIG_HARD_SPI)
259static int init_func_spi (void)
260{
261 puts ("SPI: ");
262 spi_init ();
263 puts ("ready\n");
264 return (0);
265}
266#endif
267
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WD
268/***********************************************************************/
269
270#if defined(CONFIG_WATCHDOG)
271static int init_func_watchdog_init (void)
272{
273 puts (" Watchdog enabled\n");
274 WATCHDOG_RESET ();
275 return (0);
276}
277# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
278
279static int init_func_watchdog_reset (void)
280{
281 WATCHDOG_RESET ();
282 return (0);
283}
284# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
285#else
286# define INIT_FUNC_WATCHDOG_INIT /* undef */
287# define INIT_FUNC_WATCHDOG_RESET /* undef */
288#endif /* CONFIG_WATCHDOG */
289
290/************************************************************************
291 * Initialization sequence *
292 ************************************************************************
293 */
294
295init_fnc_t *init_sequence[] = {
296
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WD
297#if defined(CONFIG_BOARD_EARLY_INIT_F)
298 board_early_init_f,
fe8c2806 299#endif
c178d3da 300
66ca92a5 301#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 302 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
303#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
304 && !defined(CONFIG_TQM885D)
e9132ea9
WD
305 adjust_sdram_tbs_8xx,
306#endif
fe8c2806 307 init_timebase,
c178d3da 308#endif
fe8c2806 309#ifdef CFG_ALLOC_DPRAM
9c4c5ae3 310#if !defined(CONFIG_CPM2)
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WD
311 dpram_init,
312#endif
7aa78614 313#endif
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WD
314#if defined(CONFIG_BOARD_POSTCLK_INIT)
315 board_postclk_init,
316#endif
317 env_init,
66ca92a5 318#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
c178d3da
WD
319 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
320 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
321 init_timebase,
322#endif
fe8c2806
WD
323 init_baudrate,
324 serial_init,
325 console_init_f,
326 display_options,
327#if defined(CONFIG_8260)
328 prt_8260_rsr,
329 prt_8260_clks,
330#endif /* CONFIG_8260 */
9be39a67
DL
331#if defined(CONFIG_MPC83XX)
332 prt_83xx_rsr,
333#endif
fe8c2806 334 checkcpu,
cbd8a35c 335#if defined(CONFIG_MPC5xxx)
945af8d7 336 prt_mpc5xxx_clks,
cbd8a35c 337#endif /* CONFIG_MPC5xxx */
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WD
338#if defined(CONFIG_MPC8220)
339 prt_mpc8220_clks,
340#endif
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341 checkboard,
342 INIT_FUNC_WATCHDOG_INIT
c837dcb1 343#if defined(CONFIG_MISC_INIT_F)
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344 misc_init_f,
345#endif
346 INIT_FUNC_WATCHDOG_RESET
347#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
348 init_func_i2c,
349#endif
04a9e118
BW
350#if defined(CONFIG_HARD_SPI)
351 init_func_spi,
352#endif
fe8c2806
WD
353#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
354 dtt_init,
4532cb69
WD
355#endif
356#ifdef CONFIG_POST
357 post_init_f,
fe8c2806
WD
358#endif
359 INIT_FUNC_WATCHDOG_RESET
360 init_func_ram,
361#if defined(CFG_DRAM_TEST)
362 testdram,
363#endif /* CFG_DRAM_TEST */
364 INIT_FUNC_WATCHDOG_RESET
365
366 NULL, /* Terminate this list */
367};
368
81d93e5c
KG
369#ifndef CONFIG_MAX_MEM_MAPPED
370#define CONFIG_MAX_MEM_MAPPED (256 << 20)
371#endif
372ulong get_effective_memsize(void)
373{
374#ifndef CONFIG_VERY_BIG_RAM
375 return gd->ram_size;
376#else
377 /* limit stack to what we can reasonable map */
378 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
379 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
380#endif
381}
382
fe8c2806
WD
383/************************************************************************
384 *
385 * This is the first part of the initialization sequence that is
386 * implemented in C, but still running from ROM.
387 *
388 * The main purpose is to provide a (serial) console interface as
389 * soon as possible (so we can see any error messages), and to
390 * initialize the RAM so that we can relocate the monitor code to
391 * RAM.
392 *
393 * Be aware of the restrictions: global data is read-only, BSS is not
394 * initialized, and stack space is limited to a few kB.
395 *
396 ************************************************************************
397 */
398
95d449ad
MB
399#ifdef CONFIG_LOGBUFFER
400unsigned long logbuffer_base(void)
401{
402 return CFG_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
403}
404#endif
405
fe8c2806
WD
406void board_init_f (ulong bootflag)
407{
fe8c2806
WD
408 bd_t *bd;
409 ulong len, addr, addr_sp;
7bc5ee07 410 ulong *s;
fe8c2806
WD
411 gd_t *id;
412 init_fnc_t **init_fnc_ptr;
413#ifdef CONFIG_PRAM
414 int i;
415 ulong reg;
416 uchar tmp[64]; /* long enough for environment variables */
417#endif
418
419 /* Pointer is writable since we allocated a register for it */
420 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
93f6a677
WD
421 /* compiler optimization barrier needed for GCC >= 3.4 */
422 __asm__ __volatile__("": : :"memory");
fe8c2806 423
f060054d
KG
424#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) && \
425 !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx)
fe8c2806
WD
426 /* Clear initial global data */
427 memset ((void *) gd, 0, sizeof (gd_t));
428#endif
429
430 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
431 if ((*init_fnc_ptr) () != 0) {
432 hang ();
433 }
434 }
435
436 /*
437 * Now that we have DRAM mapped and working, we can
438 * relocate the code and continue running from DRAM.
439 *
440 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 441 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 442 * - kernel log buffer
fe8c2806
WD
443 * - protected RAM
444 * - LCD framebuffer
445 * - monitor code
446 * - board info struct
447 */
dfc6c7b6 448 len = (ulong)&_end - CFG_MONITOR_BASE;
fe8c2806 449
14f73ca6
SR
450 /*
451 * Subtract specified amount of memory to hide so that it won't
452 * get "touched" at all by U-Boot. By fixing up gd->ram_size
453 * the Linux kernel should now get passed the now "corrected"
454 * memory size and won't touch it either. This should work
455 * for arch/ppc and arch/powerpc. Only Linux board ports in
456 * arch/powerpc with bootwrapper support, that recalculate the
457 * memory size from the SDRAM controller setup will have to
458 * get fixed.
459 */
460 gd->ram_size -= CFG_MEM_TOP_HIDE;
461
81d93e5c 462 addr = CFG_SDRAM_BASE + get_effective_memsize();
fe8c2806 463
228f29ac 464#ifdef CONFIG_LOGBUFFER
3d610186 465#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
466 /* reserve kernel log buffer */
467 addr -= (LOGBUFF_RESERVE);
9d2b18a0 468 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 469#endif
3d610186 470#endif
228f29ac 471
fe8c2806
WD
472#ifdef CONFIG_PRAM
473 /*
474 * reserve protected RAM
475 */
77ddac94
WD
476 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
477 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 478 addr -= (reg << 10); /* size is in kB */
9d2b18a0 479 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
fe8c2806
WD
480#endif /* CONFIG_PRAM */
481
482 /* round down to next 4 kB limit */
483 addr &= ~(4096 - 1);
9d2b18a0 484 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
fe8c2806
WD
485
486#ifdef CONFIG_LCD
487 /* reserve memory for LCD display (always full pages) */
488 addr = lcd_setmem (addr);
489 gd->fb_base = addr;
490#endif /* CONFIG_LCD */
491
492#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
493 /* reserve memory for video display (always full pages) */
494 addr = video_setmem (addr);
495 gd->fb_base = addr;
496#endif /* CONFIG_VIDEO */
497
498 /*
499 * reserve memory for U-Boot code, data & bss
682011ff 500 * round down to next 4 kB limit
fe8c2806
WD
501 */
502 addr -= len;
682011ff 503 addr &= ~(4096 - 1);
7d314992
WD
504#ifdef CONFIG_E500
505 /* round down to next 64 kB limit so that IVPR stays aligned */
506 addr &= ~(65536 - 1);
507#endif
fe8c2806 508
9d2b18a0 509 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 510
c7de829c
WD
511#ifdef CONFIG_AMIGAONEG3SE
512 gd->relocaddr = addr;
513#endif
514
fe8c2806
WD
515 /*
516 * reserve memory for malloc() arena
517 */
518 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 519 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 520 TOTAL_MALLOC_LEN >> 10, addr_sp);
fe8c2806
WD
521
522 /*
523 * (permanently) allocate a Board Info struct
524 * and a permanent copy of the "global" data
525 */
526 addr_sp -= sizeof (bd_t);
527 bd = (bd_t *) addr_sp;
528 gd->bd = bd;
9d2b18a0 529 debug ("Reserving %d Bytes for Board Info at: %08lx\n",
fe8c2806 530 sizeof (bd_t), addr_sp);
fe8c2806
WD
531 addr_sp -= sizeof (gd_t);
532 id = (gd_t *) addr_sp;
9d2b18a0 533 debug ("Reserving %d Bytes for Global Data at: %08lx\n",
fe8c2806 534 sizeof (gd_t), addr_sp);
fe8c2806
WD
535
536 /*
537 * Finally, we set up a new (bigger) stack.
538 *
539 * Leave some safety gap for SP, force alignment on 16 byte boundary
540 * Clear initial stack frame
541 */
542 addr_sp -= 16;
543 addr_sp &= ~0xF;
7bc5ee07
WD
544 s = (ulong *)addr_sp;
545 *s-- = 0;
546 *s-- = 0;
547 addr_sp = (ulong)s;
9d2b18a0 548 debug ("Stack Pointer at: %08lx\n", addr_sp);
fe8c2806
WD
549
550 /*
551 * Save local variables to board info struct
552 */
553
c837dcb1 554 bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
fe8c2806
WD
555 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
556
557#ifdef CONFIG_IP860
c837dcb1
WD
558 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
559 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
983fda83
WD
560#elif defined CONFIG_MPC8220
561 bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */
562 bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 563#else
c837dcb1
WD
564 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
565 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
fe8c2806
WD
566#endif
567
42d1f039 568#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 569 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
fe8c2806
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570 bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
571#endif
cbd8a35c 572#if defined(CONFIG_MPC5xxx)
945af8d7
WD
573 bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
574#endif
f046ccd1 575#if defined(CONFIG_MPC83XX)
d239d74b 576 bd->bi_immrbar = CFG_IMMR;
f046ccd1 577#endif
983fda83
WD
578#if defined(CONFIG_MPC8220)
579 bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
580 bd->bi_inpfreq = gd->inp_clk;
581 bd->bi_pcifreq = gd->pci_clk;
582 bd->bi_vcofreq = gd->vco_clk;
583 bd->bi_pevfreq = gd->pev_clk;
584 bd->bi_flbfreq = gd->flb_clk;
585
dd520bf3
WD
586 /* store bootparam to sram (backward compatible), here? */
587 {
588 u32 *sram = (u32 *)CFG_SRAM_BASE;
589 *sram++ = gd->ram_size;
590 *sram++ = gd->bus_clk;
591 *sram++ = gd->inp_clk;
592 *sram++ = gd->cpu_clk;
593 *sram++ = gd->vco_clk;
594 *sram++ = gd->flb_clk;
595 *sram++ = 0xb8c3ba11; /* boot signature */
596 }
983fda83 597#endif
fe8c2806
WD
598
599 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
600
601 WATCHDOG_RESET ();
602 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
603 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 604#if defined(CONFIG_CPM2)
fe8c2806
WD
605 bd->bi_cpmfreq = gd->cpm_clk;
606 bd->bi_brgfreq = gd->brg_clk;
607 bd->bi_sccfreq = gd->scc_clk;
608 bd->bi_vco = gd->vco_out;
9c4c5ae3 609#endif /* CONFIG_CPM2 */
281ff9a4 610#if defined(CONFIG_MPC512X)
5d49e0e1 611 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 612#endif /* CONFIG_MPC512X */
cbd8a35c 613#if defined(CONFIG_MPC5xxx)
945af8d7
WD
614 bd->bi_ipbfreq = gd->ipb_clk;
615 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 616#endif /* CONFIG_MPC5xxx */
fe8c2806
WD
617 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
618
619#ifdef CFG_EXTBDINFO
77ddac94
WD
620 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
621 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
fe8c2806
WD
622
623 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
624 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
625#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
626 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
627 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 628 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 629 bd->bi_opbfreq = get_OPB_freq ();
028ab6b5
WD
630#elif defined(CONFIG_XILINX_ML300)
631 bd->bi_pci_busfreq = get_PCI_freq ();
fe8c2806
WD
632#endif
633#endif
634
9d2b18a0 635 debug ("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806
WD
636
637 WATCHDOG_RESET ();
638
639#ifdef CONFIG_POST
640 post_bootmode_init();
6dff5529 641 post_run (NULL, POST_ROM | post_bootmode_get(0));
fe8c2806
WD
642#endif
643
644 WATCHDOG_RESET();
645
27b207fd 646 memcpy (id, (void *)gd, sizeof (gd_t));
fe8c2806
WD
647
648 relocate_code (addr_sp, id, addr);
649
650 /* NOTREACHED - relocate_code() does not return */
651}
652
fe8c2806
WD
653/************************************************************************
654 *
655 * This is the next part if the initialization sequence: we are now
656 * running from RAM and have a "normal" C environment, i. e. global
657 * data can be written, BSS has been cleared, the stack size in not
658 * that critical any more, etc.
659 *
660 ************************************************************************
661 */
fe8c2806
WD
662void board_init_r (gd_t *id, ulong dest_addr)
663{
fe8c2806
WD
664 cmd_tbl_t *cmdtp;
665 char *s, *e;
666 bd_t *bd;
667 int i;
668 extern void malloc_bin_reloc (void);
669#ifndef CFG_ENV_IS_NOWHERE
670 extern char * env_name_spec;
671#endif
672
673#ifndef CFG_NO_FLASH
674 ulong flash_size;
675#endif
676
677 gd = id; /* initialize RAM version of global data */
678 bd = gd->bd;
679
680 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63
GL
681
682#if defined(CONFIG_RELOC_FIXUP_WORKS)
683 gd->reloc_off = 0;
e9514751 684 mem_malloc_end = dest_addr;
f82b3b63 685#else
bb105f24 686 gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
f82b3b63 687#endif
bb105f24
MB
688
689#ifdef CONFIG_SERIAL_MULTI
690 serial_initialize();
691#endif
fe8c2806 692
9d2b18a0 693 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806
WD
694
695 WATCHDOG_RESET ();
696
c837dcb1
WD
697#if defined(CONFIG_BOARD_EARLY_INIT_R)
698 board_early_init_r ();
699#endif
700
3b57fe0a 701 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806
WD
702
703 /*
704 * We have to relocate the command table manually
705 */
8bde7f77 706 for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
fe8c2806 707 ulong addr;
fe8c2806
WD
708 addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
709#if 0
710 printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
711 cmdtp->name, (ulong) (cmdtp->cmd), addr);
712#endif
713 cmdtp->cmd =
714 (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
715
716 addr = (ulong)(cmdtp->name) + gd->reloc_off;
717 cmdtp->name = (char *)addr;
718
719 if (cmdtp->usage) {
720 addr = (ulong)(cmdtp->usage) + gd->reloc_off;
721 cmdtp->usage = (char *)addr;
722 }
723#ifdef CFG_LONGHELP
724 if (cmdtp->help) {
725 addr = (ulong)(cmdtp->help) + gd->reloc_off;
726 cmdtp->help = (char *)addr;
727 }
728#endif
729 }
730 /* there are some other pointer constants we must deal with */
731#ifndef CFG_ENV_IS_NOWHERE
732 env_name_spec += gd->reloc_off;
733#endif
734
735 WATCHDOG_RESET ();
736
56f94be3 737#ifdef CONFIG_LOGBUFFER
228f29ac 738 logbuff_init_ptrs ();
56f94be3 739#endif
fe8c2806 740#ifdef CONFIG_POST
228f29ac 741 post_output_backlog ();
fe8c2806
WD
742 post_reloc ();
743#endif
744
745 WATCHDOG_RESET();
746
2688e2f9
KG
747#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
748 defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
fe8c2806
WD
749 icache_enable (); /* it's time to enable the instruction cache */
750#endif
751
1c8f6d8f 752#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
c837dcb1 753 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
754#endif
755
3bac3513 756#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 757 /*
3bac3513
WD
758 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
759 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
760 * bridge there.
fe8c2806
WD
761 */
762 pci_init ();
3bac3513
WD
763#endif
764#if defined(CONFIG_BAB7xx)
fe8c2806
WD
765 /*
766 * Initialise the ISA bridge
767 */
768 initialise_w83c553f ();
769#endif
770
771 asm ("sync ; isync");
772
773 /*
774 * Setup trap handlers
775 */
776 trap_init (dest_addr);
777
778#if !defined(CFG_NO_FLASH)
779 puts ("FLASH: ");
780
781 if ((flash_size = flash_init ()) > 0) {
0cb61d7d 782# ifdef CFG_FLASH_CHECKSUM
fe8c2806
WD
783 print_size (flash_size, "");
784 /*
785 * Compute and print flash CRC if flashchecksum is set to 'y'
786 *
787 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
788 */
789 s = getenv ("flashchecksum");
790 if (s && (*s == 'y')) {
791 printf (" CRC: %08lX",
7e780369
WD
792 crc32 (0, (const unsigned char *) CFG_FLASH_BASE, flash_size)
793 );
fe8c2806
WD
794 }
795 putc ('\n');
0cb61d7d 796# else /* !CFG_FLASH_CHECKSUM */
fe8c2806 797 print_size (flash_size, "\n");
0cb61d7d 798# endif /* CFG_FLASH_CHECKSUM */
fe8c2806
WD
799 } else {
800 puts (failed);
801 hang ();
802 }
803
804 bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
805 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445
HS
806
807#if defined(CFG_UPDATE_FLASH_SIZE)
808 /* Make a update of the Memctrl. */
809 update_flash_size (flash_size);
810#endif
811
812
7e780369
WD
813# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
814 /* flash mapped at end of memory map */
815 bd->bi_flashoffset = TEXT_BASE + flash_size;
0cb61d7d 816# elif CFG_MONITOR_BASE == CFG_FLASH_BASE
3b57fe0a 817 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 818# else
fe8c2806 819 bd->bi_flashoffset = 0;
0cb61d7d
WD
820# endif
821#else /* CFG_NO_FLASH */
fe8c2806
WD
822
823 bd->bi_flashsize = 0;
824 bd->bi_flashstart = 0;
825 bd->bi_flashoffset = 0;
826#endif /* !CFG_NO_FLASH */
827
828 WATCHDOG_RESET ();
829
830 /* initialize higher level parts of CPU like time base and timers */
831 cpu_init_r ();
832
833 WATCHDOG_RESET ();
834
835 /* initialize malloc() area */
836 mem_malloc_init ();
837 malloc_bin_reloc ();
838
839#ifdef CONFIG_SPI
840# if !defined(CFG_ENV_IS_IN_EEPROM)
841 spi_init_f ();
842# endif
843 spi_init_r ();
844#endif
845
7def6b34 846#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
847 WATCHDOG_RESET ();
848 puts ("NAND: ");
849 nand_init(); /* go init the NAND */
850#endif
851
fe8c2806
WD
852 /* relocate environment function pointers etc. */
853 env_relocate ();
854
855 /*
856 * Fill in missing fields of bd_info.
8bde7f77
WD
857 * We do this here, where we have "normal" access to the
858 * environment; we used to do this still running from ROM,
859 * where had to use getenv_r(), which can be pretty slow when
860 * the environment is in EEPROM.
fe8c2806 861 */
7abf0c58
WD
862
863#if defined(CFG_EXTBDINFO)
864#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
865#if defined(CONFIG_I2CFAST)
866 /*
867 * set bi_iic_fast for linux taking environment variable
868 * "i2cfast" into account
869 */
870 {
871 char *s = getenv ("i2cfast");
872 if (s && ((*s == 'y') || (*s == 'Y'))) {
873 bd->bi_iic_fast[0] = 1;
874 bd->bi_iic_fast[1] = 1;
875 } else {
876 bd->bi_iic_fast[0] = 0;
877 bd->bi_iic_fast[1] = 0;
878 }
879 }
880#else
881 bd->bi_iic_fast[0] = 0;
882 bd->bi_iic_fast[1] = 0;
883#endif /* CONFIG_I2CFAST */
884#endif /* CONFIG_405GP, CONFIG_405EP */
885#endif /* CFG_EXTBDINFO */
886
9045f33c 887#if defined(CONFIG_SC3)
ca43ba18
HS
888 sc3_read_eeprom();
889#endif
d59feffb 890
5b2793a3 891#if defined (CFG_ID_EEPROM) || defined (CFG_I2C_MAC_OFFSET)
d59feffb
HW
892 mac_read_from_eeprom();
893#endif
894
fe8c2806 895 s = getenv ("ethaddr");
4707fb50
BS
896#if defined (CONFIG_MBX) || \
897 defined (CONFIG_RPXCLASSIC) || \
898 defined(CONFIG_IAD210) || \
899 defined(CONFIG_V38B)
fe8c2806
WD
900 if (s == NULL)
901 board_get_enetaddr (bd->bi_enetaddr);
902 else
903#endif
904 for (i = 0; i < 6; ++i) {
905 bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
906 if (s)
907 s = (*e) ? e + 1 : e;
908 }
909#ifdef CONFIG_HERMES
910 if ((gd->board_type >> 16) == 2)
911 bd->bi_ethspeed = gd->board_type & 0xFFFF;
912 else
913 bd->bi_ethspeed = 0xFFFF;
914#endif
915
916#ifdef CONFIG_NX823
917 load_sernum_ethaddr ();
918#endif
919
e2ffd59b 920#ifdef CONFIG_HAS_ETH1
fe8c2806
WD
921 /* handle the 2nd ethernet address */
922
923 s = getenv ("eth1addr");
924
925 for (i = 0; i < 6; ++i) {
926 bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
927 if (s)
928 s = (*e) ? e + 1 : e;
929 }
930#endif
e2ffd59b 931#ifdef CONFIG_HAS_ETH2
fe8c2806
WD
932 /* handle the 3rd ethernet address */
933
934 s = getenv ("eth2addr");
b79316f2 935#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
936 if (s == NULL)
937 board_get_enetaddr(bd->bi_enet2addr);
938 else
939#endif
fe8c2806
WD
940 for (i = 0; i < 6; ++i) {
941 bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
942 if (s)
943 s = (*e) ? e + 1 : e;
944 }
945#endif
946
e2ffd59b 947#ifdef CONFIG_HAS_ETH3
ba56f625
WD
948 /* handle 4th ethernet address */
949 s = getenv("eth3addr");
b79316f2 950#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
951 if (s == NULL)
952 board_get_enetaddr(bd->bi_enet3addr);
953 else
954#endif
955 for (i = 0; i < 6; ++i) {
956 bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
957 if (s)
958 s = (*e) ? e + 1 : e;
959 }
960#endif
fe8c2806
WD
961
962#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
fa230445 963 defined(CONFIG_TQM8272) || \
566a494f
HS
964 defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \
965 defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP)
fe8c2806
WD
966 load_sernum_ethaddr ();
967#endif
968 /* IP Address */
969 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
970
971 WATCHDOG_RESET ();
972
979bdbc7 973#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
974 /*
975 * Do pci configuration
976 */
977 pci_init ();
978#endif
979
980/** leave this here (after malloc(), environment and PCI are working) **/
981 /* Initialize devices */
982 devices_init ();
983
27b207fd
WD
984 /* Initialize the jump table for applications */
985 jumptable_init ();
fe8c2806 986
500856eb
RJ
987#if defined(CONFIG_API)
988 /* Initialize API */
989 api_init ();
990#endif
991
fe8c2806
WD
992 /* Initialize the console (after the relocation and devices init) */
993 console_init_r ();
fe8c2806
WD
994
995#if defined(CONFIG_CCM) || \
996 defined(CONFIG_COGENT) || \
997 defined(CONFIG_CPCI405) || \
998 defined(CONFIG_EVB64260) || \
56f94be3 999 defined(CONFIG_KUP4K) || \
0608e04d 1000 defined(CONFIG_KUP4X) || \
fe8c2806
WD
1001 defined(CONFIG_LWMON) || \
1002 defined(CONFIG_PCU_E) || \
9045f33c 1003 defined(CONFIG_SC3) || \
fe8c2806
WD
1004 defined(CONFIG_W7O) || \
1005 defined(CONFIG_MISC_INIT_R)
1006 /* miscellaneous platform dependent initialisations */
1007 misc_init_r ();
1008#endif
1009
1010#ifdef CONFIG_HERMES
1011 if (bd->bi_ethspeed != 0xFFFF)
1012 hermes_start_lxt980 ((int) bd->bi_ethspeed);
1013#endif
1014
7def6b34 1015#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
1016 WATCHDOG_RESET ();
1017 puts ("KGDB: ");
1018 kgdb_init ();
1019#endif
1020
9d2b18a0 1021 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
1022
1023 /*
1024 * Enable Interrupts
1025 */
1026 interrupt_init ();
1027
1028 /* Must happen after interrupts are initialized since
1029 * an irq handler gets installed
1030 */
42dfe7a1 1031#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
1032 serial_buffered_init();
1033#endif
1034
566a494f 1035#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
1036 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
1037#endif
1038
1039 udelay (20);
1040
1041 set_timer (0);
1042
fe8c2806
WD
1043 /* Initialize from environment */
1044 if ((s = getenv ("loadaddr")) != NULL) {
1045 load_addr = simple_strtoul (s, NULL, 16);
1046 }
7def6b34 1047#if defined(CONFIG_CMD_NET)
fe8c2806
WD
1048 if ((s = getenv ("bootfile")) != NULL) {
1049 copy_filename (BootFile, s, sizeof (BootFile));
1050 }
b3aff0cb 1051#endif
fe8c2806
WD
1052
1053 WATCHDOG_RESET ();
1054
7def6b34 1055#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
1056 WATCHDOG_RESET ();
1057 puts ("SCSI: ");
1058 scsi_init ();
1059#endif
1060
7def6b34 1061#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
1062 WATCHDOG_RESET ();
1063 puts ("DOC: ");
1064 doc_init ();
1065#endif
1066
7def6b34 1067#if defined(CONFIG_CMD_NET)
63ff004c 1068#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
1069 WATCHDOG_RESET ();
1070 puts ("Net: ");
63ff004c 1071#endif
fe8c2806
WD
1072 eth_initialize (bd);
1073#endif
1074
7def6b34 1075#if defined(CONFIG_CMD_NET) && ( \
63ff004c
MB
1076 defined(CONFIG_CCM) || \
1077 defined(CONFIG_ELPT860) || \
1078 defined(CONFIG_EP8260) || \
1079 defined(CONFIG_IP860) || \
1080 defined(CONFIG_IVML24) || \
1081 defined(CONFIG_IVMS8) || \
1082 defined(CONFIG_MPC8260ADS) || \
1083 defined(CONFIG_MPC8266ADS) || \
1084 defined(CONFIG_MPC8560ADS) || \
1085 defined(CONFIG_PCU_E) || \
1086 defined(CONFIG_RPXSUPER) || \
1087 defined(CONFIG_STXGP3) || \
1088 defined(CONFIG_SPD823TS) || \
1089 defined(CONFIG_RESET_PHY_R) )
1090
1091 WATCHDOG_RESET ();
1092 debug ("Reset Ethernet PHY\n");
1093 reset_phy ();
1094#endif
1095
fe8c2806 1096#ifdef CONFIG_POST
6dff5529 1097 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
1098#endif
1099
7def6b34
JL
1100#if defined(CONFIG_CMD_PCMCIA) \
1101 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
1102 WATCHDOG_RESET ();
1103 puts ("PCMCIA:");
1104 pcmcia_init ();
1105#endif
1106
7def6b34 1107#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
1108 WATCHDOG_RESET ();
1109# ifdef CONFIG_IDE_8xx_PCCARD
1110 puts ("PCMCIA:");
1111# else
1112 puts ("IDE: ");
1113#endif
ca43ba18
HS
1114#if defined(CONFIG_START_IDE)
1115 if (board_start_ide())
1116 ide_init ();
1117#else
fe8c2806 1118 ide_init ();
ca43ba18 1119#endif
b3aff0cb 1120#endif
fe8c2806 1121
cd54081c
DL
1122#if defined(CONFIG_CMD_SATA)
1123 puts ("SATA: ");
1124 sata_initialize ();
1125#endif
1126
fe8c2806
WD
1127#ifdef CONFIG_LAST_STAGE_INIT
1128 WATCHDOG_RESET ();
1129 /*
1130 * Some parts can be only initialized if all others (like
1131 * Interrupts) are up and running (i.e. the PC-style ISA
1132 * keyboard).
1133 */
1134 last_stage_init ();
1135#endif
1136
7def6b34 1137#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1138 WATCHDOG_RESET ();
1139 bedbug_init ();
1140#endif
1141
228f29ac 1142#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1143 /*
1144 * Export available size of memory for Linux,
1145 * taking into account the protected RAM at top of memory
1146 */
1147 {
1148 ulong pram;
fe8c2806 1149 uchar memsz[32];
228f29ac
WD
1150#ifdef CONFIG_PRAM
1151 char *s;
fe8c2806
WD
1152
1153 if ((s = getenv ("pram")) != NULL) {
1154 pram = simple_strtoul (s, NULL, 10);
1155 } else {
1156 pram = CONFIG_PRAM;
1157 }
228f29ac
WD
1158#else
1159 pram=0;
1160#endif
1161#ifdef CONFIG_LOGBUFFER
3d610186 1162#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1163 /* Also take the logbuffer into account (pram is in kB) */
1164 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1165#endif
228f29ac 1166#endif
77ddac94
WD
1167 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1168 setenv ("mem", (char *)memsz);
fe8c2806
WD
1169 }
1170#endif
1171
1c43771b
WD
1172#ifdef CONFIG_PS2KBD
1173 puts ("PS/2: ");
1174 kbd_init();
1175#endif
1176
4532cb69
WD
1177#ifdef CONFIG_MODEM_SUPPORT
1178 {
1179 extern int do_mdm_init;
1180 do_mdm_init = gd->do_mdm_init;
1181 }
1182#endif
1183
fe8c2806
WD
1184 /* Initialization complete - start the monitor */
1185
1186 /* main_loop() can return to retry autoboot, if so just run it again. */
1187 for (;;) {
1188 WATCHDOG_RESET ();
1189 main_loop ();
1190 }
1191
1192 /* NOTREACHED - no way out of command loop except booting */
1193}
1194
1195void hang (void)
1196{
1197 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1198 show_boot_progress(-30);
fe8c2806
WD
1199 for (;;);
1200}
1201
4532cb69
WD
1202#ifdef CONFIG_MODEM_SUPPORT
1203/* called from main loop (common/main.c) */
77ddac94
WD
1204/* 'inline' - We have to do it fast */
1205static inline void mdm_readline(char *buf, int bufsiz)
1206{
1207 char c;
1208 char *p;
1209 int n;
1210
1211 n = 0;
1212 p = buf;
1213 for(;;) {
1214 c = serial_getc();
1215
1216 /* dbg("(%c)", c); */
1217
1218 switch(c) {
1219 case '\r':
1220 break;
1221 case '\n':
1222 *p = '\0';
1223 return;
1224
1225 default:
1226 if(n++ > bufsiz) {
1227 *p = '\0';
1228 return; /* sanity check */
1229 }
1230 *p = c;
1231 p++;
1232 break;
1233 }
1234 }
1235}
1236
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1237extern void dbg(const char *fmt, ...);
1238int mdm_init (void)
1239{
1240 char env_str[16];
1241 char *init_str;
1242 int i;
1243 extern char console_buffer[];
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1244 extern void enable_putc(void);
1245 extern int hwflow_onoff(int);
1246
1247 enable_putc(); /* enable serial_putc() */
1248
1249#ifdef CONFIG_HWFLOW
1250 init_str = getenv("mdm_flow_control");
1251 if (init_str && (strcmp(init_str, "rts/cts") == 0))
1252 hwflow_onoff (1);
1253 else
1254 hwflow_onoff(-1);
1255#endif
1256
1257 for (i = 1;;i++) {
1258 sprintf(env_str, "mdm_init%d", i);
1259 if ((init_str = getenv(env_str)) != NULL) {
1260 serial_puts(init_str);
1261 serial_puts("\n");
1262 for(;;) {
1263 mdm_readline(console_buffer, CFG_CBSIZE);
1264 dbg("ini%d: [%s]", i, console_buffer);
1265
1266 if ((strcmp(console_buffer, "OK") == 0) ||
1267 (strcmp(console_buffer, "ERROR") == 0)) {
1268 dbg("ini%d: cmd done", i);
1269 break;
1270 } else /* in case we are originating call ... */
1271 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1272 dbg("ini%d: connect", i);
1273 return 0;
1274 }
1275 }
1276 } else
1277 break; /* no init string - stop modem init */
1278
1279 udelay(100000);
1280 }
1281
1282 udelay(100000);
1283
1284 /* final stage - wait for connect */
1285 for(;i > 1;) { /* if 'i' > 1 - wait for connection
1286 message from modem */
1287 mdm_readline(console_buffer, CFG_CBSIZE);
1288 dbg("ini_f: [%s]", console_buffer);
1289 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1290 dbg("ini_f: connected");
1291 return 0;
1292 }
1293 }
1294
1295 return 0;
1296}
1297
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1298#endif
1299
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1300#if 0 /* We could use plain global data, but the resulting code is bigger */
1301/*
1302 * Pointer to initial global data area
1303 *
1304 * Here we initialize it.
1305 */
1306#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1307#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
1308DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
1309#endif /* 0 */
1310
1311/************************************************************************/