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Eliminated arch-specific mmc header requirement
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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
fe8c2806
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
28#include <devices.h>
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
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32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
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36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
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39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
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42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
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45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
281e00a3 51#include <serial.h>
6d0f6bcf 52#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 53#if !defined(CONFIG_CPM2)
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54#include <commproc.h>
55#endif
7aa78614 56#endif
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57#include <version.h>
58#if defined(CONFIG_BAB7xx)
59#include <w83c553f.h>
60#endif
61#include <dtt.h>
62#if defined(CONFIG_POST)
63#include <post.h>
64#endif
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65#if defined(CONFIG_LOGBUFFER)
66#include <logbuff.h>
67#endif
6d0f6bcf 68#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
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69#include <asm/cache.h>
70#endif
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71#ifdef CONFIG_PS2KBD
72#include <keyboard.h>
73#endif
fe8c2806 74
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75#ifdef CONFIG_ADDR_MAP
76#include <asm/mmu.h>
77#endif
78
6d0f6bcf 79#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
fa230445
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80extern int update_flash_size (int flash_size);
81#endif
82
9045f33c 83#if defined(CONFIG_SC3)
ca43ba18
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84extern void sc3_read_eeprom(void);
85#endif
86
7def6b34 87#if defined(CONFIG_CMD_DOC)
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88void doc_init (void);
89#endif
90#if defined(CONFIG_HARD_I2C) || \
91 defined(CONFIG_SOFT_I2C)
92#include <i2c.h>
93#endif
04a9e118 94#include <spi.h>
d6ac2ed8 95#include <nand.h>
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96
97static char *failed = "*** failed ***\n";
98
17d704eb 99#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 100extern flash_info_t flash_info[];
17d704eb 101#endif
fe8c2806 102
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103#if defined(CONFIG_START_IDE)
104extern int board_start_ide(void);
105#endif
fe8c2806 106#include <environment.h>
d87080b7 107
bce84c4d 108DECLARE_GLOBAL_DATA_PTR;
fe8c2806 109
0e8d1586 110#if defined(CONFIG_ENV_IS_EMBEDDED)
6d0f6bcf
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111#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
112#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
113 (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
9314cee6 114 defined(CONFIG_ENV_IS_IN_NVRAM)
6d0f6bcf 115#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
fe8c2806 116#else
6d0f6bcf 117#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
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118#endif
119
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120#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
121#define CONFIG_SYS_MEM_TOP_HIDE 0
6fb4b640
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122#endif
123
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124extern ulong __init_end;
125extern ulong _end;
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126ulong monitor_flash_len;
127
7def6b34 128#if defined(CONFIG_CMD_BEDBUG)
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129#include <bedbug/type.h>
130#endif
131
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132/*
133 * Begin and End of memory area for malloc(), and current "brk"
134 */
135static ulong mem_malloc_start = 0;
136static ulong mem_malloc_end = 0;
137static ulong mem_malloc_brk = 0;
138
139/************************************************************************
140 * Utilities *
141 ************************************************************************
142 */
143
144/*
145 * The Malloc area is immediately below the monitor copy in DRAM
146 */
147static void mem_malloc_init (void)
148{
e9514751 149#if !defined(CONFIG_RELOC_FIXUP_WORKS)
6d0f6bcf 150 mem_malloc_end = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
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151#endif
152 mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
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153 mem_malloc_brk = mem_malloc_start;
154
155 memset ((void *) mem_malloc_start,
156 0,
157 mem_malloc_end - mem_malloc_start);
158}
159
160void *sbrk (ptrdiff_t increment)
161{
162 ulong old = mem_malloc_brk;
163 ulong new = old + increment;
164
165 if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
166 return (NULL);
167 }
168 mem_malloc_brk = new;
169 return ((void *) old);
170}
171
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172/*
173 * All attempts to come up with a "common" initialization sequence
174 * that works for all boards and architectures failed: some of the
175 * requirements are just _too_ different. To get rid of the resulting
176 * mess of board dependend #ifdef'ed code we now make the whole
177 * initialization sequence configurable to the user.
178 *
179 * The requirements for any new initalization function is simple: it
180 * receives a pointer to the "global data" structure as it's only
181 * argument, and returns an integer return code, where 0 means
182 * "continue" and != 0 means "fatal error, hang the system".
183 */
184typedef int (init_fnc_t) (void);
185
186/************************************************************************
187 * Init Utilities *
188 ************************************************************************
189 * Some of this code should be moved into the core functions,
190 * but let's get it working (again) first...
191 */
192
193static int init_baudrate (void)
194{
77ddac94 195 char tmp[64]; /* long enough for environment variables */
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196 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
197
198 gd->baudrate = (i > 0)
199 ? (int) simple_strtoul (tmp, NULL, 10)
200 : CONFIG_BAUDRATE;
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201 return (0);
202}
203
204/***********************************************************************/
205
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206void __board_add_ram_info(int use_default)
207{
208 /* please define platform specific board_add_ram_info() */
209}
210void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
211
d96f41e0 212
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213static int init_func_ram (void)
214{
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215#ifdef CONFIG_BOARD_TYPES
216 int board_type = gd->board_type;
217#else
218 int board_type = 0; /* use dummy arg */
219#endif
220 puts ("DRAM: ");
221
222 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 223 print_size (gd->ram_size, "");
d96f41e0 224 board_add_ram_info(0);
d96f41e0 225 putc('\n');
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226 return (0);
227 }
228 puts (failed);
229 return (1);
230}
231
232/***********************************************************************/
233
234#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
235static int init_func_i2c (void)
236{
237 puts ("I2C: ");
6d0f6bcf 238 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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239 puts ("ready\n");
240 return (0);
241}
242#endif
243
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244#if defined(CONFIG_HARD_SPI)
245static int init_func_spi (void)
246{
247 puts ("SPI: ");
248 spi_init ();
249 puts ("ready\n");
250 return (0);
251}
252#endif
253
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254/***********************************************************************/
255
256#if defined(CONFIG_WATCHDOG)
257static int init_func_watchdog_init (void)
258{
259 puts (" Watchdog enabled\n");
260 WATCHDOG_RESET ();
261 return (0);
262}
263# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
264
265static int init_func_watchdog_reset (void)
266{
267 WATCHDOG_RESET ();
268 return (0);
269}
270# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
271#else
272# define INIT_FUNC_WATCHDOG_INIT /* undef */
273# define INIT_FUNC_WATCHDOG_RESET /* undef */
274#endif /* CONFIG_WATCHDOG */
275
276/************************************************************************
277 * Initialization sequence *
278 ************************************************************************
279 */
280
281init_fnc_t *init_sequence[] = {
282
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283#if defined(CONFIG_BOARD_EARLY_INIT_F)
284 board_early_init_f,
fe8c2806 285#endif
c178d3da 286
66ca92a5 287#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 288 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
289#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
290 && !defined(CONFIG_TQM885D)
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291 adjust_sdram_tbs_8xx,
292#endif
fe8c2806 293 init_timebase,
c178d3da 294#endif
6d0f6bcf 295#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 296#if !defined(CONFIG_CPM2)
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297 dpram_init,
298#endif
7aa78614 299#endif
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300#if defined(CONFIG_BOARD_POSTCLK_INIT)
301 board_postclk_init,
302#endif
303 env_init,
66ca92a5 304#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
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WD
305 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
306 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
307 init_timebase,
308#endif
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309 init_baudrate,
310 serial_init,
311 console_init_f,
312 display_options,
313#if defined(CONFIG_8260)
314 prt_8260_rsr,
315 prt_8260_clks,
316#endif /* CONFIG_8260 */
9be39a67
DL
317#if defined(CONFIG_MPC83XX)
318 prt_83xx_rsr,
319#endif
fe8c2806 320 checkcpu,
cbd8a35c 321#if defined(CONFIG_MPC5xxx)
945af8d7 322 prt_mpc5xxx_clks,
cbd8a35c 323#endif /* CONFIG_MPC5xxx */
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324#if defined(CONFIG_MPC8220)
325 prt_mpc8220_clks,
326#endif
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327 checkboard,
328 INIT_FUNC_WATCHDOG_INIT
c837dcb1 329#if defined(CONFIG_MISC_INIT_F)
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330 misc_init_f,
331#endif
332 INIT_FUNC_WATCHDOG_RESET
333#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
334 init_func_i2c,
335#endif
04a9e118
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336#if defined(CONFIG_HARD_SPI)
337 init_func_spi,
338#endif
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339#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
340 dtt_init,
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341#endif
342#ifdef CONFIG_POST
343 post_init_f,
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344#endif
345 INIT_FUNC_WATCHDOG_RESET
346 init_func_ram,
6d0f6bcf 347#if defined(CONFIG_SYS_DRAM_TEST)
fe8c2806 348 testdram,
6d0f6bcf 349#endif /* CONFIG_SYS_DRAM_TEST */
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350 INIT_FUNC_WATCHDOG_RESET
351
352 NULL, /* Terminate this list */
353};
354
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355ulong get_effective_memsize(void)
356{
357#ifndef CONFIG_VERY_BIG_RAM
358 return gd->ram_size;
359#else
360 /* limit stack to what we can reasonable map */
361 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
362 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
363#endif
364}
365
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366/************************************************************************
367 *
368 * This is the first part of the initialization sequence that is
369 * implemented in C, but still running from ROM.
370 *
371 * The main purpose is to provide a (serial) console interface as
372 * soon as possible (so we can see any error messages), and to
373 * initialize the RAM so that we can relocate the monitor code to
374 * RAM.
375 *
376 * Be aware of the restrictions: global data is read-only, BSS is not
377 * initialized, and stack space is limited to a few kB.
378 *
379 ************************************************************************
380 */
381
95d449ad
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382#ifdef CONFIG_LOGBUFFER
383unsigned long logbuffer_base(void)
384{
6d0f6bcf 385 return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
95d449ad
MB
386}
387#endif
388
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389void board_init_f (ulong bootflag)
390{
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391 bd_t *bd;
392 ulong len, addr, addr_sp;
7bc5ee07 393 ulong *s;
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394 gd_t *id;
395 init_fnc_t **init_fnc_ptr;
396#ifdef CONFIG_PRAM
397 int i;
398 ulong reg;
399 uchar tmp[64]; /* long enough for environment variables */
400#endif
401
402 /* Pointer is writable since we allocated a register for it */
6d0f6bcf 403 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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WD
404 /* compiler optimization barrier needed for GCC >= 3.4 */
405 __asm__ __volatile__("": : :"memory");
fe8c2806 406
f060054d
KG
407#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) && \
408 !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx)
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409 /* Clear initial global data */
410 memset ((void *) gd, 0, sizeof (gd_t));
411#endif
412
413 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
414 if ((*init_fnc_ptr) () != 0) {
415 hang ();
416 }
417 }
418
419 /*
420 * Now that we have DRAM mapped and working, we can
421 * relocate the code and continue running from DRAM.
422 *
423 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 424 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 425 * - kernel log buffer
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426 * - protected RAM
427 * - LCD framebuffer
428 * - monitor code
429 * - board info struct
430 */
6d0f6bcf 431 len = (ulong)&_end - CONFIG_SYS_MONITOR_BASE;
fe8c2806 432
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SR
433 /*
434 * Subtract specified amount of memory to hide so that it won't
435 * get "touched" at all by U-Boot. By fixing up gd->ram_size
436 * the Linux kernel should now get passed the now "corrected"
437 * memory size and won't touch it either. This should work
438 * for arch/ppc and arch/powerpc. Only Linux board ports in
439 * arch/powerpc with bootwrapper support, that recalculate the
440 * memory size from the SDRAM controller setup will have to
441 * get fixed.
442 */
6d0f6bcf 443 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
14f73ca6 444
6d0f6bcf 445 addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
fe8c2806 446
228f29ac 447#ifdef CONFIG_LOGBUFFER
3d610186 448#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
449 /* reserve kernel log buffer */
450 addr -= (LOGBUFF_RESERVE);
9d2b18a0 451 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 452#endif
3d610186 453#endif
228f29ac 454
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WD
455#ifdef CONFIG_PRAM
456 /*
457 * reserve protected RAM
458 */
77ddac94
WD
459 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
460 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 461 addr -= (reg << 10); /* size is in kB */
9d2b18a0 462 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
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WD
463#endif /* CONFIG_PRAM */
464
465 /* round down to next 4 kB limit */
466 addr &= ~(4096 - 1);
9d2b18a0 467 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
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468
469#ifdef CONFIG_LCD
470 /* reserve memory for LCD display (always full pages) */
471 addr = lcd_setmem (addr);
472 gd->fb_base = addr;
473#endif /* CONFIG_LCD */
474
475#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
476 /* reserve memory for video display (always full pages) */
477 addr = video_setmem (addr);
478 gd->fb_base = addr;
479#endif /* CONFIG_VIDEO */
480
481 /*
482 * reserve memory for U-Boot code, data & bss
682011ff 483 * round down to next 4 kB limit
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484 */
485 addr -= len;
682011ff 486 addr &= ~(4096 - 1);
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487#ifdef CONFIG_E500
488 /* round down to next 64 kB limit so that IVPR stays aligned */
489 addr &= ~(65536 - 1);
490#endif
fe8c2806 491
9d2b18a0 492 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 493
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494#ifdef CONFIG_AMIGAONEG3SE
495 gd->relocaddr = addr;
496#endif
497
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498 /*
499 * reserve memory for malloc() arena
500 */
501 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 502 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 503 TOTAL_MALLOC_LEN >> 10, addr_sp);
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WD
504
505 /*
506 * (permanently) allocate a Board Info struct
507 * and a permanent copy of the "global" data
508 */
509 addr_sp -= sizeof (bd_t);
510 bd = (bd_t *) addr_sp;
511 gd->bd = bd;
b64f190b 512 debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
fe8c2806 513 sizeof (bd_t), addr_sp);
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514 addr_sp -= sizeof (gd_t);
515 id = (gd_t *) addr_sp;
b64f190b 516 debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
fe8c2806 517 sizeof (gd_t), addr_sp);
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518
519 /*
520 * Finally, we set up a new (bigger) stack.
521 *
522 * Leave some safety gap for SP, force alignment on 16 byte boundary
523 * Clear initial stack frame
524 */
525 addr_sp -= 16;
526 addr_sp &= ~0xF;
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WD
527 s = (ulong *)addr_sp;
528 *s-- = 0;
529 *s-- = 0;
530 addr_sp = (ulong)s;
9d2b18a0 531 debug ("Stack Pointer at: %08lx\n", addr_sp);
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532
533 /*
534 * Save local variables to board info struct
535 */
536
6d0f6bcf 537 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
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538 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
539
540#ifdef CONFIG_IP860
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541 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
542 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
983fda83 543#elif defined CONFIG_MPC8220
6d0f6bcf
JCPV
544 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
545 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 546#else
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547 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
548 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
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549#endif
550
42d1f039 551#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 552 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
6d0f6bcf 553 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
fe8c2806 554#endif
cbd8a35c 555#if defined(CONFIG_MPC5xxx)
6d0f6bcf 556 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
945af8d7 557#endif
f046ccd1 558#if defined(CONFIG_MPC83XX)
6d0f6bcf 559 bd->bi_immrbar = CONFIG_SYS_IMMR;
f046ccd1 560#endif
983fda83 561#if defined(CONFIG_MPC8220)
6d0f6bcf 562 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
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WD
563 bd->bi_inpfreq = gd->inp_clk;
564 bd->bi_pcifreq = gd->pci_clk;
565 bd->bi_vcofreq = gd->vco_clk;
566 bd->bi_pevfreq = gd->pev_clk;
567 bd->bi_flbfreq = gd->flb_clk;
568
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WD
569 /* store bootparam to sram (backward compatible), here? */
570 {
6d0f6bcf 571 u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE;
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WD
572 *sram++ = gd->ram_size;
573 *sram++ = gd->bus_clk;
574 *sram++ = gd->inp_clk;
575 *sram++ = gd->cpu_clk;
576 *sram++ = gd->vco_clk;
577 *sram++ = gd->flb_clk;
578 *sram++ = 0xb8c3ba11; /* boot signature */
579 }
983fda83 580#endif
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WD
581
582 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
583
584 WATCHDOG_RESET ();
585 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
586 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 587#if defined(CONFIG_CPM2)
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588 bd->bi_cpmfreq = gd->cpm_clk;
589 bd->bi_brgfreq = gd->brg_clk;
590 bd->bi_sccfreq = gd->scc_clk;
591 bd->bi_vco = gd->vco_out;
9c4c5ae3 592#endif /* CONFIG_CPM2 */
281ff9a4 593#if defined(CONFIG_MPC512X)
5d49e0e1 594 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 595#endif /* CONFIG_MPC512X */
cbd8a35c 596#if defined(CONFIG_MPC5xxx)
945af8d7
WD
597 bd->bi_ipbfreq = gd->ipb_clk;
598 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 599#endif /* CONFIG_MPC5xxx */
fe8c2806
WD
600 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
601
6d0f6bcf 602#ifdef CONFIG_SYS_EXTBDINFO
77ddac94
WD
603 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
604 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
fe8c2806
WD
605
606 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
607 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
608#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
609 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
610 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 611 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 612 bd->bi_opbfreq = get_OPB_freq ();
9fea65a6 613#elif defined(CONFIG_XILINX_405)
028ab6b5 614 bd->bi_pci_busfreq = get_PCI_freq ();
fe8c2806
WD
615#endif
616#endif
617
9d2b18a0 618 debug ("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806
WD
619
620 WATCHDOG_RESET ();
621
622#ifdef CONFIG_POST
623 post_bootmode_init();
6dff5529 624 post_run (NULL, POST_ROM | post_bootmode_get(0));
fe8c2806
WD
625#endif
626
627 WATCHDOG_RESET();
628
27b207fd 629 memcpy (id, (void *)gd, sizeof (gd_t));
fe8c2806
WD
630
631 relocate_code (addr_sp, id, addr);
632
633 /* NOTREACHED - relocate_code() does not return */
634}
635
fe8c2806
WD
636/************************************************************************
637 *
638 * This is the next part if the initialization sequence: we are now
639 * running from RAM and have a "normal" C environment, i. e. global
640 * data can be written, BSS has been cleared, the stack size in not
641 * that critical any more, etc.
642 *
643 ************************************************************************
644 */
fe8c2806
WD
645void board_init_r (gd_t *id, ulong dest_addr)
646{
fe8c2806
WD
647 cmd_tbl_t *cmdtp;
648 char *s, *e;
649 bd_t *bd;
650 int i;
651 extern void malloc_bin_reloc (void);
93f6d725 652#ifndef CONFIG_ENV_IS_NOWHERE
fe8c2806
WD
653 extern char * env_name_spec;
654#endif
655
6d0f6bcf 656#ifndef CONFIG_SYS_NO_FLASH
fe8c2806
WD
657 ulong flash_size;
658#endif
659
660 gd = id; /* initialize RAM version of global data */
661 bd = gd->bd;
662
663 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63
GL
664
665#if defined(CONFIG_RELOC_FIXUP_WORKS)
666 gd->reloc_off = 0;
e9514751 667 mem_malloc_end = dest_addr;
f82b3b63 668#else
6d0f6bcf 669 gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
f82b3b63 670#endif
bb105f24
MB
671
672#ifdef CONFIG_SERIAL_MULTI
673 serial_initialize();
674#endif
fe8c2806 675
9d2b18a0 676 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806
WD
677
678 WATCHDOG_RESET ();
679
d025aa4b
BB
680 /*
681 * Setup trap handlers
682 */
683 trap_init (dest_addr);
684
c9315e6b 685#ifdef CONFIG_ADDR_MAP
ecf5b98c
KG
686 init_addr_map();
687#endif
688
c837dcb1
WD
689#if defined(CONFIG_BOARD_EARLY_INIT_R)
690 board_early_init_r ();
691#endif
692
3b57fe0a 693 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806
WD
694
695 /*
696 * We have to relocate the command table manually
697 */
8bde7f77 698 for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
fe8c2806 699 ulong addr;
fe8c2806
WD
700 addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
701#if 0
702 printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
703 cmdtp->name, (ulong) (cmdtp->cmd), addr);
704#endif
705 cmdtp->cmd =
706 (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
707
708 addr = (ulong)(cmdtp->name) + gd->reloc_off;
709 cmdtp->name = (char *)addr;
710
711 if (cmdtp->usage) {
712 addr = (ulong)(cmdtp->usage) + gd->reloc_off;
713 cmdtp->usage = (char *)addr;
714 }
6d0f6bcf 715#ifdef CONFIG_SYS_LONGHELP
fe8c2806
WD
716 if (cmdtp->help) {
717 addr = (ulong)(cmdtp->help) + gd->reloc_off;
718 cmdtp->help = (char *)addr;
719 }
720#endif
721 }
722 /* there are some other pointer constants we must deal with */
93f6d725 723#ifndef CONFIG_ENV_IS_NOWHERE
fe8c2806
WD
724 env_name_spec += gd->reloc_off;
725#endif
726
727 WATCHDOG_RESET ();
728
56f94be3 729#ifdef CONFIG_LOGBUFFER
228f29ac 730 logbuff_init_ptrs ();
56f94be3 731#endif
fe8c2806 732#ifdef CONFIG_POST
228f29ac 733 post_output_backlog ();
fe8c2806
WD
734 post_reloc ();
735#endif
736
737 WATCHDOG_RESET();
738
2688e2f9
KG
739#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
740 defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
fe8c2806
WD
741 icache_enable (); /* it's time to enable the instruction cache */
742#endif
743
6d0f6bcf 744#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
c837dcb1 745 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
746#endif
747
3bac3513 748#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 749 /*
3bac3513
WD
750 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
751 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
752 * bridge there.
fe8c2806
WD
753 */
754 pci_init ();
3bac3513
WD
755#endif
756#if defined(CONFIG_BAB7xx)
fe8c2806
WD
757 /*
758 * Initialise the ISA bridge
759 */
760 initialise_w83c553f ();
761#endif
762
763 asm ("sync ; isync");
764
6d0f6bcf 765#if !defined(CONFIG_SYS_NO_FLASH)
fe8c2806
WD
766 puts ("FLASH: ");
767
768 if ((flash_size = flash_init ()) > 0) {
6d0f6bcf 769# ifdef CONFIG_SYS_FLASH_CHECKSUM
fe8c2806
WD
770 print_size (flash_size, "");
771 /*
772 * Compute and print flash CRC if flashchecksum is set to 'y'
773 *
774 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
775 */
776 s = getenv ("flashchecksum");
777 if (s && (*s == 'y')) {
06c53bea 778 printf (" CRC: %08X",
6d0f6bcf 779 crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
7e780369 780 );
fe8c2806
WD
781 }
782 putc ('\n');
6d0f6bcf 783# else /* !CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806 784 print_size (flash_size, "\n");
6d0f6bcf 785# endif /* CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806
WD
786 } else {
787 puts (failed);
788 hang ();
789 }
790
6d0f6bcf 791 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
fe8c2806 792 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445 793
6d0f6bcf 794#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
fa230445
HS
795 /* Make a update of the Memctrl. */
796 update_flash_size (flash_size);
797#endif
798
799
7e780369
WD
800# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
801 /* flash mapped at end of memory map */
802 bd->bi_flashoffset = TEXT_BASE + flash_size;
6d0f6bcf 803# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
3b57fe0a 804 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 805# else
fe8c2806 806 bd->bi_flashoffset = 0;
0cb61d7d 807# endif
6d0f6bcf 808#else /* CONFIG_SYS_NO_FLASH */
fe8c2806
WD
809
810 bd->bi_flashsize = 0;
811 bd->bi_flashstart = 0;
812 bd->bi_flashoffset = 0;
6d0f6bcf 813#endif /* !CONFIG_SYS_NO_FLASH */
fe8c2806
WD
814
815 WATCHDOG_RESET ();
816
817 /* initialize higher level parts of CPU like time base and timers */
818 cpu_init_r ();
819
820 WATCHDOG_RESET ();
821
822 /* initialize malloc() area */
823 mem_malloc_init ();
824 malloc_bin_reloc ();
825
826#ifdef CONFIG_SPI
bb1f8b4f 827# if !defined(CONFIG_ENV_IS_IN_EEPROM)
fe8c2806
WD
828 spi_init_f ();
829# endif
830 spi_init_r ();
831#endif
832
7def6b34 833#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
834 WATCHDOG_RESET ();
835 puts ("NAND: ");
836 nand_init(); /* go init the NAND */
837#endif
838
fe8c2806
WD
839 /* relocate environment function pointers etc. */
840 env_relocate ();
841
842 /*
843 * Fill in missing fields of bd_info.
8bde7f77
WD
844 * We do this here, where we have "normal" access to the
845 * environment; we used to do this still running from ROM,
846 * where had to use getenv_r(), which can be pretty slow when
847 * the environment is in EEPROM.
fe8c2806 848 */
7abf0c58 849
6d0f6bcf 850#if defined(CONFIG_SYS_EXTBDINFO)
7abf0c58
WD
851#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
852#if defined(CONFIG_I2CFAST)
853 /*
854 * set bi_iic_fast for linux taking environment variable
855 * "i2cfast" into account
856 */
857 {
858 char *s = getenv ("i2cfast");
859 if (s && ((*s == 'y') || (*s == 'Y'))) {
860 bd->bi_iic_fast[0] = 1;
861 bd->bi_iic_fast[1] = 1;
862 } else {
863 bd->bi_iic_fast[0] = 0;
864 bd->bi_iic_fast[1] = 0;
865 }
866 }
867#else
868 bd->bi_iic_fast[0] = 0;
869 bd->bi_iic_fast[1] = 0;
870#endif /* CONFIG_I2CFAST */
871#endif /* CONFIG_405GP, CONFIG_405EP */
6d0f6bcf 872#endif /* CONFIG_SYS_EXTBDINFO */
7abf0c58 873
9045f33c 874#if defined(CONFIG_SC3)
ca43ba18
HS
875 sc3_read_eeprom();
876#endif
d59feffb 877
6d0f6bcf 878#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET)
d59feffb
HW
879 mac_read_from_eeprom();
880#endif
881
fe8c2806 882 s = getenv ("ethaddr");
4707fb50
BS
883#if defined (CONFIG_MBX) || \
884 defined (CONFIG_RPXCLASSIC) || \
885 defined(CONFIG_IAD210) || \
886 defined(CONFIG_V38B)
fe8c2806
WD
887 if (s == NULL)
888 board_get_enetaddr (bd->bi_enetaddr);
889 else
890#endif
891 for (i = 0; i < 6; ++i) {
892 bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
893 if (s)
894 s = (*e) ? e + 1 : e;
895 }
896#ifdef CONFIG_HERMES
897 if ((gd->board_type >> 16) == 2)
898 bd->bi_ethspeed = gd->board_type & 0xFFFF;
899 else
900 bd->bi_ethspeed = 0xFFFF;
901#endif
902
903#ifdef CONFIG_NX823
904 load_sernum_ethaddr ();
905#endif
906
e2ffd59b 907#ifdef CONFIG_HAS_ETH1
fe8c2806
WD
908 /* handle the 2nd ethernet address */
909
910 s = getenv ("eth1addr");
911
912 for (i = 0; i < 6; ++i) {
913 bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
914 if (s)
915 s = (*e) ? e + 1 : e;
916 }
917#endif
e2ffd59b 918#ifdef CONFIG_HAS_ETH2
fe8c2806
WD
919 /* handle the 3rd ethernet address */
920
921 s = getenv ("eth2addr");
b79316f2 922#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
923 if (s == NULL)
924 board_get_enetaddr(bd->bi_enet2addr);
925 else
926#endif
fe8c2806
WD
927 for (i = 0; i < 6; ++i) {
928 bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
929 if (s)
930 s = (*e) ? e + 1 : e;
931 }
932#endif
933
e2ffd59b 934#ifdef CONFIG_HAS_ETH3
ba56f625
WD
935 /* handle 4th ethernet address */
936 s = getenv("eth3addr");
b79316f2 937#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
938 if (s == NULL)
939 board_get_enetaddr(bd->bi_enet3addr);
940 else
941#endif
942 for (i = 0; i < 6; ++i) {
943 bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
944 if (s)
945 s = (*e) ? e + 1 : e;
946 }
947#endif
fe8c2806 948
c68a05fe 949#ifdef CONFIG_HAS_ETH4
950 /* handle 5th ethernet address */
951 s = getenv("eth4addr");
952#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
953 if (s == NULL)
954 board_get_enetaddr(bd->bi_enet4addr);
955 else
956#endif
957 for (i = 0; i < 6; ++i) {
958 bd->bi_enet4addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
959 if (s)
960 s = (*e) ? e + 1 : e;
961 }
962#endif
963
964#ifdef CONFIG_HAS_ETH5
965 /* handle 6th ethernet address */
966 s = getenv("eth5addr");
967#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
968 if (s == NULL)
969 board_get_enetaddr(bd->bi_enet5addr);
970 else
971#endif
972 for (i = 0; i < 6; ++i) {
973 bd->bi_enet5addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
974 if (s)
975 s = (*e) ? e + 1 : e;
976 }
977#endif
978
fe8c2806 979#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
fa230445 980 defined(CONFIG_TQM8272) || \
566a494f
HS
981 defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \
982 defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP)
fe8c2806
WD
983 load_sernum_ethaddr ();
984#endif
985 /* IP Address */
986 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
987
988 WATCHDOG_RESET ();
989
979bdbc7 990#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
991 /*
992 * Do pci configuration
993 */
994 pci_init ();
995#endif
996
997/** leave this here (after malloc(), environment and PCI are working) **/
998 /* Initialize devices */
999 devices_init ();
1000
27b207fd
WD
1001 /* Initialize the jump table for applications */
1002 jumptable_init ();
fe8c2806 1003
500856eb
RJ
1004#if defined(CONFIG_API)
1005 /* Initialize API */
1006 api_init ();
1007#endif
1008
fe8c2806
WD
1009 /* Initialize the console (after the relocation and devices init) */
1010 console_init_r ();
fe8c2806
WD
1011
1012#if defined(CONFIG_CCM) || \
1013 defined(CONFIG_COGENT) || \
1014 defined(CONFIG_CPCI405) || \
1015 defined(CONFIG_EVB64260) || \
56f94be3 1016 defined(CONFIG_KUP4K) || \
0608e04d 1017 defined(CONFIG_KUP4X) || \
fe8c2806
WD
1018 defined(CONFIG_LWMON) || \
1019 defined(CONFIG_PCU_E) || \
9045f33c 1020 defined(CONFIG_SC3) || \
fe8c2806
WD
1021 defined(CONFIG_W7O) || \
1022 defined(CONFIG_MISC_INIT_R)
1023 /* miscellaneous platform dependent initialisations */
1024 misc_init_r ();
1025#endif
1026
1027#ifdef CONFIG_HERMES
1028 if (bd->bi_ethspeed != 0xFFFF)
1029 hermes_start_lxt980 ((int) bd->bi_ethspeed);
1030#endif
1031
7def6b34 1032#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
1033 WATCHDOG_RESET ();
1034 puts ("KGDB: ");
1035 kgdb_init ();
1036#endif
1037
9d2b18a0 1038 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
1039
1040 /*
1041 * Enable Interrupts
1042 */
1043 interrupt_init ();
1044
1045 /* Must happen after interrupts are initialized since
1046 * an irq handler gets installed
1047 */
42dfe7a1 1048#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
1049 serial_buffered_init();
1050#endif
1051
566a494f 1052#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
1053 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
1054#endif
1055
1056 udelay (20);
1057
1058 set_timer (0);
1059
fe8c2806
WD
1060 /* Initialize from environment */
1061 if ((s = getenv ("loadaddr")) != NULL) {
1062 load_addr = simple_strtoul (s, NULL, 16);
1063 }
7def6b34 1064#if defined(CONFIG_CMD_NET)
fe8c2806
WD
1065 if ((s = getenv ("bootfile")) != NULL) {
1066 copy_filename (BootFile, s, sizeof (BootFile));
1067 }
b3aff0cb 1068#endif
fe8c2806
WD
1069
1070 WATCHDOG_RESET ();
1071
7def6b34 1072#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
1073 WATCHDOG_RESET ();
1074 puts ("SCSI: ");
1075 scsi_init ();
1076#endif
1077
7def6b34 1078#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
1079 WATCHDOG_RESET ();
1080 puts ("DOC: ");
1081 doc_init ();
1082#endif
1083
7def6b34 1084#if defined(CONFIG_CMD_NET)
63ff004c 1085#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
1086 WATCHDOG_RESET ();
1087 puts ("Net: ");
63ff004c 1088#endif
fe8c2806
WD
1089 eth_initialize (bd);
1090#endif
1091
7def6b34 1092#if defined(CONFIG_CMD_NET) && ( \
63ff004c
MB
1093 defined(CONFIG_CCM) || \
1094 defined(CONFIG_ELPT860) || \
1095 defined(CONFIG_EP8260) || \
1096 defined(CONFIG_IP860) || \
1097 defined(CONFIG_IVML24) || \
1098 defined(CONFIG_IVMS8) || \
1099 defined(CONFIG_MPC8260ADS) || \
1100 defined(CONFIG_MPC8266ADS) || \
1101 defined(CONFIG_MPC8560ADS) || \
1102 defined(CONFIG_PCU_E) || \
1103 defined(CONFIG_RPXSUPER) || \
1104 defined(CONFIG_STXGP3) || \
1105 defined(CONFIG_SPD823TS) || \
1106 defined(CONFIG_RESET_PHY_R) )
1107
1108 WATCHDOG_RESET ();
1109 debug ("Reset Ethernet PHY\n");
1110 reset_phy ();
1111#endif
1112
fe8c2806 1113#ifdef CONFIG_POST
6dff5529 1114 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
1115#endif
1116
7def6b34
JL
1117#if defined(CONFIG_CMD_PCMCIA) \
1118 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
1119 WATCHDOG_RESET ();
1120 puts ("PCMCIA:");
1121 pcmcia_init ();
1122#endif
1123
7def6b34 1124#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
1125 WATCHDOG_RESET ();
1126# ifdef CONFIG_IDE_8xx_PCCARD
1127 puts ("PCMCIA:");
1128# else
1129 puts ("IDE: ");
1130#endif
ca43ba18
HS
1131#if defined(CONFIG_START_IDE)
1132 if (board_start_ide())
1133 ide_init ();
1134#else
fe8c2806 1135 ide_init ();
ca43ba18 1136#endif
b3aff0cb 1137#endif
fe8c2806
WD
1138
1139#ifdef CONFIG_LAST_STAGE_INIT
1140 WATCHDOG_RESET ();
1141 /*
1142 * Some parts can be only initialized if all others (like
1143 * Interrupts) are up and running (i.e. the PC-style ISA
1144 * keyboard).
1145 */
1146 last_stage_init ();
1147#endif
1148
7def6b34 1149#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1150 WATCHDOG_RESET ();
1151 bedbug_init ();
1152#endif
1153
228f29ac 1154#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1155 /*
1156 * Export available size of memory for Linux,
1157 * taking into account the protected RAM at top of memory
1158 */
1159 {
1160 ulong pram;
fe8c2806 1161 uchar memsz[32];
228f29ac
WD
1162#ifdef CONFIG_PRAM
1163 char *s;
fe8c2806
WD
1164
1165 if ((s = getenv ("pram")) != NULL) {
1166 pram = simple_strtoul (s, NULL, 10);
1167 } else {
1168 pram = CONFIG_PRAM;
1169 }
228f29ac
WD
1170#else
1171 pram=0;
1172#endif
1173#ifdef CONFIG_LOGBUFFER
3d610186 1174#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1175 /* Also take the logbuffer into account (pram is in kB) */
1176 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1177#endif
228f29ac 1178#endif
77ddac94
WD
1179 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1180 setenv ("mem", (char *)memsz);
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1181 }
1182#endif
1183
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1184#ifdef CONFIG_PS2KBD
1185 puts ("PS/2: ");
1186 kbd_init();
1187#endif
1188
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1189#ifdef CONFIG_MODEM_SUPPORT
1190 {
1191 extern int do_mdm_init;
1192 do_mdm_init = gd->do_mdm_init;
1193 }
1194#endif
1195
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1196 /* Initialization complete - start the monitor */
1197
1198 /* main_loop() can return to retry autoboot, if so just run it again. */
1199 for (;;) {
1200 WATCHDOG_RESET ();
1201 main_loop ();
1202 }
1203
1204 /* NOTREACHED - no way out of command loop except booting */
1205}
1206
1207void hang (void)
1208{
1209 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1210 show_boot_progress(-30);
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1211 for (;;);
1212}
1213
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1214#ifdef CONFIG_MODEM_SUPPORT
1215/* called from main loop (common/main.c) */
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1216/* 'inline' - We have to do it fast */
1217static inline void mdm_readline(char *buf, int bufsiz)
1218{
1219 char c;
1220 char *p;
1221 int n;
1222
1223 n = 0;
1224 p = buf;
1225 for(;;) {
1226 c = serial_getc();
1227
1228 /* dbg("(%c)", c); */
1229
1230 switch(c) {
1231 case '\r':
1232 break;
1233 case '\n':
1234 *p = '\0';
1235 return;
1236
1237 default:
1238 if(n++ > bufsiz) {
1239 *p = '\0';
1240 return; /* sanity check */
1241 }
1242 *p = c;
1243 p++;
1244 break;
1245 }
1246 }
1247}
1248
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1249extern void dbg(const char *fmt, ...);
1250int mdm_init (void)
1251{
1252 char env_str[16];
1253 char *init_str;
1254 int i;
1255 extern char console_buffer[];
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1256 extern void enable_putc(void);
1257 extern int hwflow_onoff(int);
1258
1259 enable_putc(); /* enable serial_putc() */
1260
1261#ifdef CONFIG_HWFLOW
1262 init_str = getenv("mdm_flow_control");
1263 if (init_str && (strcmp(init_str, "rts/cts") == 0))
1264 hwflow_onoff (1);
1265 else
1266 hwflow_onoff(-1);
1267#endif
1268
1269 for (i = 1;;i++) {
1270 sprintf(env_str, "mdm_init%d", i);
1271 if ((init_str = getenv(env_str)) != NULL) {
1272 serial_puts(init_str);
1273 serial_puts("\n");
1274 for(;;) {
6d0f6bcf 1275 mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
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1276 dbg("ini%d: [%s]", i, console_buffer);
1277
1278 if ((strcmp(console_buffer, "OK") == 0) ||
1279 (strcmp(console_buffer, "ERROR") == 0)) {
1280 dbg("ini%d: cmd done", i);
1281 break;
1282 } else /* in case we are originating call ... */
1283 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1284 dbg("ini%d: connect", i);
1285 return 0;
1286 }
1287 }
1288 } else
1289 break; /* no init string - stop modem init */
1290
1291 udelay(100000);
1292 }
1293
1294 udelay(100000);
1295
1296 /* final stage - wait for connect */
1297 for(;i > 1;) { /* if 'i' > 1 - wait for connection
1298 message from modem */
6d0f6bcf 1299 mdm_readline(console_buffer, CONFIG_SYS_CBSIZE);
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1300 dbg("ini_f: [%s]", console_buffer);
1301 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1302 dbg("ini_f: connected");
1303 return 0;
1304 }
1305 }
1306
1307 return 0;
1308}
1309
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1310#endif
1311
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1312#if 0 /* We could use plain global data, but the resulting code is bigger */
1313/*
1314 * Pointer to initial global data area
1315 *
1316 * Here we initialize it.
1317 */
1318#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1319#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
6d0f6bcf 1320DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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1321#endif /* 0 */
1322
1323/************************************************************************/