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fe8c2806 | 1 | /* |
4707fb50 | 2 | * (C) Copyright 2000-2006 |
fe8c2806 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <watchdog.h> | |
26 | #include <command.h> | |
27 | #include <malloc.h> | |
28 | #include <devices.h> | |
fe8c2806 WD |
29 | #ifdef CONFIG_8xx |
30 | #include <mpc8xx.h> | |
31 | #endif | |
0db5bca8 WD |
32 | #ifdef CONFIG_5xx |
33 | #include <mpc5xx.h> | |
34 | #endif | |
cbd8a35c | 35 | #ifdef CONFIG_MPC5xxx |
945af8d7 WD |
36 | #include <mpc5xxx.h> |
37 | #endif | |
7def6b34 | 38 | #if defined(CONFIG_CMD_IDE) |
fe8c2806 WD |
39 | #include <ide.h> |
40 | #endif | |
cd54081c DL |
41 | #if defined(CONFIG_CMD_SATA) |
42 | #include <sata.h> | |
43 | #endif | |
7def6b34 | 44 | #if defined(CONFIG_CMD_SCSI) |
fe8c2806 WD |
45 | #include <scsi.h> |
46 | #endif | |
7def6b34 | 47 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
48 | #include <kgdb.h> |
49 | #endif | |
50 | #ifdef CONFIG_STATUS_LED | |
51 | #include <status_led.h> | |
52 | #endif | |
53 | #include <net.h> | |
281e00a3 | 54 | #include <serial.h> |
fe8c2806 | 55 | #ifdef CFG_ALLOC_DPRAM |
9c4c5ae3 | 56 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
57 | #include <commproc.h> |
58 | #endif | |
7aa78614 | 59 | #endif |
fe8c2806 WD |
60 | #include <version.h> |
61 | #if defined(CONFIG_BAB7xx) | |
62 | #include <w83c553f.h> | |
63 | #endif | |
64 | #include <dtt.h> | |
65 | #if defined(CONFIG_POST) | |
66 | #include <post.h> | |
67 | #endif | |
56f94be3 WD |
68 | #if defined(CONFIG_LOGBUFFER) |
69 | #include <logbuff.h> | |
70 | #endif | |
42d1f039 WD |
71 | #if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) |
72 | #include <asm/cache.h> | |
73 | #endif | |
1c43771b WD |
74 | #ifdef CONFIG_PS2KBD |
75 | #include <keyboard.h> | |
76 | #endif | |
fe8c2806 | 77 | |
fa230445 HS |
78 | #ifdef CFG_UPDATE_FLASH_SIZE |
79 | extern int update_flash_size (int flash_size); | |
80 | #endif | |
81 | ||
9045f33c | 82 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
83 | extern void sc3_read_eeprom(void); |
84 | #endif | |
85 | ||
7def6b34 | 86 | #if defined(CONFIG_CMD_DOC) |
fe8c2806 WD |
87 | void doc_init (void); |
88 | #endif | |
89 | #if defined(CONFIG_HARD_I2C) || \ | |
90 | defined(CONFIG_SOFT_I2C) | |
91 | #include <i2c.h> | |
92 | #endif | |
04a9e118 BW |
93 | #if defined(CONFIG_HARD_SPI) |
94 | #include <spi.h> | |
95 | #endif | |
7def6b34 | 96 | #if defined(CONFIG_CMD_NAND) |
bedc4970 SR |
97 | void nand_init (void); |
98 | #endif | |
fe8c2806 WD |
99 | |
100 | static char *failed = "*** failed ***\n"; | |
101 | ||
17d704eb | 102 | #if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU) |
fe8c2806 | 103 | extern flash_info_t flash_info[]; |
17d704eb | 104 | #endif |
fe8c2806 | 105 | |
ca43ba18 HS |
106 | #if defined(CONFIG_START_IDE) |
107 | extern int board_start_ide(void); | |
108 | #endif | |
fe8c2806 | 109 | #include <environment.h> |
d87080b7 | 110 | |
bce84c4d | 111 | DECLARE_GLOBAL_DATA_PTR; |
fe8c2806 | 112 | |
7e780369 WD |
113 | #if defined(CFG_ENV_IS_EMBEDDED) |
114 | #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN | |
115 | #elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ | |
04a85b3b | 116 | (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ |
7e780369 | 117 | defined(CFG_ENV_IS_IN_NVRAM) |
fe8c2806 WD |
118 | #define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) |
119 | #else | |
120 | #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN | |
121 | #endif | |
122 | ||
6fb4b640 SR |
123 | #if !defined(CFG_MEM_TOP_HIDE) |
124 | #define CFG_MEM_TOP_HIDE 0 | |
125 | #endif | |
126 | ||
3b57fe0a WD |
127 | extern ulong __init_end; |
128 | extern ulong _end; | |
3b57fe0a WD |
129 | ulong monitor_flash_len; |
130 | ||
7def6b34 | 131 | #if defined(CONFIG_CMD_BEDBUG) |
8bde7f77 WD |
132 | #include <bedbug/type.h> |
133 | #endif | |
134 | ||
fe8c2806 WD |
135 | /* |
136 | * Begin and End of memory area for malloc(), and current "brk" | |
137 | */ | |
138 | static ulong mem_malloc_start = 0; | |
139 | static ulong mem_malloc_end = 0; | |
140 | static ulong mem_malloc_brk = 0; | |
141 | ||
142 | /************************************************************************ | |
143 | * Utilities * | |
144 | ************************************************************************ | |
145 | */ | |
146 | ||
147 | /* | |
148 | * The Malloc area is immediately below the monitor copy in DRAM | |
149 | */ | |
150 | static void mem_malloc_init (void) | |
151 | { | |
e9514751 SR |
152 | #if !defined(CONFIG_RELOC_FIXUP_WORKS) |
153 | mem_malloc_end = CFG_MONITOR_BASE + gd->reloc_off; | |
154 | #endif | |
155 | mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN; | |
fe8c2806 WD |
156 | mem_malloc_brk = mem_malloc_start; |
157 | ||
158 | memset ((void *) mem_malloc_start, | |
159 | 0, | |
160 | mem_malloc_end - mem_malloc_start); | |
161 | } | |
162 | ||
163 | void *sbrk (ptrdiff_t increment) | |
164 | { | |
165 | ulong old = mem_malloc_brk; | |
166 | ulong new = old + increment; | |
167 | ||
168 | if ((new < mem_malloc_start) || (new > mem_malloc_end)) { | |
169 | return (NULL); | |
170 | } | |
171 | mem_malloc_brk = new; | |
172 | return ((void *) old); | |
173 | } | |
174 | ||
175 | char *strmhz (char *buf, long hz) | |
176 | { | |
177 | long l, n; | |
178 | long m; | |
179 | ||
180 | n = hz / 1000000L; | |
181 | l = sprintf (buf, "%ld", n); | |
182 | m = (hz % 1000000L) / 1000L; | |
183 | if (m != 0) | |
184 | sprintf (buf + l, ".%03ld", m); | |
185 | return (buf); | |
186 | } | |
187 | ||
fe8c2806 WD |
188 | /* |
189 | * All attempts to come up with a "common" initialization sequence | |
190 | * that works for all boards and architectures failed: some of the | |
191 | * requirements are just _too_ different. To get rid of the resulting | |
192 | * mess of board dependend #ifdef'ed code we now make the whole | |
193 | * initialization sequence configurable to the user. | |
194 | * | |
195 | * The requirements for any new initalization function is simple: it | |
196 | * receives a pointer to the "global data" structure as it's only | |
197 | * argument, and returns an integer return code, where 0 means | |
198 | * "continue" and != 0 means "fatal error, hang the system". | |
199 | */ | |
200 | typedef int (init_fnc_t) (void); | |
201 | ||
202 | /************************************************************************ | |
203 | * Init Utilities * | |
204 | ************************************************************************ | |
205 | * Some of this code should be moved into the core functions, | |
206 | * but let's get it working (again) first... | |
207 | */ | |
208 | ||
209 | static int init_baudrate (void) | |
210 | { | |
77ddac94 | 211 | char tmp[64]; /* long enough for environment variables */ |
fe8c2806 WD |
212 | int i = getenv_r ("baudrate", tmp, sizeof (tmp)); |
213 | ||
214 | gd->baudrate = (i > 0) | |
215 | ? (int) simple_strtoul (tmp, NULL, 10) | |
216 | : CONFIG_BAUDRATE; | |
fe8c2806 WD |
217 | return (0); |
218 | } | |
219 | ||
220 | /***********************************************************************/ | |
221 | ||
79f240f7 KP |
222 | void __board_add_ram_info(int use_default) |
223 | { | |
224 | /* please define platform specific board_add_ram_info() */ | |
225 | } | |
226 | void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info"))); | |
227 | ||
d96f41e0 | 228 | |
fe8c2806 WD |
229 | static int init_func_ram (void) |
230 | { | |
fe8c2806 WD |
231 | #ifdef CONFIG_BOARD_TYPES |
232 | int board_type = gd->board_type; | |
233 | #else | |
234 | int board_type = 0; /* use dummy arg */ | |
235 | #endif | |
236 | puts ("DRAM: "); | |
237 | ||
238 | if ((gd->ram_size = initdram (board_type)) > 0) { | |
d96f41e0 | 239 | print_size (gd->ram_size, ""); |
d96f41e0 | 240 | board_add_ram_info(0); |
d96f41e0 | 241 | putc('\n'); |
fe8c2806 WD |
242 | return (0); |
243 | } | |
244 | puts (failed); | |
245 | return (1); | |
246 | } | |
247 | ||
248 | /***********************************************************************/ | |
249 | ||
250 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) | |
251 | static int init_func_i2c (void) | |
252 | { | |
253 | puts ("I2C: "); | |
254 | i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); | |
255 | puts ("ready\n"); | |
256 | return (0); | |
257 | } | |
258 | #endif | |
259 | ||
04a9e118 BW |
260 | #if defined(CONFIG_HARD_SPI) |
261 | static int init_func_spi (void) | |
262 | { | |
263 | puts ("SPI: "); | |
264 | spi_init (); | |
265 | puts ("ready\n"); | |
266 | return (0); | |
267 | } | |
268 | #endif | |
269 | ||
fe8c2806 WD |
270 | /***********************************************************************/ |
271 | ||
272 | #if defined(CONFIG_WATCHDOG) | |
273 | static int init_func_watchdog_init (void) | |
274 | { | |
275 | puts (" Watchdog enabled\n"); | |
276 | WATCHDOG_RESET (); | |
277 | return (0); | |
278 | } | |
279 | # define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, | |
280 | ||
281 | static int init_func_watchdog_reset (void) | |
282 | { | |
283 | WATCHDOG_RESET (); | |
284 | return (0); | |
285 | } | |
286 | # define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, | |
287 | #else | |
288 | # define INIT_FUNC_WATCHDOG_INIT /* undef */ | |
289 | # define INIT_FUNC_WATCHDOG_RESET /* undef */ | |
290 | #endif /* CONFIG_WATCHDOG */ | |
291 | ||
292 | /************************************************************************ | |
293 | * Initialization sequence * | |
294 | ************************************************************************ | |
295 | */ | |
296 | ||
297 | init_fnc_t *init_sequence[] = { | |
298 | ||
c837dcb1 WD |
299 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
300 | board_early_init_f, | |
fe8c2806 | 301 | #endif |
c178d3da | 302 | |
66ca92a5 | 303 | #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) |
fe8c2806 | 304 | get_clocks, /* get CPU and bus clocks (etc.) */ |
090eb735 MK |
305 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ |
306 | && !defined(CONFIG_TQM885D) | |
e9132ea9 WD |
307 | adjust_sdram_tbs_8xx, |
308 | #endif | |
fe8c2806 | 309 | init_timebase, |
c178d3da | 310 | #endif |
fe8c2806 | 311 | #ifdef CFG_ALLOC_DPRAM |
9c4c5ae3 | 312 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
313 | dpram_init, |
314 | #endif | |
7aa78614 | 315 | #endif |
fe8c2806 WD |
316 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
317 | board_postclk_init, | |
318 | #endif | |
319 | env_init, | |
66ca92a5 | 320 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
c178d3da WD |
321 | get_clocks_866, /* get CPU and bus clocks according to the environment variable */ |
322 | sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */ | |
323 | init_timebase, | |
324 | #endif | |
fe8c2806 WD |
325 | init_baudrate, |
326 | serial_init, | |
327 | console_init_f, | |
328 | display_options, | |
329 | #if defined(CONFIG_8260) | |
330 | prt_8260_rsr, | |
331 | prt_8260_clks, | |
332 | #endif /* CONFIG_8260 */ | |
9be39a67 DL |
333 | #if defined(CONFIG_MPC83XX) |
334 | prt_83xx_rsr, | |
335 | #endif | |
fe8c2806 | 336 | checkcpu, |
cbd8a35c | 337 | #if defined(CONFIG_MPC5xxx) |
945af8d7 | 338 | prt_mpc5xxx_clks, |
cbd8a35c | 339 | #endif /* CONFIG_MPC5xxx */ |
983fda83 WD |
340 | #if defined(CONFIG_MPC8220) |
341 | prt_mpc8220_clks, | |
342 | #endif | |
fe8c2806 WD |
343 | checkboard, |
344 | INIT_FUNC_WATCHDOG_INIT | |
c837dcb1 | 345 | #if defined(CONFIG_MISC_INIT_F) |
fe8c2806 WD |
346 | misc_init_f, |
347 | #endif | |
348 | INIT_FUNC_WATCHDOG_RESET | |
349 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) | |
350 | init_func_i2c, | |
351 | #endif | |
04a9e118 BW |
352 | #if defined(CONFIG_HARD_SPI) |
353 | init_func_spi, | |
354 | #endif | |
fe8c2806 WD |
355 | #if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */ |
356 | dtt_init, | |
4532cb69 WD |
357 | #endif |
358 | #ifdef CONFIG_POST | |
359 | post_init_f, | |
fe8c2806 WD |
360 | #endif |
361 | INIT_FUNC_WATCHDOG_RESET | |
362 | init_func_ram, | |
363 | #if defined(CFG_DRAM_TEST) | |
364 | testdram, | |
365 | #endif /* CFG_DRAM_TEST */ | |
366 | INIT_FUNC_WATCHDOG_RESET | |
367 | ||
368 | NULL, /* Terminate this list */ | |
369 | }; | |
370 | ||
81d93e5c KG |
371 | #ifndef CONFIG_MAX_MEM_MAPPED |
372 | #define CONFIG_MAX_MEM_MAPPED (256 << 20) | |
373 | #endif | |
374 | ulong get_effective_memsize(void) | |
375 | { | |
376 | #ifndef CONFIG_VERY_BIG_RAM | |
377 | return gd->ram_size; | |
378 | #else | |
379 | /* limit stack to what we can reasonable map */ | |
380 | return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? | |
381 | CONFIG_MAX_MEM_MAPPED : gd->ram_size); | |
382 | #endif | |
383 | } | |
384 | ||
fe8c2806 WD |
385 | /************************************************************************ |
386 | * | |
387 | * This is the first part of the initialization sequence that is | |
388 | * implemented in C, but still running from ROM. | |
389 | * | |
390 | * The main purpose is to provide a (serial) console interface as | |
391 | * soon as possible (so we can see any error messages), and to | |
392 | * initialize the RAM so that we can relocate the monitor code to | |
393 | * RAM. | |
394 | * | |
395 | * Be aware of the restrictions: global data is read-only, BSS is not | |
396 | * initialized, and stack space is limited to a few kB. | |
397 | * | |
398 | ************************************************************************ | |
399 | */ | |
400 | ||
401 | void board_init_f (ulong bootflag) | |
402 | { | |
fe8c2806 WD |
403 | bd_t *bd; |
404 | ulong len, addr, addr_sp; | |
7bc5ee07 | 405 | ulong *s; |
fe8c2806 WD |
406 | gd_t *id; |
407 | init_fnc_t **init_fnc_ptr; | |
408 | #ifdef CONFIG_PRAM | |
409 | int i; | |
410 | ulong reg; | |
411 | uchar tmp[64]; /* long enough for environment variables */ | |
412 | #endif | |
413 | ||
414 | /* Pointer is writable since we allocated a register for it */ | |
415 | gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); | |
93f6a677 WD |
416 | /* compiler optimization barrier needed for GCC >= 3.4 */ |
417 | __asm__ __volatile__("": : :"memory"); | |
fe8c2806 | 418 | |
9be39a67 | 419 | #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) |
fe8c2806 WD |
420 | /* Clear initial global data */ |
421 | memset ((void *) gd, 0, sizeof (gd_t)); | |
422 | #endif | |
423 | ||
424 | for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { | |
425 | if ((*init_fnc_ptr) () != 0) { | |
426 | hang (); | |
427 | } | |
428 | } | |
429 | ||
430 | /* | |
431 | * Now that we have DRAM mapped and working, we can | |
432 | * relocate the code and continue running from DRAM. | |
433 | * | |
434 | * Reserve memory at end of RAM for (top down in that order): | |
14f73ca6 | 435 | * - area that won't get touched by U-Boot and Linux (optional) |
8bde7f77 | 436 | * - kernel log buffer |
fe8c2806 WD |
437 | * - protected RAM |
438 | * - LCD framebuffer | |
439 | * - monitor code | |
440 | * - board info struct | |
441 | */ | |
dfc6c7b6 | 442 | len = (ulong)&_end - CFG_MONITOR_BASE; |
fe8c2806 | 443 | |
14f73ca6 SR |
444 | /* |
445 | * Subtract specified amount of memory to hide so that it won't | |
446 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
447 | * the Linux kernel should now get passed the now "corrected" | |
448 | * memory size and won't touch it either. This should work | |
449 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
450 | * arch/powerpc with bootwrapper support, that recalculate the | |
451 | * memory size from the SDRAM controller setup will have to | |
452 | * get fixed. | |
453 | */ | |
454 | gd->ram_size -= CFG_MEM_TOP_HIDE; | |
455 | ||
81d93e5c | 456 | addr = CFG_SDRAM_BASE + get_effective_memsize(); |
fe8c2806 | 457 | |
228f29ac | 458 | #ifdef CONFIG_LOGBUFFER |
3d610186 | 459 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac WD |
460 | /* reserve kernel log buffer */ |
461 | addr -= (LOGBUFF_RESERVE); | |
9d2b18a0 | 462 | debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); |
228f29ac | 463 | #endif |
3d610186 | 464 | #endif |
228f29ac | 465 | |
fe8c2806 WD |
466 | #ifdef CONFIG_PRAM |
467 | /* | |
468 | * reserve protected RAM | |
469 | */ | |
77ddac94 WD |
470 | i = getenv_r ("pram", (char *)tmp, sizeof (tmp)); |
471 | reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM; | |
fe8c2806 | 472 | addr -= (reg << 10); /* size is in kB */ |
9d2b18a0 | 473 | debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); |
fe8c2806 WD |
474 | #endif /* CONFIG_PRAM */ |
475 | ||
476 | /* round down to next 4 kB limit */ | |
477 | addr &= ~(4096 - 1); | |
9d2b18a0 | 478 | debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); |
fe8c2806 WD |
479 | |
480 | #ifdef CONFIG_LCD | |
481 | /* reserve memory for LCD display (always full pages) */ | |
482 | addr = lcd_setmem (addr); | |
483 | gd->fb_base = addr; | |
484 | #endif /* CONFIG_LCD */ | |
485 | ||
486 | #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) | |
487 | /* reserve memory for video display (always full pages) */ | |
488 | addr = video_setmem (addr); | |
489 | gd->fb_base = addr; | |
490 | #endif /* CONFIG_VIDEO */ | |
491 | ||
492 | /* | |
493 | * reserve memory for U-Boot code, data & bss | |
682011ff | 494 | * round down to next 4 kB limit |
fe8c2806 WD |
495 | */ |
496 | addr -= len; | |
682011ff | 497 | addr &= ~(4096 - 1); |
7d314992 WD |
498 | #ifdef CONFIG_E500 |
499 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
500 | addr &= ~(65536 - 1); | |
501 | #endif | |
fe8c2806 | 502 | |
9d2b18a0 | 503 | debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); |
fe8c2806 | 504 | |
c7de829c WD |
505 | #ifdef CONFIG_AMIGAONEG3SE |
506 | gd->relocaddr = addr; | |
507 | #endif | |
508 | ||
fe8c2806 WD |
509 | /* |
510 | * reserve memory for malloc() arena | |
511 | */ | |
512 | addr_sp = addr - TOTAL_MALLOC_LEN; | |
9d2b18a0 | 513 | debug ("Reserving %dk for malloc() at: %08lx\n", |
fe8c2806 | 514 | TOTAL_MALLOC_LEN >> 10, addr_sp); |
fe8c2806 WD |
515 | |
516 | /* | |
517 | * (permanently) allocate a Board Info struct | |
518 | * and a permanent copy of the "global" data | |
519 | */ | |
520 | addr_sp -= sizeof (bd_t); | |
521 | bd = (bd_t *) addr_sp; | |
522 | gd->bd = bd; | |
9d2b18a0 | 523 | debug ("Reserving %d Bytes for Board Info at: %08lx\n", |
fe8c2806 | 524 | sizeof (bd_t), addr_sp); |
fe8c2806 WD |
525 | addr_sp -= sizeof (gd_t); |
526 | id = (gd_t *) addr_sp; | |
9d2b18a0 | 527 | debug ("Reserving %d Bytes for Global Data at: %08lx\n", |
fe8c2806 | 528 | sizeof (gd_t), addr_sp); |
fe8c2806 WD |
529 | |
530 | /* | |
531 | * Finally, we set up a new (bigger) stack. | |
532 | * | |
533 | * Leave some safety gap for SP, force alignment on 16 byte boundary | |
534 | * Clear initial stack frame | |
535 | */ | |
536 | addr_sp -= 16; | |
537 | addr_sp &= ~0xF; | |
7bc5ee07 WD |
538 | s = (ulong *)addr_sp; |
539 | *s-- = 0; | |
540 | *s-- = 0; | |
541 | addr_sp = (ulong)s; | |
9d2b18a0 | 542 | debug ("Stack Pointer at: %08lx\n", addr_sp); |
fe8c2806 WD |
543 | |
544 | /* | |
545 | * Save local variables to board info struct | |
546 | */ | |
547 | ||
c837dcb1 | 548 | bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ |
fe8c2806 WD |
549 | bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ |
550 | ||
551 | #ifdef CONFIG_IP860 | |
c837dcb1 WD |
552 | bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */ |
553 | bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */ | |
983fda83 WD |
554 | #elif defined CONFIG_MPC8220 |
555 | bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */ | |
556 | bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */ | |
fe8c2806 | 557 | #else |
c837dcb1 WD |
558 | bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */ |
559 | bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */ | |
fe8c2806 WD |
560 | #endif |
561 | ||
42d1f039 | 562 | #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ |
debb7354 | 563 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
fe8c2806 WD |
564 | bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */ |
565 | #endif | |
cbd8a35c | 566 | #if defined(CONFIG_MPC5xxx) |
945af8d7 WD |
567 | bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ |
568 | #endif | |
f046ccd1 | 569 | #if defined(CONFIG_MPC83XX) |
d239d74b | 570 | bd->bi_immrbar = CFG_IMMR; |
f046ccd1 | 571 | #endif |
983fda83 WD |
572 | #if defined(CONFIG_MPC8220) |
573 | bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ | |
574 | bd->bi_inpfreq = gd->inp_clk; | |
575 | bd->bi_pcifreq = gd->pci_clk; | |
576 | bd->bi_vcofreq = gd->vco_clk; | |
577 | bd->bi_pevfreq = gd->pev_clk; | |
578 | bd->bi_flbfreq = gd->flb_clk; | |
579 | ||
dd520bf3 WD |
580 | /* store bootparam to sram (backward compatible), here? */ |
581 | { | |
582 | u32 *sram = (u32 *)CFG_SRAM_BASE; | |
583 | *sram++ = gd->ram_size; | |
584 | *sram++ = gd->bus_clk; | |
585 | *sram++ = gd->inp_clk; | |
586 | *sram++ = gd->cpu_clk; | |
587 | *sram++ = gd->vco_clk; | |
588 | *sram++ = gd->flb_clk; | |
589 | *sram++ = 0xb8c3ba11; /* boot signature */ | |
590 | } | |
983fda83 | 591 | #endif |
fe8c2806 WD |
592 | |
593 | bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ | |
594 | ||
595 | WATCHDOG_RESET (); | |
596 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
597 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
9c4c5ae3 | 598 | #if defined(CONFIG_CPM2) |
fe8c2806 WD |
599 | bd->bi_cpmfreq = gd->cpm_clk; |
600 | bd->bi_brgfreq = gd->brg_clk; | |
601 | bd->bi_sccfreq = gd->scc_clk; | |
602 | bd->bi_vco = gd->vco_out; | |
9c4c5ae3 | 603 | #endif /* CONFIG_CPM2 */ |
281ff9a4 | 604 | #if defined(CONFIG_MPC512X) |
5d49e0e1 | 605 | bd->bi_ipsfreq = gd->ips_clk; |
281ff9a4 | 606 | #endif /* CONFIG_MPC512X */ |
cbd8a35c | 607 | #if defined(CONFIG_MPC5xxx) |
945af8d7 WD |
608 | bd->bi_ipbfreq = gd->ipb_clk; |
609 | bd->bi_pcifreq = gd->pci_clk; | |
cbd8a35c | 610 | #endif /* CONFIG_MPC5xxx */ |
fe8c2806 WD |
611 | bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ |
612 | ||
613 | #ifdef CFG_EXTBDINFO | |
77ddac94 WD |
614 | strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); |
615 | strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); | |
fe8c2806 WD |
616 | |
617 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
618 | bd->bi_plb_busfreq = gd->bus_clk; | |
343c48bd SR |
619 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ |
620 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
621 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
fe8c2806 | 622 | bd->bi_pci_busfreq = get_PCI_freq (); |
109c0e3a | 623 | bd->bi_opbfreq = get_OPB_freq (); |
028ab6b5 WD |
624 | #elif defined(CONFIG_XILINX_ML300) |
625 | bd->bi_pci_busfreq = get_PCI_freq (); | |
fe8c2806 WD |
626 | #endif |
627 | #endif | |
628 | ||
9d2b18a0 | 629 | debug ("New Stack Pointer is: %08lx\n", addr_sp); |
fe8c2806 WD |
630 | |
631 | WATCHDOG_RESET (); | |
632 | ||
633 | #ifdef CONFIG_POST | |
634 | post_bootmode_init(); | |
6dff5529 | 635 | post_run (NULL, POST_ROM | post_bootmode_get(0)); |
fe8c2806 WD |
636 | #endif |
637 | ||
638 | WATCHDOG_RESET(); | |
639 | ||
27b207fd | 640 | memcpy (id, (void *)gd, sizeof (gd_t)); |
fe8c2806 WD |
641 | |
642 | relocate_code (addr_sp, id, addr); | |
643 | ||
644 | /* NOTREACHED - relocate_code() does not return */ | |
645 | } | |
646 | ||
fe8c2806 WD |
647 | /************************************************************************ |
648 | * | |
649 | * This is the next part if the initialization sequence: we are now | |
650 | * running from RAM and have a "normal" C environment, i. e. global | |
651 | * data can be written, BSS has been cleared, the stack size in not | |
652 | * that critical any more, etc. | |
653 | * | |
654 | ************************************************************************ | |
655 | */ | |
fe8c2806 WD |
656 | void board_init_r (gd_t *id, ulong dest_addr) |
657 | { | |
fe8c2806 WD |
658 | cmd_tbl_t *cmdtp; |
659 | char *s, *e; | |
660 | bd_t *bd; | |
661 | int i; | |
662 | extern void malloc_bin_reloc (void); | |
663 | #ifndef CFG_ENV_IS_NOWHERE | |
664 | extern char * env_name_spec; | |
665 | #endif | |
666 | ||
667 | #ifndef CFG_NO_FLASH | |
668 | ulong flash_size; | |
669 | #endif | |
670 | ||
671 | gd = id; /* initialize RAM version of global data */ | |
672 | bd = gd->bd; | |
673 | ||
674 | gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ | |
f82b3b63 GL |
675 | |
676 | #if defined(CONFIG_RELOC_FIXUP_WORKS) | |
677 | gd->reloc_off = 0; | |
e9514751 | 678 | mem_malloc_end = dest_addr; |
f82b3b63 | 679 | #else |
bb105f24 | 680 | gd->reloc_off = dest_addr - CFG_MONITOR_BASE; |
f82b3b63 | 681 | #endif |
bb105f24 MB |
682 | |
683 | #ifdef CONFIG_SERIAL_MULTI | |
684 | serial_initialize(); | |
685 | #endif | |
fe8c2806 | 686 | |
9d2b18a0 | 687 | debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); |
fe8c2806 WD |
688 | |
689 | WATCHDOG_RESET (); | |
690 | ||
c837dcb1 WD |
691 | #if defined(CONFIG_BOARD_EARLY_INIT_R) |
692 | board_early_init_r (); | |
693 | #endif | |
694 | ||
3b57fe0a | 695 | monitor_flash_len = (ulong)&__init_end - dest_addr; |
fe8c2806 WD |
696 | |
697 | /* | |
698 | * We have to relocate the command table manually | |
699 | */ | |
8bde7f77 | 700 | for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { |
fe8c2806 | 701 | ulong addr; |
fe8c2806 WD |
702 | addr = (ulong) (cmdtp->cmd) + gd->reloc_off; |
703 | #if 0 | |
704 | printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", | |
705 | cmdtp->name, (ulong) (cmdtp->cmd), addr); | |
706 | #endif | |
707 | cmdtp->cmd = | |
708 | (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; | |
709 | ||
710 | addr = (ulong)(cmdtp->name) + gd->reloc_off; | |
711 | cmdtp->name = (char *)addr; | |
712 | ||
713 | if (cmdtp->usage) { | |
714 | addr = (ulong)(cmdtp->usage) + gd->reloc_off; | |
715 | cmdtp->usage = (char *)addr; | |
716 | } | |
717 | #ifdef CFG_LONGHELP | |
718 | if (cmdtp->help) { | |
719 | addr = (ulong)(cmdtp->help) + gd->reloc_off; | |
720 | cmdtp->help = (char *)addr; | |
721 | } | |
722 | #endif | |
723 | } | |
724 | /* there are some other pointer constants we must deal with */ | |
725 | #ifndef CFG_ENV_IS_NOWHERE | |
726 | env_name_spec += gd->reloc_off; | |
727 | #endif | |
728 | ||
729 | WATCHDOG_RESET (); | |
730 | ||
56f94be3 | 731 | #ifdef CONFIG_LOGBUFFER |
228f29ac | 732 | logbuff_init_ptrs (); |
56f94be3 | 733 | #endif |
fe8c2806 | 734 | #ifdef CONFIG_POST |
228f29ac | 735 | post_output_backlog (); |
fe8c2806 WD |
736 | post_reloc (); |
737 | #endif | |
738 | ||
739 | WATCHDOG_RESET(); | |
740 | ||
2688e2f9 KG |
741 | #if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \ |
742 | defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX) | |
fe8c2806 WD |
743 | icache_enable (); /* it's time to enable the instruction cache */ |
744 | #endif | |
745 | ||
1c8f6d8f | 746 | #if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) |
c837dcb1 | 747 | unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ |
42d1f039 WD |
748 | #endif |
749 | ||
3bac3513 | 750 | #if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45) |
fe8c2806 | 751 | /* |
3bac3513 WD |
752 | * Do PCI configuration on BAB7xx and CPC45 _before_ the flash |
753 | * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus | |
754 | * bridge there. | |
fe8c2806 WD |
755 | */ |
756 | pci_init (); | |
3bac3513 WD |
757 | #endif |
758 | #if defined(CONFIG_BAB7xx) | |
fe8c2806 WD |
759 | /* |
760 | * Initialise the ISA bridge | |
761 | */ | |
762 | initialise_w83c553f (); | |
763 | #endif | |
764 | ||
765 | asm ("sync ; isync"); | |
766 | ||
767 | /* | |
768 | * Setup trap handlers | |
769 | */ | |
770 | trap_init (dest_addr); | |
771 | ||
772 | #if !defined(CFG_NO_FLASH) | |
773 | puts ("FLASH: "); | |
774 | ||
775 | if ((flash_size = flash_init ()) > 0) { | |
0cb61d7d | 776 | # ifdef CFG_FLASH_CHECKSUM |
fe8c2806 WD |
777 | print_size (flash_size, ""); |
778 | /* | |
779 | * Compute and print flash CRC if flashchecksum is set to 'y' | |
780 | * | |
781 | * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX | |
782 | */ | |
783 | s = getenv ("flashchecksum"); | |
784 | if (s && (*s == 'y')) { | |
785 | printf (" CRC: %08lX", | |
7e780369 WD |
786 | crc32 (0, (const unsigned char *) CFG_FLASH_BASE, flash_size) |
787 | ); | |
fe8c2806 WD |
788 | } |
789 | putc ('\n'); | |
0cb61d7d | 790 | # else /* !CFG_FLASH_CHECKSUM */ |
fe8c2806 | 791 | print_size (flash_size, "\n"); |
0cb61d7d | 792 | # endif /* CFG_FLASH_CHECKSUM */ |
fe8c2806 WD |
793 | } else { |
794 | puts (failed); | |
795 | hang (); | |
796 | } | |
797 | ||
798 | bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */ | |
799 | bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ | |
fa230445 HS |
800 | |
801 | #if defined(CFG_UPDATE_FLASH_SIZE) | |
802 | /* Make a update of the Memctrl. */ | |
803 | update_flash_size (flash_size); | |
804 | #endif | |
805 | ||
806 | ||
7e780369 WD |
807 | # if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU) |
808 | /* flash mapped at end of memory map */ | |
809 | bd->bi_flashoffset = TEXT_BASE + flash_size; | |
0cb61d7d | 810 | # elif CFG_MONITOR_BASE == CFG_FLASH_BASE |
3b57fe0a | 811 | bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */ |
0cb61d7d | 812 | # else |
fe8c2806 | 813 | bd->bi_flashoffset = 0; |
0cb61d7d WD |
814 | # endif |
815 | #else /* CFG_NO_FLASH */ | |
fe8c2806 WD |
816 | |
817 | bd->bi_flashsize = 0; | |
818 | bd->bi_flashstart = 0; | |
819 | bd->bi_flashoffset = 0; | |
820 | #endif /* !CFG_NO_FLASH */ | |
821 | ||
822 | WATCHDOG_RESET (); | |
823 | ||
824 | /* initialize higher level parts of CPU like time base and timers */ | |
825 | cpu_init_r (); | |
826 | ||
827 | WATCHDOG_RESET (); | |
828 | ||
829 | /* initialize malloc() area */ | |
830 | mem_malloc_init (); | |
831 | malloc_bin_reloc (); | |
832 | ||
833 | #ifdef CONFIG_SPI | |
834 | # if !defined(CFG_ENV_IS_IN_EEPROM) | |
835 | spi_init_f (); | |
836 | # endif | |
837 | spi_init_r (); | |
838 | #endif | |
839 | ||
7def6b34 | 840 | #if defined(CONFIG_CMD_NAND) |
887e2ec9 SR |
841 | WATCHDOG_RESET (); |
842 | puts ("NAND: "); | |
843 | nand_init(); /* go init the NAND */ | |
844 | #endif | |
845 | ||
fe8c2806 WD |
846 | /* relocate environment function pointers etc. */ |
847 | env_relocate (); | |
848 | ||
849 | /* | |
850 | * Fill in missing fields of bd_info. | |
8bde7f77 WD |
851 | * We do this here, where we have "normal" access to the |
852 | * environment; we used to do this still running from ROM, | |
853 | * where had to use getenv_r(), which can be pretty slow when | |
854 | * the environment is in EEPROM. | |
fe8c2806 | 855 | */ |
7abf0c58 WD |
856 | |
857 | #if defined(CFG_EXTBDINFO) | |
858 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) | |
859 | #if defined(CONFIG_I2CFAST) | |
860 | /* | |
861 | * set bi_iic_fast for linux taking environment variable | |
862 | * "i2cfast" into account | |
863 | */ | |
864 | { | |
865 | char *s = getenv ("i2cfast"); | |
866 | if (s && ((*s == 'y') || (*s == 'Y'))) { | |
867 | bd->bi_iic_fast[0] = 1; | |
868 | bd->bi_iic_fast[1] = 1; | |
869 | } else { | |
870 | bd->bi_iic_fast[0] = 0; | |
871 | bd->bi_iic_fast[1] = 0; | |
872 | } | |
873 | } | |
874 | #else | |
875 | bd->bi_iic_fast[0] = 0; | |
876 | bd->bi_iic_fast[1] = 0; | |
877 | #endif /* CONFIG_I2CFAST */ | |
878 | #endif /* CONFIG_405GP, CONFIG_405EP */ | |
879 | #endif /* CFG_EXTBDINFO */ | |
880 | ||
9045f33c | 881 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
882 | sc3_read_eeprom(); |
883 | #endif | |
d59feffb | 884 | |
5b2793a3 | 885 | #if defined (CFG_ID_EEPROM) || defined (CFG_I2C_MAC_OFFSET) |
d59feffb HW |
886 | mac_read_from_eeprom(); |
887 | #endif | |
888 | ||
fe8c2806 | 889 | s = getenv ("ethaddr"); |
4707fb50 BS |
890 | #if defined (CONFIG_MBX) || \ |
891 | defined (CONFIG_RPXCLASSIC) || \ | |
892 | defined(CONFIG_IAD210) || \ | |
893 | defined(CONFIG_V38B) | |
fe8c2806 WD |
894 | if (s == NULL) |
895 | board_get_enetaddr (bd->bi_enetaddr); | |
896 | else | |
897 | #endif | |
898 | for (i = 0; i < 6; ++i) { | |
899 | bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; | |
900 | if (s) | |
901 | s = (*e) ? e + 1 : e; | |
902 | } | |
903 | #ifdef CONFIG_HERMES | |
904 | if ((gd->board_type >> 16) == 2) | |
905 | bd->bi_ethspeed = gd->board_type & 0xFFFF; | |
906 | else | |
907 | bd->bi_ethspeed = 0xFFFF; | |
908 | #endif | |
909 | ||
910 | #ifdef CONFIG_NX823 | |
911 | load_sernum_ethaddr (); | |
912 | #endif | |
913 | ||
e2ffd59b | 914 | #ifdef CONFIG_HAS_ETH1 |
fe8c2806 WD |
915 | /* handle the 2nd ethernet address */ |
916 | ||
917 | s = getenv ("eth1addr"); | |
918 | ||
919 | for (i = 0; i < 6; ++i) { | |
920 | bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0; | |
921 | if (s) | |
922 | s = (*e) ? e + 1 : e; | |
923 | } | |
924 | #endif | |
e2ffd59b | 925 | #ifdef CONFIG_HAS_ETH2 |
fe8c2806 WD |
926 | /* handle the 3rd ethernet address */ |
927 | ||
928 | s = getenv ("eth2addr"); | |
b79316f2 | 929 | #if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) |
ba56f625 WD |
930 | if (s == NULL) |
931 | board_get_enetaddr(bd->bi_enet2addr); | |
932 | else | |
933 | #endif | |
fe8c2806 WD |
934 | for (i = 0; i < 6; ++i) { |
935 | bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0; | |
936 | if (s) | |
937 | s = (*e) ? e + 1 : e; | |
938 | } | |
939 | #endif | |
940 | ||
e2ffd59b | 941 | #ifdef CONFIG_HAS_ETH3 |
ba56f625 WD |
942 | /* handle 4th ethernet address */ |
943 | s = getenv("eth3addr"); | |
b79316f2 | 944 | #if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) |
ba56f625 WD |
945 | if (s == NULL) |
946 | board_get_enetaddr(bd->bi_enet3addr); | |
947 | else | |
948 | #endif | |
949 | for (i = 0; i < 6; ++i) { | |
950 | bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0; | |
951 | if (s) | |
952 | s = (*e) ? e + 1 : e; | |
953 | } | |
954 | #endif | |
fe8c2806 WD |
955 | |
956 | #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ | |
fa230445 | 957 | defined(CONFIG_TQM8272) || \ |
566a494f HS |
958 | defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \ |
959 | defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP) | |
fe8c2806 WD |
960 | load_sernum_ethaddr (); |
961 | #endif | |
962 | /* IP Address */ | |
963 | bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); | |
964 | ||
965 | WATCHDOG_RESET (); | |
966 | ||
979bdbc7 | 967 | #if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45) |
fe8c2806 WD |
968 | /* |
969 | * Do pci configuration | |
970 | */ | |
971 | pci_init (); | |
972 | #endif | |
973 | ||
974 | /** leave this here (after malloc(), environment and PCI are working) **/ | |
975 | /* Initialize devices */ | |
976 | devices_init (); | |
977 | ||
27b207fd WD |
978 | /* Initialize the jump table for applications */ |
979 | jumptable_init (); | |
fe8c2806 | 980 | |
500856eb RJ |
981 | #if defined(CONFIG_API) |
982 | /* Initialize API */ | |
983 | api_init (); | |
984 | #endif | |
985 | ||
fe8c2806 WD |
986 | /* Initialize the console (after the relocation and devices init) */ |
987 | console_init_r (); | |
fe8c2806 WD |
988 | |
989 | #if defined(CONFIG_CCM) || \ | |
990 | defined(CONFIG_COGENT) || \ | |
991 | defined(CONFIG_CPCI405) || \ | |
992 | defined(CONFIG_EVB64260) || \ | |
56f94be3 | 993 | defined(CONFIG_KUP4K) || \ |
0608e04d | 994 | defined(CONFIG_KUP4X) || \ |
fe8c2806 WD |
995 | defined(CONFIG_LWMON) || \ |
996 | defined(CONFIG_PCU_E) || \ | |
9045f33c | 997 | defined(CONFIG_SC3) || \ |
fe8c2806 WD |
998 | defined(CONFIG_W7O) || \ |
999 | defined(CONFIG_MISC_INIT_R) | |
1000 | /* miscellaneous platform dependent initialisations */ | |
1001 | misc_init_r (); | |
1002 | #endif | |
1003 | ||
1004 | #ifdef CONFIG_HERMES | |
1005 | if (bd->bi_ethspeed != 0xFFFF) | |
1006 | hermes_start_lxt980 ((int) bd->bi_ethspeed); | |
1007 | #endif | |
1008 | ||
7def6b34 | 1009 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
1010 | WATCHDOG_RESET (); |
1011 | puts ("KGDB: "); | |
1012 | kgdb_init (); | |
1013 | #endif | |
1014 | ||
9d2b18a0 | 1015 | debug ("U-Boot relocated to %08lx\n", dest_addr); |
fe8c2806 WD |
1016 | |
1017 | /* | |
1018 | * Enable Interrupts | |
1019 | */ | |
1020 | interrupt_init (); | |
1021 | ||
1022 | /* Must happen after interrupts are initialized since | |
1023 | * an irq handler gets installed | |
1024 | */ | |
42dfe7a1 | 1025 | #ifdef CONFIG_SERIAL_SOFTWARE_FIFO |
fe8c2806 WD |
1026 | serial_buffered_init(); |
1027 | #endif | |
1028 | ||
566a494f | 1029 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
fe8c2806 WD |
1030 | status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); |
1031 | #endif | |
1032 | ||
1033 | udelay (20); | |
1034 | ||
1035 | set_timer (0); | |
1036 | ||
fe8c2806 WD |
1037 | /* Initialize from environment */ |
1038 | if ((s = getenv ("loadaddr")) != NULL) { | |
1039 | load_addr = simple_strtoul (s, NULL, 16); | |
1040 | } | |
7def6b34 | 1041 | #if defined(CONFIG_CMD_NET) |
fe8c2806 WD |
1042 | if ((s = getenv ("bootfile")) != NULL) { |
1043 | copy_filename (BootFile, s, sizeof (BootFile)); | |
1044 | } | |
b3aff0cb | 1045 | #endif |
fe8c2806 WD |
1046 | |
1047 | WATCHDOG_RESET (); | |
1048 | ||
7def6b34 | 1049 | #if defined(CONFIG_CMD_SCSI) |
fe8c2806 WD |
1050 | WATCHDOG_RESET (); |
1051 | puts ("SCSI: "); | |
1052 | scsi_init (); | |
1053 | #endif | |
1054 | ||
7def6b34 | 1055 | #if defined(CONFIG_CMD_DOC) |
fe8c2806 WD |
1056 | WATCHDOG_RESET (); |
1057 | puts ("DOC: "); | |
1058 | doc_init (); | |
1059 | #endif | |
1060 | ||
7def6b34 | 1061 | #if defined(CONFIG_CMD_NET) |
63ff004c | 1062 | #if defined(CONFIG_NET_MULTI) |
fe8c2806 WD |
1063 | WATCHDOG_RESET (); |
1064 | puts ("Net: "); | |
63ff004c | 1065 | #endif |
fe8c2806 WD |
1066 | eth_initialize (bd); |
1067 | #endif | |
1068 | ||
7def6b34 | 1069 | #if defined(CONFIG_CMD_NET) && ( \ |
63ff004c MB |
1070 | defined(CONFIG_CCM) || \ |
1071 | defined(CONFIG_ELPT860) || \ | |
1072 | defined(CONFIG_EP8260) || \ | |
1073 | defined(CONFIG_IP860) || \ | |
1074 | defined(CONFIG_IVML24) || \ | |
1075 | defined(CONFIG_IVMS8) || \ | |
1076 | defined(CONFIG_MPC8260ADS) || \ | |
1077 | defined(CONFIG_MPC8266ADS) || \ | |
1078 | defined(CONFIG_MPC8560ADS) || \ | |
1079 | defined(CONFIG_PCU_E) || \ | |
1080 | defined(CONFIG_RPXSUPER) || \ | |
1081 | defined(CONFIG_STXGP3) || \ | |
1082 | defined(CONFIG_SPD823TS) || \ | |
1083 | defined(CONFIG_RESET_PHY_R) ) | |
1084 | ||
1085 | WATCHDOG_RESET (); | |
1086 | debug ("Reset Ethernet PHY\n"); | |
1087 | reset_phy (); | |
1088 | #endif | |
1089 | ||
fe8c2806 | 1090 | #ifdef CONFIG_POST |
6dff5529 | 1091 | post_run (NULL, POST_RAM | post_bootmode_get(0)); |
fe8c2806 WD |
1092 | #endif |
1093 | ||
7def6b34 JL |
1094 | #if defined(CONFIG_CMD_PCMCIA) \ |
1095 | && !defined(CONFIG_CMD_IDE) | |
fe8c2806 WD |
1096 | WATCHDOG_RESET (); |
1097 | puts ("PCMCIA:"); | |
1098 | pcmcia_init (); | |
1099 | #endif | |
1100 | ||
7def6b34 | 1101 | #if defined(CONFIG_CMD_IDE) |
fe8c2806 WD |
1102 | WATCHDOG_RESET (); |
1103 | # ifdef CONFIG_IDE_8xx_PCCARD | |
1104 | puts ("PCMCIA:"); | |
1105 | # else | |
1106 | puts ("IDE: "); | |
1107 | #endif | |
ca43ba18 HS |
1108 | #if defined(CONFIG_START_IDE) |
1109 | if (board_start_ide()) | |
1110 | ide_init (); | |
1111 | #else | |
fe8c2806 | 1112 | ide_init (); |
ca43ba18 | 1113 | #endif |
b3aff0cb | 1114 | #endif |
fe8c2806 | 1115 | |
cd54081c DL |
1116 | #if defined(CONFIG_CMD_SATA) |
1117 | puts ("SATA: "); | |
1118 | sata_initialize (); | |
1119 | #endif | |
1120 | ||
fe8c2806 WD |
1121 | #ifdef CONFIG_LAST_STAGE_INIT |
1122 | WATCHDOG_RESET (); | |
1123 | /* | |
1124 | * Some parts can be only initialized if all others (like | |
1125 | * Interrupts) are up and running (i.e. the PC-style ISA | |
1126 | * keyboard). | |
1127 | */ | |
1128 | last_stage_init (); | |
1129 | #endif | |
1130 | ||
7def6b34 | 1131 | #if defined(CONFIG_CMD_BEDBUG) |
fe8c2806 WD |
1132 | WATCHDOG_RESET (); |
1133 | bedbug_init (); | |
1134 | #endif | |
1135 | ||
228f29ac | 1136 | #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) |
fe8c2806 WD |
1137 | /* |
1138 | * Export available size of memory for Linux, | |
1139 | * taking into account the protected RAM at top of memory | |
1140 | */ | |
1141 | { | |
1142 | ulong pram; | |
fe8c2806 | 1143 | uchar memsz[32]; |
228f29ac WD |
1144 | #ifdef CONFIG_PRAM |
1145 | char *s; | |
fe8c2806 WD |
1146 | |
1147 | if ((s = getenv ("pram")) != NULL) { | |
1148 | pram = simple_strtoul (s, NULL, 10); | |
1149 | } else { | |
1150 | pram = CONFIG_PRAM; | |
1151 | } | |
228f29ac WD |
1152 | #else |
1153 | pram=0; | |
1154 | #endif | |
1155 | #ifdef CONFIG_LOGBUFFER | |
3d610186 | 1156 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac WD |
1157 | /* Also take the logbuffer into account (pram is in kB) */ |
1158 | pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; | |
3d610186 | 1159 | #endif |
228f29ac | 1160 | #endif |
77ddac94 WD |
1161 | sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); |
1162 | setenv ("mem", (char *)memsz); | |
fe8c2806 WD |
1163 | } |
1164 | #endif | |
1165 | ||
1c43771b WD |
1166 | #ifdef CONFIG_PS2KBD |
1167 | puts ("PS/2: "); | |
1168 | kbd_init(); | |
1169 | #endif | |
1170 | ||
4532cb69 WD |
1171 | #ifdef CONFIG_MODEM_SUPPORT |
1172 | { | |
1173 | extern int do_mdm_init; | |
1174 | do_mdm_init = gd->do_mdm_init; | |
1175 | } | |
1176 | #endif | |
1177 | ||
fe8c2806 WD |
1178 | /* Initialization complete - start the monitor */ |
1179 | ||
1180 | /* main_loop() can return to retry autoboot, if so just run it again. */ | |
1181 | for (;;) { | |
1182 | WATCHDOG_RESET (); | |
1183 | main_loop (); | |
1184 | } | |
1185 | ||
1186 | /* NOTREACHED - no way out of command loop except booting */ | |
1187 | } | |
1188 | ||
1189 | void hang (void) | |
1190 | { | |
1191 | puts ("### ERROR ### Please RESET the board ###\n"); | |
63e73c9a | 1192 | show_boot_progress(-30); |
fe8c2806 WD |
1193 | for (;;); |
1194 | } | |
1195 | ||
4532cb69 WD |
1196 | #ifdef CONFIG_MODEM_SUPPORT |
1197 | /* called from main loop (common/main.c) */ | |
77ddac94 WD |
1198 | /* 'inline' - We have to do it fast */ |
1199 | static inline void mdm_readline(char *buf, int bufsiz) | |
1200 | { | |
1201 | char c; | |
1202 | char *p; | |
1203 | int n; | |
1204 | ||
1205 | n = 0; | |
1206 | p = buf; | |
1207 | for(;;) { | |
1208 | c = serial_getc(); | |
1209 | ||
1210 | /* dbg("(%c)", c); */ | |
1211 | ||
1212 | switch(c) { | |
1213 | case '\r': | |
1214 | break; | |
1215 | case '\n': | |
1216 | *p = '\0'; | |
1217 | return; | |
1218 | ||
1219 | default: | |
1220 | if(n++ > bufsiz) { | |
1221 | *p = '\0'; | |
1222 | return; /* sanity check */ | |
1223 | } | |
1224 | *p = c; | |
1225 | p++; | |
1226 | break; | |
1227 | } | |
1228 | } | |
1229 | } | |
1230 | ||
4532cb69 WD |
1231 | extern void dbg(const char *fmt, ...); |
1232 | int mdm_init (void) | |
1233 | { | |
1234 | char env_str[16]; | |
1235 | char *init_str; | |
1236 | int i; | |
1237 | extern char console_buffer[]; | |
4532cb69 WD |
1238 | extern void enable_putc(void); |
1239 | extern int hwflow_onoff(int); | |
1240 | ||
1241 | enable_putc(); /* enable serial_putc() */ | |
1242 | ||
1243 | #ifdef CONFIG_HWFLOW | |
1244 | init_str = getenv("mdm_flow_control"); | |
1245 | if (init_str && (strcmp(init_str, "rts/cts") == 0)) | |
1246 | hwflow_onoff (1); | |
1247 | else | |
1248 | hwflow_onoff(-1); | |
1249 | #endif | |
1250 | ||
1251 | for (i = 1;;i++) { | |
1252 | sprintf(env_str, "mdm_init%d", i); | |
1253 | if ((init_str = getenv(env_str)) != NULL) { | |
1254 | serial_puts(init_str); | |
1255 | serial_puts("\n"); | |
1256 | for(;;) { | |
1257 | mdm_readline(console_buffer, CFG_CBSIZE); | |
1258 | dbg("ini%d: [%s]", i, console_buffer); | |
1259 | ||
1260 | if ((strcmp(console_buffer, "OK") == 0) || | |
1261 | (strcmp(console_buffer, "ERROR") == 0)) { | |
1262 | dbg("ini%d: cmd done", i); | |
1263 | break; | |
1264 | } else /* in case we are originating call ... */ | |
1265 | if (strncmp(console_buffer, "CONNECT", 7) == 0) { | |
1266 | dbg("ini%d: connect", i); | |
1267 | return 0; | |
1268 | } | |
1269 | } | |
1270 | } else | |
1271 | break; /* no init string - stop modem init */ | |
1272 | ||
1273 | udelay(100000); | |
1274 | } | |
1275 | ||
1276 | udelay(100000); | |
1277 | ||
1278 | /* final stage - wait for connect */ | |
1279 | for(;i > 1;) { /* if 'i' > 1 - wait for connection | |
1280 | message from modem */ | |
1281 | mdm_readline(console_buffer, CFG_CBSIZE); | |
1282 | dbg("ini_f: [%s]", console_buffer); | |
1283 | if (strncmp(console_buffer, "CONNECT", 7) == 0) { | |
1284 | dbg("ini_f: connected"); | |
1285 | return 0; | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
4532cb69 WD |
1292 | #endif |
1293 | ||
fe8c2806 WD |
1294 | #if 0 /* We could use plain global data, but the resulting code is bigger */ |
1295 | /* | |
1296 | * Pointer to initial global data area | |
1297 | * | |
1298 | * Here we initialize it. | |
1299 | */ | |
1300 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
1301 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
1302 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); | |
1303 | #endif /* 0 */ | |
1304 | ||
1305 | /************************************************************************/ |