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ppc4xx: Add fdt support to Prodrive alpr
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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
28#include <devices.h>
fe8c2806
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
WD
32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
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36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
fe8c2806
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39#include <ide.h>
40#endif
cd54081c
DL
41#if defined(CONFIG_CMD_SATA)
42#include <sata.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_SCSI)
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45#include <scsi.h>
46#endif
7def6b34 47#if defined(CONFIG_CMD_KGDB)
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48#include <kgdb.h>
49#endif
50#ifdef CONFIG_STATUS_LED
51#include <status_led.h>
52#endif
53#include <net.h>
281e00a3 54#include <serial.h>
fe8c2806 55#ifdef CFG_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
fe8c2806
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57#include <commproc.h>
58#endif
7aa78614 59#endif
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
56f94be3
WD
68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
42d1f039
WD
71#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
72#include <asm/cache.h>
73#endif
1c43771b
WD
74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
fa230445
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78#ifdef CFG_UPDATE_FLASH_SIZE
79extern int update_flash_size (int flash_size);
80#endif
81
9045f33c 82#if defined(CONFIG_SC3)
ca43ba18
HS
83extern void sc3_read_eeprom(void);
84#endif
85
7def6b34 86#if defined(CONFIG_CMD_DOC)
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87void doc_init (void);
88#endif
89#if defined(CONFIG_HARD_I2C) || \
90 defined(CONFIG_SOFT_I2C)
91#include <i2c.h>
92#endif
04a9e118
BW
93#if defined(CONFIG_HARD_SPI)
94#include <spi.h>
95#endif
7def6b34 96#if defined(CONFIG_CMD_NAND)
bedc4970
SR
97void nand_init (void);
98#endif
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99
100static char *failed = "*** failed ***\n";
101
17d704eb 102#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 103extern flash_info_t flash_info[];
17d704eb 104#endif
fe8c2806 105
ca43ba18
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106#if defined(CONFIG_START_IDE)
107extern int board_start_ide(void);
108#endif
fe8c2806 109#include <environment.h>
d87080b7 110
bce84c4d 111DECLARE_GLOBAL_DATA_PTR;
fe8c2806 112
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113#if defined(CFG_ENV_IS_EMBEDDED)
114#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
115#elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
04a85b3b 116 (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
7e780369 117 defined(CFG_ENV_IS_IN_NVRAM)
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118#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
119#else
120#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
121#endif
122
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WD
123extern ulong __init_end;
124extern ulong _end;
3b57fe0a
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125ulong monitor_flash_len;
126
7def6b34 127#if defined(CONFIG_CMD_BEDBUG)
8bde7f77
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128#include <bedbug/type.h>
129#endif
130
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131/*
132 * Begin and End of memory area for malloc(), and current "brk"
133 */
134static ulong mem_malloc_start = 0;
135static ulong mem_malloc_end = 0;
136static ulong mem_malloc_brk = 0;
137
138/************************************************************************
139 * Utilities *
140 ************************************************************************
141 */
142
143/*
144 * The Malloc area is immediately below the monitor copy in DRAM
145 */
146static void mem_malloc_init (void)
147{
e9514751
SR
148#if !defined(CONFIG_RELOC_FIXUP_WORKS)
149 mem_malloc_end = CFG_MONITOR_BASE + gd->reloc_off;
150#endif
151 mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
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152 mem_malloc_brk = mem_malloc_start;
153
154 memset ((void *) mem_malloc_start,
155 0,
156 mem_malloc_end - mem_malloc_start);
157}
158
159void *sbrk (ptrdiff_t increment)
160{
161 ulong old = mem_malloc_brk;
162 ulong new = old + increment;
163
164 if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
165 return (NULL);
166 }
167 mem_malloc_brk = new;
168 return ((void *) old);
169}
170
171char *strmhz (char *buf, long hz)
172{
173 long l, n;
174 long m;
175
176 n = hz / 1000000L;
177 l = sprintf (buf, "%ld", n);
178 m = (hz % 1000000L) / 1000L;
179 if (m != 0)
180 sprintf (buf + l, ".%03ld", m);
181 return (buf);
182}
183
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184/*
185 * All attempts to come up with a "common" initialization sequence
186 * that works for all boards and architectures failed: some of the
187 * requirements are just _too_ different. To get rid of the resulting
188 * mess of board dependend #ifdef'ed code we now make the whole
189 * initialization sequence configurable to the user.
190 *
191 * The requirements for any new initalization function is simple: it
192 * receives a pointer to the "global data" structure as it's only
193 * argument, and returns an integer return code, where 0 means
194 * "continue" and != 0 means "fatal error, hang the system".
195 */
196typedef int (init_fnc_t) (void);
197
198/************************************************************************
199 * Init Utilities *
200 ************************************************************************
201 * Some of this code should be moved into the core functions,
202 * but let's get it working (again) first...
203 */
204
205static int init_baudrate (void)
206{
77ddac94 207 char tmp[64]; /* long enough for environment variables */
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208 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
209
210 gd->baudrate = (i > 0)
211 ? (int) simple_strtoul (tmp, NULL, 10)
212 : CONFIG_BAUDRATE;
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213 return (0);
214}
215
216/***********************************************************************/
217
79f240f7
KP
218void __board_add_ram_info(int use_default)
219{
220 /* please define platform specific board_add_ram_info() */
221}
222void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
223
d96f41e0 224
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225static int init_func_ram (void)
226{
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227#ifdef CONFIG_BOARD_TYPES
228 int board_type = gd->board_type;
229#else
230 int board_type = 0; /* use dummy arg */
231#endif
232 puts ("DRAM: ");
233
234 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 235 print_size (gd->ram_size, "");
d96f41e0 236 board_add_ram_info(0);
d96f41e0 237 putc('\n');
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238 return (0);
239 }
240 puts (failed);
241 return (1);
242}
243
244/***********************************************************************/
245
246#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
247static int init_func_i2c (void)
248{
249 puts ("I2C: ");
250 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
251 puts ("ready\n");
252 return (0);
253}
254#endif
255
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256#if defined(CONFIG_HARD_SPI)
257static int init_func_spi (void)
258{
259 puts ("SPI: ");
260 spi_init ();
261 puts ("ready\n");
262 return (0);
263}
264#endif
265
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266/***********************************************************************/
267
268#if defined(CONFIG_WATCHDOG)
269static int init_func_watchdog_init (void)
270{
271 puts (" Watchdog enabled\n");
272 WATCHDOG_RESET ();
273 return (0);
274}
275# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
276
277static int init_func_watchdog_reset (void)
278{
279 WATCHDOG_RESET ();
280 return (0);
281}
282# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
283#else
284# define INIT_FUNC_WATCHDOG_INIT /* undef */
285# define INIT_FUNC_WATCHDOG_RESET /* undef */
286#endif /* CONFIG_WATCHDOG */
287
288/************************************************************************
289 * Initialization sequence *
290 ************************************************************************
291 */
292
293init_fnc_t *init_sequence[] = {
294
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WD
295#if defined(CONFIG_BOARD_EARLY_INIT_F)
296 board_early_init_f,
fe8c2806 297#endif
c178d3da 298
66ca92a5 299#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 300 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
301#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
302 && !defined(CONFIG_TQM885D)
e9132ea9
WD
303 adjust_sdram_tbs_8xx,
304#endif
fe8c2806 305 init_timebase,
c178d3da 306#endif
fe8c2806 307#ifdef CFG_ALLOC_DPRAM
9c4c5ae3 308#if !defined(CONFIG_CPM2)
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309 dpram_init,
310#endif
7aa78614 311#endif
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312#if defined(CONFIG_BOARD_POSTCLK_INIT)
313 board_postclk_init,
314#endif
315 env_init,
66ca92a5 316#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
c178d3da
WD
317 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
318 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
319 init_timebase,
320#endif
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WD
321 init_baudrate,
322 serial_init,
323 console_init_f,
324 display_options,
325#if defined(CONFIG_8260)
326 prt_8260_rsr,
327 prt_8260_clks,
328#endif /* CONFIG_8260 */
9be39a67
DL
329#if defined(CONFIG_MPC83XX)
330 prt_83xx_rsr,
331#endif
fe8c2806 332 checkcpu,
cbd8a35c 333#if defined(CONFIG_MPC5xxx)
945af8d7 334 prt_mpc5xxx_clks,
cbd8a35c 335#endif /* CONFIG_MPC5xxx */
983fda83
WD
336#if defined(CONFIG_MPC8220)
337 prt_mpc8220_clks,
338#endif
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339 checkboard,
340 INIT_FUNC_WATCHDOG_INIT
c837dcb1 341#if defined(CONFIG_MISC_INIT_F)
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342 misc_init_f,
343#endif
344 INIT_FUNC_WATCHDOG_RESET
345#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
346 init_func_i2c,
347#endif
04a9e118
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348#if defined(CONFIG_HARD_SPI)
349 init_func_spi,
350#endif
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351#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
352 dtt_init,
4532cb69
WD
353#endif
354#ifdef CONFIG_POST
355 post_init_f,
fe8c2806
WD
356#endif
357 INIT_FUNC_WATCHDOG_RESET
358 init_func_ram,
359#if defined(CFG_DRAM_TEST)
360 testdram,
361#endif /* CFG_DRAM_TEST */
362 INIT_FUNC_WATCHDOG_RESET
363
364 NULL, /* Terminate this list */
365};
366
81d93e5c
KG
367#ifndef CONFIG_MAX_MEM_MAPPED
368#define CONFIG_MAX_MEM_MAPPED (256 << 20)
369#endif
370ulong get_effective_memsize(void)
371{
372#ifndef CONFIG_VERY_BIG_RAM
373 return gd->ram_size;
374#else
375 /* limit stack to what we can reasonable map */
376 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
377 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
378#endif
379}
380
fe8c2806
WD
381/************************************************************************
382 *
383 * This is the first part of the initialization sequence that is
384 * implemented in C, but still running from ROM.
385 *
386 * The main purpose is to provide a (serial) console interface as
387 * soon as possible (so we can see any error messages), and to
388 * initialize the RAM so that we can relocate the monitor code to
389 * RAM.
390 *
391 * Be aware of the restrictions: global data is read-only, BSS is not
392 * initialized, and stack space is limited to a few kB.
393 *
394 ************************************************************************
395 */
396
397void board_init_f (ulong bootflag)
398{
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WD
399 bd_t *bd;
400 ulong len, addr, addr_sp;
7bc5ee07 401 ulong *s;
fe8c2806
WD
402 gd_t *id;
403 init_fnc_t **init_fnc_ptr;
404#ifdef CONFIG_PRAM
405 int i;
406 ulong reg;
407 uchar tmp[64]; /* long enough for environment variables */
408#endif
409
410 /* Pointer is writable since we allocated a register for it */
411 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
93f6a677
WD
412 /* compiler optimization barrier needed for GCC >= 3.4 */
413 __asm__ __volatile__("": : :"memory");
fe8c2806 414
9be39a67 415#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX)
fe8c2806
WD
416 /* Clear initial global data */
417 memset ((void *) gd, 0, sizeof (gd_t));
418#endif
419
420 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
421 if ((*init_fnc_ptr) () != 0) {
422 hang ();
423 }
424 }
425
426 /*
427 * Now that we have DRAM mapped and working, we can
428 * relocate the code and continue running from DRAM.
429 *
430 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 431 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 432 * - kernel log buffer
fe8c2806
WD
433 * - protected RAM
434 * - LCD framebuffer
435 * - monitor code
436 * - board info struct
437 */
3b57fe0a 438 len = (ulong)&_end - CFG_MONITOR_BASE;
fe8c2806 439
14f73ca6
SR
440 /*
441 * Subtract specified amount of memory to hide so that it won't
442 * get "touched" at all by U-Boot. By fixing up gd->ram_size
443 * the Linux kernel should now get passed the now "corrected"
444 * memory size and won't touch it either. This should work
445 * for arch/ppc and arch/powerpc. Only Linux board ports in
446 * arch/powerpc with bootwrapper support, that recalculate the
447 * memory size from the SDRAM controller setup will have to
448 * get fixed.
449 */
450 gd->ram_size -= CFG_MEM_TOP_HIDE;
451
9c666a7d
KG
452#ifndef CONFIG_MAX_MEM_MAPPED
453#define CONFIG_MAX_MEM_MAPPED (256 << 20)
454#endif
455
456#ifndef CONFIG_VERY_BIG_RAM
81d93e5c 457 addr = CFG_SDRAM_BASE + get_effective_memsize();
9c666a7d
KG
458#else
459 /* only allow stack below 256M */
460 addr = CFG_SDRAM_BASE +
461 (gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
462 CONFIG_MAX_MEM_MAPPED : get_effective_memsize();
463#endif
fe8c2806 464
228f29ac 465#ifdef CONFIG_LOGBUFFER
3d610186 466#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
467 /* reserve kernel log buffer */
468 addr -= (LOGBUFF_RESERVE);
9d2b18a0 469 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 470#endif
3d610186 471#endif
228f29ac 472
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WD
473#ifdef CONFIG_PRAM
474 /*
475 * reserve protected RAM
476 */
77ddac94
WD
477 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
478 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 479 addr -= (reg << 10); /* size is in kB */
9d2b18a0 480 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
fe8c2806
WD
481#endif /* CONFIG_PRAM */
482
483 /* round down to next 4 kB limit */
484 addr &= ~(4096 - 1);
9d2b18a0 485 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
fe8c2806
WD
486
487#ifdef CONFIG_LCD
488 /* reserve memory for LCD display (always full pages) */
489 addr = lcd_setmem (addr);
490 gd->fb_base = addr;
491#endif /* CONFIG_LCD */
492
493#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
494 /* reserve memory for video display (always full pages) */
495 addr = video_setmem (addr);
496 gd->fb_base = addr;
497#endif /* CONFIG_VIDEO */
498
499 /*
500 * reserve memory for U-Boot code, data & bss
682011ff 501 * round down to next 4 kB limit
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502 */
503 addr -= len;
682011ff 504 addr &= ~(4096 - 1);
7d314992
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505#ifdef CONFIG_E500
506 /* round down to next 64 kB limit so that IVPR stays aligned */
507 addr &= ~(65536 - 1);
508#endif
fe8c2806 509
9d2b18a0 510 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 511
c7de829c
WD
512#ifdef CONFIG_AMIGAONEG3SE
513 gd->relocaddr = addr;
514#endif
515
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516 /*
517 * reserve memory for malloc() arena
518 */
519 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 520 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 521 TOTAL_MALLOC_LEN >> 10, addr_sp);
fe8c2806
WD
522
523 /*
524 * (permanently) allocate a Board Info struct
525 * and a permanent copy of the "global" data
526 */
527 addr_sp -= sizeof (bd_t);
528 bd = (bd_t *) addr_sp;
529 gd->bd = bd;
9d2b18a0 530 debug ("Reserving %d Bytes for Board Info at: %08lx\n",
fe8c2806 531 sizeof (bd_t), addr_sp);
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WD
532 addr_sp -= sizeof (gd_t);
533 id = (gd_t *) addr_sp;
9d2b18a0 534 debug ("Reserving %d Bytes for Global Data at: %08lx\n",
fe8c2806 535 sizeof (gd_t), addr_sp);
fe8c2806
WD
536
537 /*
538 * Finally, we set up a new (bigger) stack.
539 *
540 * Leave some safety gap for SP, force alignment on 16 byte boundary
541 * Clear initial stack frame
542 */
543 addr_sp -= 16;
544 addr_sp &= ~0xF;
7bc5ee07
WD
545 s = (ulong *)addr_sp;
546 *s-- = 0;
547 *s-- = 0;
548 addr_sp = (ulong)s;
9d2b18a0 549 debug ("Stack Pointer at: %08lx\n", addr_sp);
fe8c2806
WD
550
551 /*
552 * Save local variables to board info struct
553 */
554
c837dcb1 555 bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
fe8c2806
WD
556 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
557
558#ifdef CONFIG_IP860
c837dcb1
WD
559 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
560 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
983fda83
WD
561#elif defined CONFIG_MPC8220
562 bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */
563 bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 564#else
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565 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
566 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
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WD
567#endif
568
42d1f039 569#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 570 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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571 bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
572#endif
cbd8a35c 573#if defined(CONFIG_MPC5xxx)
945af8d7
WD
574 bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
575#endif
f046ccd1 576#if defined(CONFIG_MPC83XX)
d239d74b 577 bd->bi_immrbar = CFG_IMMR;
f046ccd1 578#endif
983fda83
WD
579#if defined(CONFIG_MPC8220)
580 bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
581 bd->bi_inpfreq = gd->inp_clk;
582 bd->bi_pcifreq = gd->pci_clk;
583 bd->bi_vcofreq = gd->vco_clk;
584 bd->bi_pevfreq = gd->pev_clk;
585 bd->bi_flbfreq = gd->flb_clk;
586
dd520bf3
WD
587 /* store bootparam to sram (backward compatible), here? */
588 {
589 u32 *sram = (u32 *)CFG_SRAM_BASE;
590 *sram++ = gd->ram_size;
591 *sram++ = gd->bus_clk;
592 *sram++ = gd->inp_clk;
593 *sram++ = gd->cpu_clk;
594 *sram++ = gd->vco_clk;
595 *sram++ = gd->flb_clk;
596 *sram++ = 0xb8c3ba11; /* boot signature */
597 }
983fda83 598#endif
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WD
599
600 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
601
602 WATCHDOG_RESET ();
603 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
604 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 605#if defined(CONFIG_CPM2)
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WD
606 bd->bi_cpmfreq = gd->cpm_clk;
607 bd->bi_brgfreq = gd->brg_clk;
608 bd->bi_sccfreq = gd->scc_clk;
609 bd->bi_vco = gd->vco_out;
9c4c5ae3 610#endif /* CONFIG_CPM2 */
281ff9a4 611#if defined(CONFIG_MPC512X)
5d49e0e1 612 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 613#endif /* CONFIG_MPC512X */
cbd8a35c 614#if defined(CONFIG_MPC5xxx)
945af8d7
WD
615 bd->bi_ipbfreq = gd->ipb_clk;
616 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 617#endif /* CONFIG_MPC5xxx */
fe8c2806
WD
618 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
619
620#ifdef CFG_EXTBDINFO
77ddac94
WD
621 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
622 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
fe8c2806
WD
623
624 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
625 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
626#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
627 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
628 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 629 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 630 bd->bi_opbfreq = get_OPB_freq ();
028ab6b5
WD
631#elif defined(CONFIG_XILINX_ML300)
632 bd->bi_pci_busfreq = get_PCI_freq ();
fe8c2806
WD
633#endif
634#endif
635
9d2b18a0 636 debug ("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806
WD
637
638 WATCHDOG_RESET ();
639
640#ifdef CONFIG_POST
641 post_bootmode_init();
6dff5529 642 post_run (NULL, POST_ROM | post_bootmode_get(0));
fe8c2806
WD
643#endif
644
645 WATCHDOG_RESET();
646
27b207fd 647 memcpy (id, (void *)gd, sizeof (gd_t));
fe8c2806
WD
648
649 relocate_code (addr_sp, id, addr);
650
651 /* NOTREACHED - relocate_code() does not return */
652}
653
fe8c2806
WD
654/************************************************************************
655 *
656 * This is the next part if the initialization sequence: we are now
657 * running from RAM and have a "normal" C environment, i. e. global
658 * data can be written, BSS has been cleared, the stack size in not
659 * that critical any more, etc.
660 *
661 ************************************************************************
662 */
fe8c2806
WD
663void board_init_r (gd_t *id, ulong dest_addr)
664{
fe8c2806
WD
665 cmd_tbl_t *cmdtp;
666 char *s, *e;
667 bd_t *bd;
668 int i;
669 extern void malloc_bin_reloc (void);
670#ifndef CFG_ENV_IS_NOWHERE
671 extern char * env_name_spec;
672#endif
673
674#ifndef CFG_NO_FLASH
675 ulong flash_size;
676#endif
677
678 gd = id; /* initialize RAM version of global data */
679 bd = gd->bd;
680
681 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63
GL
682
683#if defined(CONFIG_RELOC_FIXUP_WORKS)
684 gd->reloc_off = 0;
e9514751 685 mem_malloc_end = dest_addr;
f82b3b63 686#else
bb105f24 687 gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
f82b3b63 688#endif
bb105f24
MB
689
690#ifdef CONFIG_SERIAL_MULTI
691 serial_initialize();
692#endif
fe8c2806 693
9d2b18a0 694 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806
WD
695
696 WATCHDOG_RESET ();
697
c837dcb1
WD
698#if defined(CONFIG_BOARD_EARLY_INIT_R)
699 board_early_init_r ();
700#endif
701
3b57fe0a 702 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806
WD
703
704 /*
705 * We have to relocate the command table manually
706 */
8bde7f77 707 for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
fe8c2806 708 ulong addr;
fe8c2806
WD
709 addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
710#if 0
711 printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
712 cmdtp->name, (ulong) (cmdtp->cmd), addr);
713#endif
714 cmdtp->cmd =
715 (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
716
717 addr = (ulong)(cmdtp->name) + gd->reloc_off;
718 cmdtp->name = (char *)addr;
719
720 if (cmdtp->usage) {
721 addr = (ulong)(cmdtp->usage) + gd->reloc_off;
722 cmdtp->usage = (char *)addr;
723 }
724#ifdef CFG_LONGHELP
725 if (cmdtp->help) {
726 addr = (ulong)(cmdtp->help) + gd->reloc_off;
727 cmdtp->help = (char *)addr;
728 }
729#endif
730 }
731 /* there are some other pointer constants we must deal with */
732#ifndef CFG_ENV_IS_NOWHERE
733 env_name_spec += gd->reloc_off;
734#endif
735
736 WATCHDOG_RESET ();
737
56f94be3 738#ifdef CONFIG_LOGBUFFER
228f29ac 739 logbuff_init_ptrs ();
56f94be3 740#endif
fe8c2806 741#ifdef CONFIG_POST
228f29ac 742 post_output_backlog ();
fe8c2806
WD
743 post_reloc ();
744#endif
745
746 WATCHDOG_RESET();
747
2688e2f9
KG
748#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
749 defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
fe8c2806
WD
750 icache_enable (); /* it's time to enable the instruction cache */
751#endif
752
1c8f6d8f 753#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
c837dcb1 754 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
755#endif
756
3bac3513 757#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 758 /*
3bac3513
WD
759 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
760 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
761 * bridge there.
fe8c2806
WD
762 */
763 pci_init ();
3bac3513
WD
764#endif
765#if defined(CONFIG_BAB7xx)
fe8c2806
WD
766 /*
767 * Initialise the ISA bridge
768 */
769 initialise_w83c553f ();
770#endif
771
772 asm ("sync ; isync");
773
774 /*
775 * Setup trap handlers
776 */
777 trap_init (dest_addr);
778
779#if !defined(CFG_NO_FLASH)
780 puts ("FLASH: ");
781
782 if ((flash_size = flash_init ()) > 0) {
0cb61d7d 783# ifdef CFG_FLASH_CHECKSUM
fe8c2806
WD
784 print_size (flash_size, "");
785 /*
786 * Compute and print flash CRC if flashchecksum is set to 'y'
787 *
788 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
789 */
790 s = getenv ("flashchecksum");
791 if (s && (*s == 'y')) {
792 printf (" CRC: %08lX",
7e780369
WD
793 crc32 (0, (const unsigned char *) CFG_FLASH_BASE, flash_size)
794 );
fe8c2806
WD
795 }
796 putc ('\n');
0cb61d7d 797# else /* !CFG_FLASH_CHECKSUM */
fe8c2806 798 print_size (flash_size, "\n");
0cb61d7d 799# endif /* CFG_FLASH_CHECKSUM */
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WD
800 } else {
801 puts (failed);
802 hang ();
803 }
804
805 bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
806 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445
HS
807
808#if defined(CFG_UPDATE_FLASH_SIZE)
809 /* Make a update of the Memctrl. */
810 update_flash_size (flash_size);
811#endif
812
813
7e780369
WD
814# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
815 /* flash mapped at end of memory map */
816 bd->bi_flashoffset = TEXT_BASE + flash_size;
0cb61d7d 817# elif CFG_MONITOR_BASE == CFG_FLASH_BASE
3b57fe0a 818 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 819# else
fe8c2806 820 bd->bi_flashoffset = 0;
0cb61d7d
WD
821# endif
822#else /* CFG_NO_FLASH */
fe8c2806
WD
823
824 bd->bi_flashsize = 0;
825 bd->bi_flashstart = 0;
826 bd->bi_flashoffset = 0;
827#endif /* !CFG_NO_FLASH */
828
829 WATCHDOG_RESET ();
830
831 /* initialize higher level parts of CPU like time base and timers */
832 cpu_init_r ();
833
834 WATCHDOG_RESET ();
835
836 /* initialize malloc() area */
837 mem_malloc_init ();
838 malloc_bin_reloc ();
839
840#ifdef CONFIG_SPI
841# if !defined(CFG_ENV_IS_IN_EEPROM)
842 spi_init_f ();
843# endif
844 spi_init_r ();
845#endif
846
7def6b34 847#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
848 WATCHDOG_RESET ();
849 puts ("NAND: ");
850 nand_init(); /* go init the NAND */
851#endif
852
fe8c2806
WD
853 /* relocate environment function pointers etc. */
854 env_relocate ();
855
856 /*
857 * Fill in missing fields of bd_info.
8bde7f77
WD
858 * We do this here, where we have "normal" access to the
859 * environment; we used to do this still running from ROM,
860 * where had to use getenv_r(), which can be pretty slow when
861 * the environment is in EEPROM.
fe8c2806 862 */
7abf0c58
WD
863
864#if defined(CFG_EXTBDINFO)
865#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
866#if defined(CONFIG_I2CFAST)
867 /*
868 * set bi_iic_fast for linux taking environment variable
869 * "i2cfast" into account
870 */
871 {
872 char *s = getenv ("i2cfast");
873 if (s && ((*s == 'y') || (*s == 'Y'))) {
874 bd->bi_iic_fast[0] = 1;
875 bd->bi_iic_fast[1] = 1;
876 } else {
877 bd->bi_iic_fast[0] = 0;
878 bd->bi_iic_fast[1] = 0;
879 }
880 }
881#else
882 bd->bi_iic_fast[0] = 0;
883 bd->bi_iic_fast[1] = 0;
884#endif /* CONFIG_I2CFAST */
885#endif /* CONFIG_405GP, CONFIG_405EP */
886#endif /* CFG_EXTBDINFO */
887
9045f33c 888#if defined(CONFIG_SC3)
ca43ba18
HS
889 sc3_read_eeprom();
890#endif
d59feffb
HW
891
892#ifdef CFG_ID_EEPROM
893 mac_read_from_eeprom();
894#endif
895
fe8c2806 896 s = getenv ("ethaddr");
4707fb50
BS
897#if defined (CONFIG_MBX) || \
898 defined (CONFIG_RPXCLASSIC) || \
899 defined(CONFIG_IAD210) || \
900 defined(CONFIG_V38B)
fe8c2806
WD
901 if (s == NULL)
902 board_get_enetaddr (bd->bi_enetaddr);
903 else
904#endif
905 for (i = 0; i < 6; ++i) {
906 bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
907 if (s)
908 s = (*e) ? e + 1 : e;
909 }
910#ifdef CONFIG_HERMES
911 if ((gd->board_type >> 16) == 2)
912 bd->bi_ethspeed = gd->board_type & 0xFFFF;
913 else
914 bd->bi_ethspeed = 0xFFFF;
915#endif
916
917#ifdef CONFIG_NX823
918 load_sernum_ethaddr ();
919#endif
920
e2ffd59b 921#ifdef CONFIG_HAS_ETH1
fe8c2806
WD
922 /* handle the 2nd ethernet address */
923
924 s = getenv ("eth1addr");
925
926 for (i = 0; i < 6; ++i) {
927 bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
928 if (s)
929 s = (*e) ? e + 1 : e;
930 }
931#endif
e2ffd59b 932#ifdef CONFIG_HAS_ETH2
fe8c2806
WD
933 /* handle the 3rd ethernet address */
934
935 s = getenv ("eth2addr");
b79316f2 936#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
937 if (s == NULL)
938 board_get_enetaddr(bd->bi_enet2addr);
939 else
940#endif
fe8c2806
WD
941 for (i = 0; i < 6; ++i) {
942 bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
943 if (s)
944 s = (*e) ? e + 1 : e;
945 }
946#endif
947
e2ffd59b 948#ifdef CONFIG_HAS_ETH3
ba56f625
WD
949 /* handle 4th ethernet address */
950 s = getenv("eth3addr");
b79316f2 951#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
ba56f625
WD
952 if (s == NULL)
953 board_get_enetaddr(bd->bi_enet3addr);
954 else
955#endif
956 for (i = 0; i < 6; ++i) {
957 bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
958 if (s)
959 s = (*e) ? e + 1 : e;
960 }
961#endif
fe8c2806
WD
962
963#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
fa230445 964 defined(CONFIG_TQM8272) || \
566a494f
HS
965 defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \
966 defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP)
fe8c2806
WD
967 load_sernum_ethaddr ();
968#endif
969 /* IP Address */
970 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
971
972 WATCHDOG_RESET ();
973
979bdbc7 974#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
975 /*
976 * Do pci configuration
977 */
978 pci_init ();
979#endif
980
981/** leave this here (after malloc(), environment and PCI are working) **/
982 /* Initialize devices */
983 devices_init ();
984
27b207fd
WD
985 /* Initialize the jump table for applications */
986 jumptable_init ();
fe8c2806 987
500856eb
RJ
988#if defined(CONFIG_API)
989 /* Initialize API */
990 api_init ();
991#endif
992
fe8c2806
WD
993 /* Initialize the console (after the relocation and devices init) */
994 console_init_r ();
fe8c2806
WD
995
996#if defined(CONFIG_CCM) || \
997 defined(CONFIG_COGENT) || \
998 defined(CONFIG_CPCI405) || \
999 defined(CONFIG_EVB64260) || \
56f94be3 1000 defined(CONFIG_KUP4K) || \
0608e04d 1001 defined(CONFIG_KUP4X) || \
fe8c2806
WD
1002 defined(CONFIG_LWMON) || \
1003 defined(CONFIG_PCU_E) || \
9045f33c 1004 defined(CONFIG_SC3) || \
fe8c2806
WD
1005 defined(CONFIG_W7O) || \
1006 defined(CONFIG_MISC_INIT_R)
1007 /* miscellaneous platform dependent initialisations */
1008 misc_init_r ();
1009#endif
1010
1011#ifdef CONFIG_HERMES
1012 if (bd->bi_ethspeed != 0xFFFF)
1013 hermes_start_lxt980 ((int) bd->bi_ethspeed);
1014#endif
1015
7def6b34 1016#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
1017 WATCHDOG_RESET ();
1018 puts ("KGDB: ");
1019 kgdb_init ();
1020#endif
1021
9d2b18a0 1022 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
1023
1024 /*
1025 * Enable Interrupts
1026 */
1027 interrupt_init ();
1028
1029 /* Must happen after interrupts are initialized since
1030 * an irq handler gets installed
1031 */
42dfe7a1 1032#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
1033 serial_buffered_init();
1034#endif
1035
566a494f 1036#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
1037 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
1038#endif
1039
1040 udelay (20);
1041
1042 set_timer (0);
1043
fe8c2806
WD
1044 /* Initialize from environment */
1045 if ((s = getenv ("loadaddr")) != NULL) {
1046 load_addr = simple_strtoul (s, NULL, 16);
1047 }
7def6b34 1048#if defined(CONFIG_CMD_NET)
fe8c2806
WD
1049 if ((s = getenv ("bootfile")) != NULL) {
1050 copy_filename (BootFile, s, sizeof (BootFile));
1051 }
b3aff0cb 1052#endif
fe8c2806
WD
1053
1054 WATCHDOG_RESET ();
1055
7def6b34 1056#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
1057 WATCHDOG_RESET ();
1058 puts ("SCSI: ");
1059 scsi_init ();
1060#endif
1061
7def6b34 1062#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
1063 WATCHDOG_RESET ();
1064 puts ("DOC: ");
1065 doc_init ();
1066#endif
1067
7def6b34 1068#if defined(CONFIG_CMD_NET)
63ff004c 1069#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
1070 WATCHDOG_RESET ();
1071 puts ("Net: ");
63ff004c 1072#endif
fe8c2806
WD
1073 eth_initialize (bd);
1074#endif
1075
7def6b34 1076#if defined(CONFIG_CMD_NET) && ( \
63ff004c
MB
1077 defined(CONFIG_CCM) || \
1078 defined(CONFIG_ELPT860) || \
1079 defined(CONFIG_EP8260) || \
1080 defined(CONFIG_IP860) || \
1081 defined(CONFIG_IVML24) || \
1082 defined(CONFIG_IVMS8) || \
1083 defined(CONFIG_MPC8260ADS) || \
1084 defined(CONFIG_MPC8266ADS) || \
1085 defined(CONFIG_MPC8560ADS) || \
1086 defined(CONFIG_PCU_E) || \
1087 defined(CONFIG_RPXSUPER) || \
1088 defined(CONFIG_STXGP3) || \
1089 defined(CONFIG_SPD823TS) || \
1090 defined(CONFIG_RESET_PHY_R) )
1091
1092 WATCHDOG_RESET ();
1093 debug ("Reset Ethernet PHY\n");
1094 reset_phy ();
1095#endif
1096
fe8c2806 1097#ifdef CONFIG_POST
6dff5529 1098 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
1099#endif
1100
7def6b34
JL
1101#if defined(CONFIG_CMD_PCMCIA) \
1102 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
1103 WATCHDOG_RESET ();
1104 puts ("PCMCIA:");
1105 pcmcia_init ();
1106#endif
1107
7def6b34 1108#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
1109 WATCHDOG_RESET ();
1110# ifdef CONFIG_IDE_8xx_PCCARD
1111 puts ("PCMCIA:");
1112# else
1113 puts ("IDE: ");
1114#endif
ca43ba18
HS
1115#if defined(CONFIG_START_IDE)
1116 if (board_start_ide())
1117 ide_init ();
1118#else
fe8c2806 1119 ide_init ();
ca43ba18 1120#endif
b3aff0cb 1121#endif
fe8c2806 1122
cd54081c
DL
1123#if defined(CONFIG_CMD_SATA)
1124 puts ("SATA: ");
1125 sata_initialize ();
1126#endif
1127
fe8c2806
WD
1128#ifdef CONFIG_LAST_STAGE_INIT
1129 WATCHDOG_RESET ();
1130 /*
1131 * Some parts can be only initialized if all others (like
1132 * Interrupts) are up and running (i.e. the PC-style ISA
1133 * keyboard).
1134 */
1135 last_stage_init ();
1136#endif
1137
7def6b34 1138#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1139 WATCHDOG_RESET ();
1140 bedbug_init ();
1141#endif
1142
228f29ac 1143#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1144 /*
1145 * Export available size of memory for Linux,
1146 * taking into account the protected RAM at top of memory
1147 */
1148 {
1149 ulong pram;
fe8c2806 1150 uchar memsz[32];
228f29ac
WD
1151#ifdef CONFIG_PRAM
1152 char *s;
fe8c2806
WD
1153
1154 if ((s = getenv ("pram")) != NULL) {
1155 pram = simple_strtoul (s, NULL, 10);
1156 } else {
1157 pram = CONFIG_PRAM;
1158 }
228f29ac
WD
1159#else
1160 pram=0;
1161#endif
1162#ifdef CONFIG_LOGBUFFER
3d610186 1163#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1164 /* Also take the logbuffer into account (pram is in kB) */
1165 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1166#endif
228f29ac 1167#endif
77ddac94
WD
1168 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1169 setenv ("mem", (char *)memsz);
fe8c2806
WD
1170 }
1171#endif
1172
1c43771b
WD
1173#ifdef CONFIG_PS2KBD
1174 puts ("PS/2: ");
1175 kbd_init();
1176#endif
1177
4532cb69
WD
1178#ifdef CONFIG_MODEM_SUPPORT
1179 {
1180 extern int do_mdm_init;
1181 do_mdm_init = gd->do_mdm_init;
1182 }
1183#endif
1184
fe8c2806
WD
1185 /* Initialization complete - start the monitor */
1186
1187 /* main_loop() can return to retry autoboot, if so just run it again. */
1188 for (;;) {
1189 WATCHDOG_RESET ();
1190 main_loop ();
1191 }
1192
1193 /* NOTREACHED - no way out of command loop except booting */
1194}
1195
1196void hang (void)
1197{
1198 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1199 show_boot_progress(-30);
fe8c2806
WD
1200 for (;;);
1201}
1202
4532cb69
WD
1203#ifdef CONFIG_MODEM_SUPPORT
1204/* called from main loop (common/main.c) */
77ddac94
WD
1205/* 'inline' - We have to do it fast */
1206static inline void mdm_readline(char *buf, int bufsiz)
1207{
1208 char c;
1209 char *p;
1210 int n;
1211
1212 n = 0;
1213 p = buf;
1214 for(;;) {
1215 c = serial_getc();
1216
1217 /* dbg("(%c)", c); */
1218
1219 switch(c) {
1220 case '\r':
1221 break;
1222 case '\n':
1223 *p = '\0';
1224 return;
1225
1226 default:
1227 if(n++ > bufsiz) {
1228 *p = '\0';
1229 return; /* sanity check */
1230 }
1231 *p = c;
1232 p++;
1233 break;
1234 }
1235 }
1236}
1237
4532cb69
WD
1238extern void dbg(const char *fmt, ...);
1239int mdm_init (void)
1240{
1241 char env_str[16];
1242 char *init_str;
1243 int i;
1244 extern char console_buffer[];
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1245 extern void enable_putc(void);
1246 extern int hwflow_onoff(int);
1247
1248 enable_putc(); /* enable serial_putc() */
1249
1250#ifdef CONFIG_HWFLOW
1251 init_str = getenv("mdm_flow_control");
1252 if (init_str && (strcmp(init_str, "rts/cts") == 0))
1253 hwflow_onoff (1);
1254 else
1255 hwflow_onoff(-1);
1256#endif
1257
1258 for (i = 1;;i++) {
1259 sprintf(env_str, "mdm_init%d", i);
1260 if ((init_str = getenv(env_str)) != NULL) {
1261 serial_puts(init_str);
1262 serial_puts("\n");
1263 for(;;) {
1264 mdm_readline(console_buffer, CFG_CBSIZE);
1265 dbg("ini%d: [%s]", i, console_buffer);
1266
1267 if ((strcmp(console_buffer, "OK") == 0) ||
1268 (strcmp(console_buffer, "ERROR") == 0)) {
1269 dbg("ini%d: cmd done", i);
1270 break;
1271 } else /* in case we are originating call ... */
1272 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1273 dbg("ini%d: connect", i);
1274 return 0;
1275 }
1276 }
1277 } else
1278 break; /* no init string - stop modem init */
1279
1280 udelay(100000);
1281 }
1282
1283 udelay(100000);
1284
1285 /* final stage - wait for connect */
1286 for(;i > 1;) { /* if 'i' > 1 - wait for connection
1287 message from modem */
1288 mdm_readline(console_buffer, CFG_CBSIZE);
1289 dbg("ini_f: [%s]", console_buffer);
1290 if (strncmp(console_buffer, "CONNECT", 7) == 0) {
1291 dbg("ini_f: connected");
1292 return 0;
1293 }
1294 }
1295
1296 return 0;
1297}
1298
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1299#endif
1300
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1301#if 0 /* We could use plain global data, but the resulting code is bigger */
1302/*
1303 * Pointer to initial global data area
1304 *
1305 * Here we initialize it.
1306 */
1307#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1308#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
1309DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
1310#endif /* 0 */
1311
1312/************************************************************************/