]>
Commit | Line | Data |
---|---|---|
c7a34993 MM |
1 | /* |
2 | * The PCI Utilities -- Show Capabilities | |
3 | * | |
b47b5bd4 | 4 | * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz> |
c7a34993 MM |
5 | * |
6 | * Can be freely distributed and used under the terms of the GNU GPL. | |
7 | */ | |
8 | ||
9 | #include <stdio.h> | |
10 | #include <string.h> | |
11 | ||
12 | #include "lspci.h" | |
13 | ||
14 | static void | |
15 | cap_pm(struct device *d, int where, int cap) | |
16 | { | |
17 | int t, b; | |
18 | static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 }; | |
19 | ||
20 | printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK); | |
21 | if (verbose < 2) | |
22 | return; | |
23 | printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n", | |
24 | FLAG(cap, PCI_PM_CAP_PME_CLOCK), | |
25 | FLAG(cap, PCI_PM_CAP_DSI), | |
26 | FLAG(cap, PCI_PM_CAP_D1), | |
27 | FLAG(cap, PCI_PM_CAP_D2), | |
02d761b4 | 28 | pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6], |
c7a34993 MM |
29 | FLAG(cap, PCI_PM_CAP_PME_D0), |
30 | FLAG(cap, PCI_PM_CAP_PME_D1), | |
31 | FLAG(cap, PCI_PM_CAP_PME_D2), | |
32 | FLAG(cap, PCI_PM_CAP_PME_D3_HOT), | |
33 | FLAG(cap, PCI_PM_CAP_PME_D3_COLD)); | |
34 | if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL)) | |
35 | return; | |
36 | t = get_conf_word(d, where + PCI_PM_CTRL); | |
1c702fac | 37 | printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n", |
c7a34993 | 38 | t & PCI_PM_CTRL_STATE_MASK, |
1c702fac | 39 | FLAG(t, PCI_PM_CTRL_NO_SOFT_RST), |
c7a34993 MM |
40 | FLAG(t, PCI_PM_CTRL_PME_ENABLE), |
41 | (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9, | |
42 | (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13, | |
43 | FLAG(t, PCI_PM_CTRL_PME_STATUS)); | |
44 | b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS); | |
45 | if (b) | |
46 | printf("\t\tBridge: PM%c B3%c\n", | |
47 | FLAG(t, PCI_PM_BPCC_ENABLE), | |
48 | FLAG(~t, PCI_PM_PPB_B2_B3)); | |
49 | } | |
50 | ||
51 | static void | |
52 | format_agp_rate(int rate, char *buf, int agp3) | |
53 | { | |
54 | char *c = buf; | |
55 | int i; | |
56 | ||
57 | for (i=0; i<=2; i++) | |
58 | if (rate & (1 << i)) | |
59 | { | |
60 | if (c != buf) | |
61 | *c++ = ','; | |
62 | c += sprintf(c, "x%d", 1 << (i + 2*agp3)); | |
63 | } | |
64 | if (c != buf) | |
65 | *c = 0; | |
66 | else | |
67 | strcpy(buf, "<none>"); | |
68 | } | |
69 | ||
70 | static void | |
71 | cap_agp(struct device *d, int where, int cap) | |
72 | { | |
73 | u32 t; | |
74 | char rate[16]; | |
75 | int ver, rev; | |
76 | int agp3 = 0; | |
77 | ||
78 | ver = (cap >> 4) & 0x0f; | |
79 | rev = cap & 0x0f; | |
80 | printf("AGP version %x.%x\n", ver, rev); | |
81 | if (verbose < 2) | |
82 | return; | |
83 | if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS)) | |
84 | return; | |
85 | t = get_conf_long(d, where + PCI_AGP_STATUS); | |
86 | if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3)) | |
87 | agp3 = 1; | |
88 | format_agp_rate(t & 7, rate, agp3); | |
89 | printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n", | |
90 | ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1, | |
91 | FLAG(t, PCI_AGP_STATUS_ISOCH), | |
92 | ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13), | |
93 | ((t & PCI_AGP_STATUS_CAL_MASK) >> 10), | |
94 | FLAG(t, PCI_AGP_STATUS_SBA), | |
95 | FLAG(t, PCI_AGP_STATUS_ITA_COH), | |
96 | FLAG(t, PCI_AGP_STATUS_GART64), | |
97 | FLAG(t, PCI_AGP_STATUS_HTRANS), | |
98 | FLAG(t, PCI_AGP_STATUS_64BIT), | |
99 | FLAG(t, PCI_AGP_STATUS_FW), | |
100 | FLAG(t, PCI_AGP_STATUS_AGP3), | |
101 | rate); | |
102 | t = get_conf_long(d, where + PCI_AGP_COMMAND); | |
103 | format_agp_rate(t & 7, rate, agp3); | |
104 | printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n", | |
105 | ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1, | |
106 | ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13), | |
107 | ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10), | |
108 | FLAG(t, PCI_AGP_COMMAND_SBA), | |
109 | FLAG(t, PCI_AGP_COMMAND_AGP), | |
110 | FLAG(t, PCI_AGP_COMMAND_GART64), | |
111 | FLAG(t, PCI_AGP_COMMAND_64BIT), | |
112 | FLAG(t, PCI_AGP_COMMAND_FW), | |
113 | rate); | |
114 | } | |
115 | ||
116 | static void | |
117 | cap_pcix_nobridge(struct device *d, int where) | |
118 | { | |
119 | u16 command; | |
120 | u32 status; | |
121 | static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 }; | |
122 | ||
123 | printf("PCI-X non-bridge device\n"); | |
124 | ||
125 | if (verbose < 2) | |
126 | return; | |
127 | ||
128 | if (!config_fetch(d, where + PCI_PCIX_STATUS, 4)) | |
129 | return; | |
130 | ||
131 | command = get_conf_word(d, where + PCI_PCIX_COMMAND); | |
132 | status = get_conf_long(d, where + PCI_PCIX_STATUS); | |
133 | printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n", | |
134 | FLAG(command, PCI_PCIX_COMMAND_DPERE), | |
135 | FLAG(command, PCI_PCIX_COMMAND_ERO), | |
136 | 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)), | |
137 | max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]); | |
138 | printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n", | |
02d761b4 BH |
139 | (status & PCI_PCIX_STATUS_BUS) >> 8, |
140 | (status & PCI_PCIX_STATUS_DEVICE) >> 3, | |
c7a34993 MM |
141 | (status & PCI_PCIX_STATUS_FUNCTION), |
142 | FLAG(status, PCI_PCIX_STATUS_64BIT), | |
143 | FLAG(status, PCI_PCIX_STATUS_133MHZ), | |
144 | FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED), | |
145 | FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC), | |
146 | ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"), | |
02d761b4 BH |
147 | 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)), |
148 | max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23], | |
149 | 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)), | |
c7a34993 MM |
150 | FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS), |
151 | FLAG(status, PCI_PCIX_STATUS_266MHZ), | |
152 | FLAG(status, PCI_PCIX_STATUS_533MHZ)); | |
153 | } | |
154 | ||
155 | static void | |
156 | cap_pcix_bridge(struct device *d, int where) | |
157 | { | |
158 | static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" }; | |
159 | u16 secstatus; | |
160 | u32 status, upstcr, downstcr; | |
161 | ||
162 | printf("PCI-X bridge device\n"); | |
163 | ||
164 | if (verbose < 2) | |
165 | return; | |
166 | ||
167 | if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12)) | |
168 | return; | |
169 | ||
170 | secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS); | |
171 | printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n", | |
172 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT), | |
173 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ), | |
174 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED), | |
175 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC), | |
176 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN), | |
177 | FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED), | |
02d761b4 | 178 | sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]); |
c7a34993 MM |
179 | status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS); |
180 | printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n", | |
02d761b4 BH |
181 | (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8, |
182 | (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3, | |
c7a34993 MM |
183 | (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), |
184 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT), | |
185 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ), | |
186 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED), | |
187 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC), | |
188 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN), | |
189 | FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED)); | |
190 | upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL); | |
191 | printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n", | |
192 | (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), | |
193 | (upstcr >> 16) & 0xffff); | |
194 | downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL); | |
195 | printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n", | |
196 | (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), | |
197 | (downstcr >> 16) & 0xffff); | |
198 | } | |
199 | ||
200 | static void | |
201 | cap_pcix(struct device *d, int where) | |
202 | { | |
203 | switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f) | |
204 | { | |
205 | case PCI_HEADER_TYPE_NORMAL: | |
206 | cap_pcix_nobridge(d, where); | |
207 | break; | |
208 | case PCI_HEADER_TYPE_BRIDGE: | |
209 | cap_pcix_bridge(d, where); | |
210 | break; | |
211 | } | |
212 | } | |
213 | ||
214 | static inline char * | |
215 | ht_link_width(unsigned width) | |
216 | { | |
217 | static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" }; | |
218 | return widths[width]; | |
219 | } | |
220 | ||
221 | static inline char * | |
222 | ht_link_freq(unsigned freq) | |
223 | { | |
224 | static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz", | |
225 | "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" }; | |
226 | return freqs[freq]; | |
227 | } | |
228 | ||
229 | static void | |
230 | cap_ht_pri(struct device *d, int where, int cmd) | |
231 | { | |
232 | u16 lctr0, lcnf0, lctr1, lcnf1, eh; | |
233 | u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn; | |
c7a34993 MM |
234 | |
235 | printf("HyperTransport: Slave or Primary Interface\n"); | |
236 | if (verbose < 2) | |
237 | return; | |
238 | ||
239 | if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0)) | |
240 | return; | |
241 | rid = get_conf_byte(d, where + PCI_HT_PRI_RID); | |
242 | if (rid < 0x22 && rid > 0x11) | |
243 | printf("\t\t!!! Possibly incomplete decoding\n"); | |
244 | ||
0089d489 | 245 | printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c", |
c7a34993 MM |
246 | (cmd & PCI_HT_PRI_CMD_BUID), |
247 | (cmd & PCI_HT_PRI_CMD_UC) >> 5, | |
248 | FLAG(cmd, PCI_HT_PRI_CMD_MH), | |
0089d489 | 249 | FLAG(cmd, PCI_HT_PRI_CMD_DD)); |
c7a34993 | 250 | if (rid >= 0x22) |
0089d489 MM |
251 | printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL)); |
252 | printf("\n"); | |
253 | ||
254 | lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0); | |
255 | printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x", | |
c7a34993 MM |
256 | FLAG(lctr0, PCI_HT_LCTR_CFLE), |
257 | FLAG(lctr0, PCI_HT_LCTR_CST), | |
258 | FLAG(lctr0, PCI_HT_LCTR_CFE), | |
259 | FLAG(lctr0, PCI_HT_LCTR_LKFAIL), | |
260 | FLAG(lctr0, PCI_HT_LCTR_INIT), | |
261 | FLAG(lctr0, PCI_HT_LCTR_EOC), | |
262 | FLAG(lctr0, PCI_HT_LCTR_TXO), | |
0089d489 | 263 | (lctr0 & PCI_HT_LCTR_CRCERR) >> 8); |
c7a34993 | 264 | if (rid >= 0x22) |
0089d489 MM |
265 | printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", |
266 | FLAG(lctr0, PCI_HT_LCTR_ISOCEN), | |
267 | FLAG(lctr0, PCI_HT_LCTR_LSEN), | |
268 | FLAG(lctr0, PCI_HT_LCTR_EXTCTL), | |
269 | FLAG(lctr0, PCI_HT_LCTR_64B)); | |
270 | printf("\n"); | |
271 | ||
272 | lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); | |
273 | if (rid < 0x22) | |
274 | printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", | |
275 | ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), | |
276 | ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), | |
277 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), | |
278 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12)); | |
c7a34993 | 279 | else |
0089d489 MM |
280 | printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", |
281 | ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), | |
282 | FLAG(lcnf0, PCI_HT_LCNF_DFI), | |
283 | ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), | |
284 | FLAG(lcnf0, PCI_HT_LCNF_DFO), | |
285 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), | |
286 | FLAG(lcnf0, PCI_HT_LCNF_DFIE), | |
287 | ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), | |
288 | FLAG(lcnf0, PCI_HT_LCNF_DFOE)); | |
289 | ||
c7a34993 | 290 | lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1); |
0089d489 | 291 | printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x", |
c7a34993 MM |
292 | FLAG(lctr1, PCI_HT_LCTR_CFLE), |
293 | FLAG(lctr1, PCI_HT_LCTR_CST), | |
294 | FLAG(lctr1, PCI_HT_LCTR_CFE), | |
295 | FLAG(lctr1, PCI_HT_LCTR_LKFAIL), | |
296 | FLAG(lctr1, PCI_HT_LCTR_INIT), | |
297 | FLAG(lctr1, PCI_HT_LCTR_EOC), | |
298 | FLAG(lctr1, PCI_HT_LCTR_TXO), | |
0089d489 MM |
299 | (lctr1 & PCI_HT_LCTR_CRCERR) >> 8); |
300 | if (rid >= 0x22) | |
301 | printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", | |
c7a34993 MM |
302 | FLAG(lctr1, PCI_HT_LCTR_ISOCEN), |
303 | FLAG(lctr1, PCI_HT_LCTR_LSEN), | |
304 | FLAG(lctr1, PCI_HT_LCTR_EXTCTL), | |
305 | FLAG(lctr1, PCI_HT_LCTR_64B)); | |
0089d489 MM |
306 | printf("\n"); |
307 | ||
c7a34993 | 308 | lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1); |
0089d489 MM |
309 | if (rid < 0x22) |
310 | printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", | |
311 | ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), | |
312 | ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), | |
313 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), | |
314 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12)); | |
c7a34993 | 315 | else |
0089d489 MM |
316 | printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", |
317 | ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), | |
318 | FLAG(lcnf1, PCI_HT_LCNF_DFI), | |
319 | ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), | |
320 | FLAG(lcnf1, PCI_HT_LCNF_DFO), | |
321 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), | |
322 | FLAG(lcnf1, PCI_HT_LCNF_DFIE), | |
323 | ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), | |
324 | FLAG(lcnf1, PCI_HT_LCNF_DFOE)); | |
325 | ||
c7a34993 MM |
326 | printf("\t\tRevision ID: %u.%02u\n", |
327 | (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); | |
328 | if (rid < 0x22) | |
329 | return; | |
0089d489 | 330 | |
c7a34993 MM |
331 | lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0); |
332 | printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ)); | |
333 | printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n", | |
334 | FLAG(lfrer0, PCI_HT_LFRER_PROT), | |
335 | FLAG(lfrer0, PCI_HT_LFRER_OV), | |
336 | FLAG(lfrer0, PCI_HT_LFRER_EOC), | |
337 | FLAG(lfrer0, PCI_HT_LFRER_CTLT)); | |
0089d489 | 338 | |
c7a34993 MM |
339 | lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0); |
340 | printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n", | |
341 | FLAG(lfcap0, PCI_HT_LFCAP_200), | |
342 | FLAG(lfcap0, PCI_HT_LFCAP_300), | |
343 | FLAG(lfcap0, PCI_HT_LFCAP_400), | |
344 | FLAG(lfcap0, PCI_HT_LFCAP_500), | |
345 | FLAG(lfcap0, PCI_HT_LFCAP_600), | |
346 | FLAG(lfcap0, PCI_HT_LFCAP_800), | |
347 | FLAG(lfcap0, PCI_HT_LFCAP_1000), | |
348 | FLAG(lfcap0, PCI_HT_LFCAP_1200), | |
349 | FLAG(lfcap0, PCI_HT_LFCAP_1400), | |
350 | FLAG(lfcap0, PCI_HT_LFCAP_1600), | |
351 | FLAG(lfcap0, PCI_HT_LFCAP_VEND)); | |
0089d489 | 352 | |
c7a34993 MM |
353 | ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR); |
354 | printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n", | |
355 | FLAG(ftr, PCI_HT_FTR_ISOCFC), | |
356 | FLAG(ftr, PCI_HT_FTR_LDTSTOP), | |
357 | FLAG(ftr, PCI_HT_FTR_CRCTM), | |
358 | FLAG(ftr, PCI_HT_FTR_ECTLT), | |
359 | FLAG(ftr, PCI_HT_FTR_64BA), | |
360 | FLAG(ftr, PCI_HT_FTR_UIDRD)); | |
0089d489 | 361 | |
c7a34993 MM |
362 | lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1); |
363 | printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ)); | |
364 | printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n", | |
365 | FLAG(lfrer1, PCI_HT_LFRER_PROT), | |
366 | FLAG(lfrer1, PCI_HT_LFRER_OV), | |
367 | FLAG(lfrer1, PCI_HT_LFRER_EOC), | |
368 | FLAG(lfrer1, PCI_HT_LFRER_CTLT)); | |
0089d489 | 369 | |
c7a34993 MM |
370 | lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1); |
371 | printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n", | |
372 | FLAG(lfcap1, PCI_HT_LFCAP_200), | |
373 | FLAG(lfcap1, PCI_HT_LFCAP_300), | |
374 | FLAG(lfcap1, PCI_HT_LFCAP_400), | |
375 | FLAG(lfcap1, PCI_HT_LFCAP_500), | |
376 | FLAG(lfcap1, PCI_HT_LFCAP_600), | |
377 | FLAG(lfcap1, PCI_HT_LFCAP_800), | |
378 | FLAG(lfcap1, PCI_HT_LFCAP_1000), | |
379 | FLAG(lfcap1, PCI_HT_LFCAP_1200), | |
380 | FLAG(lfcap1, PCI_HT_LFCAP_1400), | |
381 | FLAG(lfcap1, PCI_HT_LFCAP_1600), | |
382 | FLAG(lfcap1, PCI_HT_LFCAP_VEND)); | |
0089d489 | 383 | |
c7a34993 MM |
384 | eh = get_conf_word(d, where + PCI_HT_PRI_EH); |
385 | printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n", | |
386 | FLAG(eh, PCI_HT_EH_PFLE), | |
387 | FLAG(eh, PCI_HT_EH_OFLE), | |
388 | FLAG(eh, PCI_HT_EH_PFE), | |
389 | FLAG(eh, PCI_HT_EH_OFE), | |
390 | FLAG(eh, PCI_HT_EH_EOCFE), | |
391 | FLAG(eh, PCI_HT_EH_RFE), | |
392 | FLAG(eh, PCI_HT_EH_CRCFE), | |
393 | FLAG(eh, PCI_HT_EH_SERRFE), | |
394 | FLAG(eh, PCI_HT_EH_CF), | |
395 | FLAG(eh, PCI_HT_EH_RE), | |
396 | FLAG(eh, PCI_HT_EH_PNFE), | |
397 | FLAG(eh, PCI_HT_EH_ONFE), | |
398 | FLAG(eh, PCI_HT_EH_EOCNFE), | |
399 | FLAG(eh, PCI_HT_EH_RNFE), | |
400 | FLAG(eh, PCI_HT_EH_CRCNFE), | |
401 | FLAG(eh, PCI_HT_EH_SERRNFE)); | |
0089d489 | 402 | |
c7a34993 MM |
403 | mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU); |
404 | mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU); | |
405 | printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu); | |
0089d489 | 406 | |
c7a34993 MM |
407 | bn = get_conf_byte(d, where + PCI_HT_PRI_BN); |
408 | printf("\t\tBus Number: %02x\n", bn); | |
409 | } | |
410 | ||
411 | static void | |
412 | cap_ht_sec(struct device *d, int where, int cmd) | |
413 | { | |
414 | u16 lctr, lcnf, ftr, eh; | |
415 | u8 rid, lfrer, lfcap, mbu, mlu; | |
416 | char *fmt; | |
417 | ||
418 | printf("HyperTransport: Host or Secondary Interface\n"); | |
419 | if (verbose < 2) | |
420 | return; | |
421 | ||
422 | if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR)) | |
423 | return; | |
424 | rid = get_conf_byte(d, where + PCI_HT_SEC_RID); | |
425 | if (rid < 0x22 && rid > 0x11) | |
426 | printf("\t\t!!! Possibly incomplete decoding\n"); | |
427 | ||
428 | if (rid >= 0x22) | |
429 | fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n"; | |
430 | else | |
431 | fmt = "\t\tCommand: WarmRst%c DblEnd%c\n"; | |
432 | printf(fmt, | |
433 | FLAG(cmd, PCI_HT_SEC_CMD_WR), | |
434 | FLAG(cmd, PCI_HT_SEC_CMD_DE), | |
435 | (cmd & PCI_HT_SEC_CMD_DN) >> 2, | |
436 | FLAG(cmd, PCI_HT_SEC_CMD_CS), | |
437 | FLAG(cmd, PCI_HT_SEC_CMD_HH), | |
438 | FLAG(cmd, PCI_HT_SEC_CMD_AS), | |
439 | FLAG(cmd, PCI_HT_SEC_CMD_HIECE), | |
440 | FLAG(cmd, PCI_HT_SEC_CMD_DUL)); | |
441 | lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR); | |
442 | if (rid >= 0x22) | |
443 | fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n"; | |
444 | else | |
445 | fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n"; | |
446 | printf(fmt, | |
447 | FLAG(lctr, PCI_HT_LCTR_CFLE), | |
448 | FLAG(lctr, PCI_HT_LCTR_CST), | |
449 | FLAG(lctr, PCI_HT_LCTR_CFE), | |
450 | FLAG(lctr, PCI_HT_LCTR_LKFAIL), | |
451 | FLAG(lctr, PCI_HT_LCTR_INIT), | |
452 | FLAG(lctr, PCI_HT_LCTR_EOC), | |
453 | FLAG(lctr, PCI_HT_LCTR_TXO), | |
454 | (lctr & PCI_HT_LCTR_CRCERR) >> 8, | |
455 | FLAG(lctr, PCI_HT_LCTR_ISOCEN), | |
456 | FLAG(lctr, PCI_HT_LCTR_LSEN), | |
457 | FLAG(lctr, PCI_HT_LCTR_EXTCTL), | |
458 | FLAG(lctr, PCI_HT_LCTR_64B)); | |
459 | lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF); | |
460 | if (rid >= 0x22) | |
461 | fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; | |
462 | else | |
463 | fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; | |
464 | printf(fmt, | |
465 | ht_link_width(lcnf & PCI_HT_LCNF_MLWI), | |
466 | ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4), | |
467 | ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8), | |
468 | ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12), | |
469 | FLAG(lcnf, PCI_HT_LCNF_DFI), | |
470 | FLAG(lcnf, PCI_HT_LCNF_DFO), | |
471 | FLAG(lcnf, PCI_HT_LCNF_DFIE), | |
472 | FLAG(lcnf, PCI_HT_LCNF_DFOE)); | |
473 | printf("\t\tRevision ID: %u.%02u\n", | |
474 | (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); | |
475 | if (rid < 0x22) | |
476 | return; | |
477 | lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER); | |
478 | printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ)); | |
479 | printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n", | |
480 | FLAG(lfrer, PCI_HT_LFRER_PROT), | |
481 | FLAG(lfrer, PCI_HT_LFRER_OV), | |
482 | FLAG(lfrer, PCI_HT_LFRER_EOC), | |
483 | FLAG(lfrer, PCI_HT_LFRER_CTLT)); | |
484 | lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP); | |
485 | printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n", | |
486 | FLAG(lfcap, PCI_HT_LFCAP_200), | |
487 | FLAG(lfcap, PCI_HT_LFCAP_300), | |
488 | FLAG(lfcap, PCI_HT_LFCAP_400), | |
489 | FLAG(lfcap, PCI_HT_LFCAP_500), | |
490 | FLAG(lfcap, PCI_HT_LFCAP_600), | |
491 | FLAG(lfcap, PCI_HT_LFCAP_800), | |
492 | FLAG(lfcap, PCI_HT_LFCAP_1000), | |
493 | FLAG(lfcap, PCI_HT_LFCAP_1200), | |
494 | FLAG(lfcap, PCI_HT_LFCAP_1400), | |
495 | FLAG(lfcap, PCI_HT_LFCAP_1600), | |
496 | FLAG(lfcap, PCI_HT_LFCAP_VEND)); | |
497 | ftr = get_conf_word(d, where + PCI_HT_SEC_FTR); | |
498 | printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n", | |
499 | FLAG(ftr, PCI_HT_FTR_ISOCFC), | |
500 | FLAG(ftr, PCI_HT_FTR_LDTSTOP), | |
501 | FLAG(ftr, PCI_HT_FTR_CRCTM), | |
502 | FLAG(ftr, PCI_HT_FTR_ECTLT), | |
503 | FLAG(ftr, PCI_HT_FTR_64BA), | |
504 | FLAG(ftr, PCI_HT_FTR_UIDRD), | |
505 | FLAG(ftr, PCI_HT_SEC_FTR_EXTRS), | |
506 | FLAG(ftr, PCI_HT_SEC_FTR_UCNFE)); | |
507 | if (ftr & PCI_HT_SEC_FTR_EXTRS) | |
508 | { | |
509 | eh = get_conf_word(d, where + PCI_HT_SEC_EH); | |
510 | printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n", | |
511 | FLAG(eh, PCI_HT_EH_PFLE), | |
512 | FLAG(eh, PCI_HT_EH_OFLE), | |
513 | FLAG(eh, PCI_HT_EH_PFE), | |
514 | FLAG(eh, PCI_HT_EH_OFE), | |
515 | FLAG(eh, PCI_HT_EH_EOCFE), | |
516 | FLAG(eh, PCI_HT_EH_RFE), | |
517 | FLAG(eh, PCI_HT_EH_CRCFE), | |
518 | FLAG(eh, PCI_HT_EH_SERRFE), | |
519 | FLAG(eh, PCI_HT_EH_CF), | |
520 | FLAG(eh, PCI_HT_EH_RE), | |
521 | FLAG(eh, PCI_HT_EH_PNFE), | |
522 | FLAG(eh, PCI_HT_EH_ONFE), | |
523 | FLAG(eh, PCI_HT_EH_EOCNFE), | |
524 | FLAG(eh, PCI_HT_EH_RNFE), | |
525 | FLAG(eh, PCI_HT_EH_CRCNFE), | |
526 | FLAG(eh, PCI_HT_EH_SERRNFE)); | |
527 | mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU); | |
528 | mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU); | |
529 | printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu); | |
530 | } | |
531 | } | |
532 | ||
533 | static void | |
534 | cap_ht(struct device *d, int where, int cmd) | |
535 | { | |
536 | int type; | |
537 | ||
538 | switch (cmd & PCI_HT_CMD_TYP_HI) | |
539 | { | |
540 | case PCI_HT_CMD_TYP_HI_PRI: | |
541 | cap_ht_pri(d, where, cmd); | |
542 | return; | |
543 | case PCI_HT_CMD_TYP_HI_SEC: | |
544 | cap_ht_sec(d, where, cmd); | |
545 | return; | |
546 | } | |
547 | ||
548 | type = cmd & PCI_HT_CMD_TYP; | |
549 | switch (type) | |
550 | { | |
551 | case PCI_HT_CMD_TYP_SW: | |
552 | printf("HyperTransport: Switch\n"); | |
553 | break; | |
554 | case PCI_HT_CMD_TYP_IDC: | |
555 | printf("HyperTransport: Interrupt Discovery and Configuration\n"); | |
556 | break; | |
557 | case PCI_HT_CMD_TYP_RID: | |
558 | printf("HyperTransport: Revision ID: %u.%02u\n", | |
559 | (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN)); | |
560 | break; | |
561 | case PCI_HT_CMD_TYP_UIDC: | |
562 | printf("HyperTransport: UnitID Clumping\n"); | |
563 | break; | |
564 | case PCI_HT_CMD_TYP_ECSA: | |
565 | printf("HyperTransport: Extended Configuration Space Access\n"); | |
566 | break; | |
567 | case PCI_HT_CMD_TYP_AM: | |
568 | printf("HyperTransport: Address Mapping\n"); | |
569 | break; | |
570 | case PCI_HT_CMD_TYP_MSIM: | |
571 | printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n", | |
572 | FLAG(cmd, PCI_HT_MSIM_CMD_EN), | |
573 | FLAG(cmd, PCI_HT_MSIM_CMD_FIXD)); | |
574 | if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD)) | |
575 | { | |
576 | u32 offl, offh; | |
577 | if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8)) | |
578 | break; | |
579 | offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO); | |
580 | offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI); | |
6811edb8 | 581 | printf("\t\tMapping Address Base: %016" PCI_U64_FMT_X "\n", ((u64)offh << 32) | (offl & ~0xfffff)); |
c7a34993 MM |
582 | } |
583 | break; | |
584 | case PCI_HT_CMD_TYP_DR: | |
585 | printf("HyperTransport: DirectRoute\n"); | |
586 | break; | |
587 | case PCI_HT_CMD_TYP_VCS: | |
588 | printf("HyperTransport: VCSet\n"); | |
589 | break; | |
590 | case PCI_HT_CMD_TYP_RM: | |
591 | printf("HyperTransport: Retry Mode\n"); | |
592 | break; | |
593 | case PCI_HT_CMD_TYP_X86: | |
594 | printf("HyperTransport: X86 (reserved)\n"); | |
595 | break; | |
596 | default: | |
597 | printf("HyperTransport: #%02x\n", type >> 11); | |
598 | } | |
599 | } | |
600 | ||
601 | static void | |
602 | cap_msi(struct device *d, int where, int cap) | |
603 | { | |
604 | int is64; | |
605 | u32 t; | |
606 | u16 w; | |
607 | ||
04885ef7 MW |
608 | printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n", |
609 | FLAG(cap, PCI_MSI_FLAGS_ENABLE), | |
c7a34993 MM |
610 | 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4), |
611 | 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1), | |
04885ef7 MW |
612 | FLAG(cap, PCI_MSI_FLAGS_MASK_BIT), |
613 | FLAG(cap, PCI_MSI_FLAGS_64BIT)); | |
c7a34993 MM |
614 | if (verbose < 2) |
615 | return; | |
616 | is64 = cap & PCI_MSI_FLAGS_64BIT; | |
617 | if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO)) | |
618 | return; | |
619 | printf("\t\tAddress: "); | |
620 | if (is64) | |
621 | { | |
622 | t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI); | |
623 | w = get_conf_word(d, where + PCI_MSI_DATA_64); | |
624 | printf("%08x", t); | |
625 | } | |
626 | else | |
627 | w = get_conf_word(d, where + PCI_MSI_DATA_32); | |
628 | t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO); | |
629 | printf("%08x Data: %04x\n", t, w); | |
630 | if (cap & PCI_MSI_FLAGS_MASK_BIT) | |
631 | { | |
632 | u32 mask, pending; | |
633 | ||
634 | if (is64) | |
635 | { | |
636 | if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8)) | |
637 | return; | |
638 | mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64); | |
639 | pending = get_conf_long(d, where + PCI_MSI_PENDING_64); | |
640 | } | |
641 | else | |
642 | { | |
643 | if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8)) | |
644 | return; | |
645 | mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32); | |
646 | pending = get_conf_long(d, where + PCI_MSI_PENDING_32); | |
647 | } | |
648 | printf("\t\tMasking: %08x Pending: %08x\n", mask, pending); | |
649 | } | |
650 | } | |
651 | ||
623ed0e1 BH |
652 | static int exp_downstream_port(int type) |
653 | { | |
654 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
655 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
656 | type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */ | |
657 | } | |
658 | ||
41e49114 | 659 | static void show_power_limit(int value, int scale) |
c7a34993 MM |
660 | { |
661 | static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 }; | |
41e49114 PR |
662 | static const int scale0_values[3] = { 250, 275, 300 }; |
663 | ||
664 | if (scale == 0 && value >= 0xF0) | |
665 | { | |
666 | /* F3h to FFh = Reserved for Slot Power Limit values above 300 W */ | |
667 | if (value >= 0xF3) | |
668 | { | |
669 | printf(">300W"); | |
670 | return; | |
671 | } | |
672 | value = scale0_values[value - 0xF0]; | |
673 | } | |
674 | printf("%gW", value * scales[scale]); | |
c7a34993 MM |
675 | } |
676 | ||
677 | static const char *latency_l0s(int value) | |
678 | { | |
679 | static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" }; | |
680 | return latencies[value]; | |
681 | } | |
682 | ||
683 | static const char *latency_l1(int value) | |
684 | { | |
685 | static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" }; | |
686 | return latencies[value]; | |
687 | } | |
688 | ||
689 | static void cap_express_dev(struct device *d, int where, int type) | |
690 | { | |
691 | u32 t; | |
692 | u16 w; | |
693 | ||
694 | t = get_conf_long(d, where + PCI_EXP_DEVCAP); | |
0dc85d67 | 695 | printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d", |
c7a34993 | 696 | 128 << (t & PCI_EXP_DEVCAP_PAYLOAD), |
0dc85d67 BH |
697 | (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1); |
698 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) | |
699 | printf(", Latency L0s %s, L1 %s", | |
c7a34993 MM |
700 | latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6), |
701 | latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9)); | |
0dc85d67 | 702 | printf("\n"); |
c7a34993 MM |
703 | printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG)); |
704 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || | |
705 | (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) | |
706 | printf(" AttnBtn%c AttnInd%c PwrInd%c", | |
707 | FLAG(t, PCI_EXP_DEVCAP_ATN_BUT), | |
708 | FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND)); | |
5d602ff4 BH |
709 | printf(" RBE%c", |
710 | FLAG(t, PCI_EXP_DEVCAP_RBE)); | |
10168b84 | 711 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) |
5d602ff4 | 712 | printf(" FLReset%c", |
c7a34993 | 713 | FLAG(t, PCI_EXP_DEVCAP_FLRESET)); |
acf56dd2 BH |
714 | if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || |
715 | (type == PCI_EXP_TYPE_PCI_BRIDGE)) | |
41e49114 PR |
716 | { |
717 | printf(" SlotPowerLimit "); | |
718 | show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26); | |
719 | } | |
c7a34993 MM |
720 | printf("\n"); |
721 | ||
722 | w = get_conf_word(d, where + PCI_EXP_DEVCTL); | |
aca48104 | 723 | printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n", |
c7a34993 MM |
724 | FLAG(w, PCI_EXP_DEVCTL_CERE), |
725 | FLAG(w, PCI_EXP_DEVCTL_NFERE), | |
726 | FLAG(w, PCI_EXP_DEVCTL_FERE), | |
727 | FLAG(w, PCI_EXP_DEVCTL_URRE)); | |
728 | printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c", | |
729 | FLAG(w, PCI_EXP_DEVCTL_RELAXED), | |
730 | FLAG(w, PCI_EXP_DEVCTL_EXT_TAG), | |
731 | FLAG(w, PCI_EXP_DEVCTL_PHANTOM), | |
732 | FLAG(w, PCI_EXP_DEVCTL_AUX_PME), | |
733 | FLAG(w, PCI_EXP_DEVCTL_NOSNOOP)); | |
77120d53 | 734 | if (type == PCI_EXP_TYPE_PCI_BRIDGE) |
c7a34993 | 735 | printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE)); |
10168b84 | 736 | if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) && |
5d602ff4 | 737 | (t & PCI_EXP_DEVCAP_FLRESET)) |
c7a34993 MM |
738 | printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET)); |
739 | printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n", | |
740 | 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5), | |
741 | 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12)); | |
742 | ||
743 | w = get_conf_word(d, where + PCI_EXP_DEVSTA); | |
aca48104 | 744 | printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n", |
c7a34993 MM |
745 | FLAG(w, PCI_EXP_DEVSTA_CED), |
746 | FLAG(w, PCI_EXP_DEVSTA_NFED), | |
747 | FLAG(w, PCI_EXP_DEVSTA_FED), | |
748 | FLAG(w, PCI_EXP_DEVSTA_URD), | |
749 | FLAG(w, PCI_EXP_DEVSTA_AUXPD), | |
750 | FLAG(w, PCI_EXP_DEVSTA_TRPND)); | |
751 | } | |
752 | ||
753 | static char *link_speed(int speed) | |
754 | { | |
755 | switch (speed) | |
756 | { | |
757 | case 1: | |
758 | return "2.5GT/s"; | |
759 | case 2: | |
760 | return "5GT/s"; | |
4dc4ff43 MM |
761 | case 3: |
762 | return "8GT/s"; | |
9628600b GS |
763 | case 4: |
764 | return "16GT/s"; | |
caca31a0 GP |
765 | case 5: |
766 | return "32GT/s"; | |
5bdf63b6 GP |
767 | case 6: |
768 | return "64GT/s"; | |
c7a34993 MM |
769 | default: |
770 | return "unknown"; | |
771 | } | |
772 | } | |
773 | ||
9f768120 | 774 | static char *link_compare(int type, int sta, int cap) |
b47b5bd4 | 775 | { |
b47b5bd4 | 776 | if (sta > cap) |
9f768120 MM |
777 | return " (overdriven)"; |
778 | if (sta == cap) | |
779 | return ""; | |
780 | if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) || | |
781 | (type == PCI_EXP_TYPE_PCIE_BRIDGE)) | |
782 | return ""; | |
783 | return " (downgraded)"; | |
b47b5bd4 MM |
784 | } |
785 | ||
c7a34993 MM |
786 | static char *aspm_support(int code) |
787 | { | |
788 | switch (code) | |
789 | { | |
87bc7e64 BH |
790 | case 0: |
791 | return "not supported"; | |
c7a34993 MM |
792 | case 1: |
793 | return "L0s"; | |
4dc4ff43 MM |
794 | case 2: |
795 | return "L1"; | |
c7a34993 MM |
796 | case 3: |
797 | return "L0s L1"; | |
798 | default: | |
799 | return "unknown"; | |
800 | } | |
801 | } | |
802 | ||
803 | static const char *aspm_enabled(int code) | |
804 | { | |
805 | static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" }; | |
806 | return desc[code]; | |
807 | } | |
808 | ||
809 | static void cap_express_link(struct device *d, int where, int type) | |
810 | { | |
b47b5bd4 | 811 | u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width; |
c7a34993 MM |
812 | u16 w; |
813 | ||
814 | t = get_conf_long(d, where + PCI_EXP_LNKCAP); | |
78996f1c | 815 | aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10; |
b47b5bd4 MM |
816 | cap_speed = t & PCI_EXP_LNKCAP_SPEED; |
817 | cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4; | |
78996f1c | 818 | printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s", |
c7a34993 | 819 | t >> 24, |
b47b5bd4 | 820 | link_speed(cap_speed), cap_width, |
78996f1c BH |
821 | aspm_support(aspm)); |
822 | if (aspm) | |
823 | { | |
824 | printf(", Exit Latency "); | |
825 | if (aspm & 1) | |
826 | printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12)); | |
827 | if (aspm & 2) | |
828 | printf("%sL1 %s", (aspm & 1) ? ", " : "", | |
829 | latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); | |
830 | } | |
831 | printf("\n"); | |
b7a807b4 | 832 | printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n", |
c7a34993 MM |
833 | FLAG(t, PCI_EXP_LNKCAP_CLOCKPM), |
834 | FLAG(t, PCI_EXP_LNKCAP_SURPRISE), | |
835 | FLAG(t, PCI_EXP_LNKCAP_DLLA), | |
b7a807b4 MM |
836 | FLAG(t, PCI_EXP_LNKCAP_LBNC), |
837 | FLAG(t, PCI_EXP_LNKCAP_AOC)); | |
c7a34993 MM |
838 | |
839 | w = get_conf_word(d, where + PCI_EXP_LNKCTL); | |
840 | printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM)); | |
841 | if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || | |
a1f57a29 | 842 | (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) |
018f413c | 843 | printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); |
8ad3c8cf | 844 | printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", |
c7a34993 | 845 | FLAG(w, PCI_EXP_LNKCTL_DISABLE), |
c7a34993 MM |
846 | FLAG(w, PCI_EXP_LNKCTL_CLOCK), |
847 | FLAG(w, PCI_EXP_LNKCTL_XSYNCH), | |
848 | FLAG(w, PCI_EXP_LNKCTL_CLOCKPM), | |
849 | FLAG(w, PCI_EXP_LNKCTL_HWAUTWD), | |
850 | FLAG(w, PCI_EXP_LNKCTL_BWMIE), | |
851 | FLAG(w, PCI_EXP_LNKCTL_AUTBWIE)); | |
852 | ||
853 | w = get_conf_word(d, where + PCI_EXP_LNKSTA); | |
b47b5bd4 MM |
854 | sta_speed = w & PCI_EXP_LNKSTA_SPEED; |
855 | sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; | |
9f768120 | 856 | printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n", |
b47b5bd4 | 857 | link_speed(sta_speed), |
9f768120 | 858 | link_compare(type, sta_speed, cap_speed), |
b47b5bd4 | 859 | sta_width, |
9f768120 | 860 | link_compare(type, sta_width, cap_width)); |
b47b5bd4 | 861 | printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", |
c7a34993 MM |
862 | FLAG(w, PCI_EXP_LNKSTA_TR_ERR), |
863 | FLAG(w, PCI_EXP_LNKSTA_TRAIN), | |
864 | FLAG(w, PCI_EXP_LNKSTA_SL_CLK), | |
865 | FLAG(w, PCI_EXP_LNKSTA_DL_ACT), | |
866 | FLAG(w, PCI_EXP_LNKSTA_BWMGMT), | |
867 | FLAG(w, PCI_EXP_LNKSTA_AUTBW)); | |
868 | } | |
869 | ||
870 | static const char *indicator(int code) | |
871 | { | |
872 | static const char *names[] = { "Unknown", "On", "Blink", "Off" }; | |
873 | return names[code]; | |
874 | } | |
875 | ||
876 | static void cap_express_slot(struct device *d, int where) | |
877 | { | |
878 | u32 t; | |
879 | u16 w; | |
880 | ||
881 | t = get_conf_long(d, where + PCI_EXP_SLTCAP); | |
5f6aca18 | 882 | printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n", |
c7a34993 MM |
883 | FLAG(t, PCI_EXP_SLTCAP_ATNB), |
884 | FLAG(t, PCI_EXP_SLTCAP_PWRC), | |
885 | FLAG(t, PCI_EXP_SLTCAP_MRL), | |
886 | FLAG(t, PCI_EXP_SLTCAP_ATNI), | |
887 | FLAG(t, PCI_EXP_SLTCAP_PWRI), | |
888 | FLAG(t, PCI_EXP_SLTCAP_HPC), | |
889 | FLAG(t, PCI_EXP_SLTCAP_HPS)); | |
41e49114 PR |
890 | printf("\t\t\tSlot #%d, PowerLimit ", |
891 | (t & PCI_EXP_SLTCAP_PSN) >> 19); | |
892 | show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15); | |
893 | printf("; Interlock%c NoCompl%c\n", | |
c7a34993 MM |
894 | FLAG(t, PCI_EXP_SLTCAP_INTERLOCK), |
895 | FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP)); | |
896 | ||
897 | w = get_conf_word(d, where + PCI_EXP_SLTCTL); | |
898 | printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n", | |
899 | FLAG(w, PCI_EXP_SLTCTL_ATNB), | |
900 | FLAG(w, PCI_EXP_SLTCTL_PWRF), | |
901 | FLAG(w, PCI_EXP_SLTCTL_MRLS), | |
902 | FLAG(w, PCI_EXP_SLTCTL_PRSD), | |
903 | FLAG(w, PCI_EXP_SLTCTL_CMDC), | |
904 | FLAG(w, PCI_EXP_SLTCTL_HPIE), | |
905 | FLAG(w, PCI_EXP_SLTCTL_LLCHG)); | |
906 | printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n", | |
907 | indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6), | |
908 | indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8), | |
909 | FLAG(w, PCI_EXP_SLTCTL_PWRC), | |
910 | FLAG(w, PCI_EXP_SLTCTL_INTERLOCK)); | |
911 | ||
912 | w = get_conf_word(d, where + PCI_EXP_SLTSTA); | |
913 | printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n", | |
914 | FLAG(w, PCI_EXP_SLTSTA_ATNB), | |
915 | FLAG(w, PCI_EXP_SLTSTA_PWRF), | |
916 | FLAG(w, PCI_EXP_SLTSTA_MRL_ST), | |
917 | FLAG(w, PCI_EXP_SLTSTA_CMDC), | |
918 | FLAG(w, PCI_EXP_SLTSTA_PRES), | |
919 | FLAG(w, PCI_EXP_SLTSTA_INTERLOCK)); | |
920 | printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n", | |
921 | FLAG(w, PCI_EXP_SLTSTA_MRLS), | |
922 | FLAG(w, PCI_EXP_SLTSTA_PRSD), | |
923 | FLAG(w, PCI_EXP_SLTSTA_LLCHG)); | |
924 | } | |
925 | ||
926 | static void cap_express_root(struct device *d, int where) | |
927 | { | |
e6a11bb4 BH |
928 | u32 w; |
929 | ||
930 | w = get_conf_word(d, where + PCI_EXP_RTCAP); | |
931 | printf("\t\tRootCap: CRSVisible%c\n", | |
932 | FLAG(w, PCI_EXP_RTCAP_CRSVIS)); | |
933 | ||
934 | w = get_conf_word(d, where + PCI_EXP_RTCTL); | |
c7a34993 MM |
935 | printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n", |
936 | FLAG(w, PCI_EXP_RTCTL_SECEE), | |
937 | FLAG(w, PCI_EXP_RTCTL_SENFEE), | |
938 | FLAG(w, PCI_EXP_RTCTL_SEFEE), | |
939 | FLAG(w, PCI_EXP_RTCTL_PMEIE), | |
940 | FLAG(w, PCI_EXP_RTCTL_CRSVIS)); | |
941 | ||
23c27798 | 942 | w = get_conf_long(d, where + PCI_EXP_RTSTA); |
c7a34993 MM |
943 | printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n", |
944 | w & PCI_EXP_RTSTA_PME_REQID, | |
945 | FLAG(w, PCI_EXP_RTSTA_PME_STATUS), | |
946 | FLAG(w, PCI_EXP_RTSTA_PME_PENDING)); | |
947 | } | |
948 | ||
949 | static const char *cap_express_dev2_timeout_range(int type) | |
950 | { | |
951 | /* Decode Completion Timeout Ranges. */ | |
952 | switch (type) | |
953 | { | |
954 | case 0: | |
955 | return "Not Supported"; | |
956 | case 1: | |
957 | return "Range A"; | |
958 | case 2: | |
959 | return "Range B"; | |
960 | case 3: | |
961 | return "Range AB"; | |
962 | case 6: | |
963 | return "Range BC"; | |
964 | case 7: | |
965 | return "Range ABC"; | |
966 | case 14: | |
967 | return "Range BCD"; | |
968 | case 15: | |
969 | return "Range ABCD"; | |
970 | default: | |
971 | return "Unknown"; | |
972 | } | |
973 | } | |
974 | ||
975 | static const char *cap_express_dev2_timeout_value(int type) | |
976 | { | |
977 | /* Decode Completion Timeout Value. */ | |
978 | switch (type) | |
979 | { | |
980 | case 0: | |
981 | return "50us to 50ms"; | |
982 | case 1: | |
983 | return "50us to 100us"; | |
984 | case 2: | |
985 | return "1ms to 10ms"; | |
986 | case 5: | |
987 | return "16ms to 55ms"; | |
988 | case 6: | |
989 | return "65ms to 210ms"; | |
990 | case 9: | |
991 | return "260ms to 900ms"; | |
992 | case 10: | |
993 | return "1s to 3.5s"; | |
994 | case 13: | |
995 | return "4s to 13s"; | |
996 | case 14: | |
997 | return "17s to 64s"; | |
998 | default: | |
999 | return "Unknown"; | |
1000 | } | |
1001 | } | |
1002 | ||
d4c91e40 MW |
1003 | static const char *cap_express_devcap2_obff(int obff) |
1004 | { | |
1005 | switch (obff) | |
1006 | { | |
1007 | case 1: | |
1008 | return "Via message"; | |
1009 | case 2: | |
1010 | return "Via WAKE#"; | |
1011 | case 3: | |
1012 | return "Via message/WAKE#"; | |
1013 | default: | |
1014 | return "Not Supported"; | |
1015 | } | |
1016 | } | |
1017 | ||
33226851 FL |
1018 | static const char *cap_express_devcap2_epr(int epr) |
1019 | { | |
1020 | switch (epr) | |
1021 | { | |
1022 | case 1: | |
1023 | return "Dev Specific"; | |
1024 | case 2: | |
1025 | return "Form Factor Dev Specific"; | |
1026 | case 3: | |
1027 | return "Reserved"; | |
1028 | default: | |
1029 | return "Not Supported"; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | static const char *cap_express_devcap2_lncls(int lncls) | |
1034 | { | |
1035 | switch (lncls) | |
1036 | { | |
1037 | case 1: | |
1038 | return "64byte cachelines"; | |
1039 | case 2: | |
1040 | return "128byte cachelines"; | |
1041 | case 3: | |
1042 | return "Reserved"; | |
1043 | default: | |
1044 | return "Not Supported"; | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | static const char *cap_express_devcap2_tphcomp(int tph) | |
1049 | { | |
1050 | switch (tph) | |
1051 | { | |
1052 | case 1: | |
018f413c | 1053 | return "TPHComp+ ExtTPHComp-"; |
33226851 FL |
1054 | case 2: |
1055 | /* Reserved; intentionally left blank */ | |
1056 | return ""; | |
1057 | case 3: | |
018f413c | 1058 | return "TPHComp+ ExtTPHComp+"; |
33226851 | 1059 | default: |
018f413c | 1060 | return "TPHComp- ExtTPHComp-"; |
33226851 FL |
1061 | } |
1062 | } | |
1063 | ||
d4c91e40 MW |
1064 | static const char *cap_express_devctl2_obff(int obff) |
1065 | { | |
1066 | switch (obff) | |
1067 | { | |
1068 | case 0: | |
1069 | return "Disabled"; | |
1070 | case 1: | |
1071 | return "Via message A"; | |
1072 | case 2: | |
1073 | return "Via message B"; | |
1074 | case 3: | |
1075 | return "Via WAKE#"; | |
1076 | default: | |
1077 | return "Unknown"; | |
1078 | } | |
1079 | } | |
1080 | ||
ad431573 SB |
1081 | static int |
1082 | device_has_memory_space_bar(struct device *d) | |
1083 | { | |
1084 | struct pci_dev *p = d->dev; | |
1085 | int i, found = 0; | |
1086 | ||
1087 | for (i=0; i<6; i++) | |
1088 | if (p->base_addr[i] && p->size[i]) | |
1089 | { | |
1090 | if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO)) | |
1091 | { | |
1092 | found = 1; | |
1093 | break; | |
1094 | } | |
1095 | } | |
1096 | return found; | |
1097 | } | |
1098 | ||
c7a34993 MM |
1099 | static void cap_express_dev2(struct device *d, int where, int type) |
1100 | { | |
1101 | u32 l; | |
1102 | u16 w; | |
5371aab4 | 1103 | int has_mem_bar = device_has_memory_space_bar(d); |
c7a34993 MM |
1104 | |
1105 | l = get_conf_long(d, where + PCI_EXP_DEVCAP2); | |
018f413c | 1106 | printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c", |
e79a4207 DL |
1107 | cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)), |
1108 | FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS), | |
33226851 FL |
1109 | FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP), |
1110 | FLAG(l, PCI_EXP_DEVCAP2_LTR)); | |
018f413c | 1111 | printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c", |
33226851 FL |
1112 | FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP), |
1113 | FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ), | |
1114 | cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)), | |
1115 | FLAG(l, PCI_EXP_DEVCAP2_EXTFMT), | |
1116 | FLAG(l, PCI_EXP_DEVCAP2_EE_TLP)); | |
1117 | ||
1118 | if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP)) | |
1119 | { | |
1120 | printf(", MaxEETLPPrefixes %d", | |
1121 | PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4); | |
1122 | } | |
1123 | ||
1124 | printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c", | |
1125 | cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)), | |
1126 | FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT)); | |
1127 | printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS)); | |
1128 | ||
1129 | if (type == PCI_EXP_TYPE_ROOT_PORT) | |
018f413c | 1130 | printf(" LN System CLS %s,", |
33226851 FL |
1131 | cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l))); |
1132 | ||
1133 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT) | |
018f413c | 1134 | printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l))); |
33226851 | 1135 | |
c7a34993 | 1136 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) |
e79a4207 | 1137 | printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI)); |
c7a34993 MM |
1138 | else |
1139 | printf("\n"); | |
ad431573 SB |
1140 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1141 | type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar) | |
1142 | { | |
c4cf2d1c | 1143 | printf("\t\t\t AtomicOpsCap:"); |
ad431573 SB |
1144 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1145 | type == PCI_EXP_TYPE_DOWNSTREAM) | |
1146 | printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING)); | |
1147 | if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar) | |
1148 | printf(" 32bit%c 64bit%c 128bitCAS%c", | |
1149 | FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP), | |
1150 | FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP), | |
1151 | FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP)); | |
1152 | printf("\n"); | |
1153 | } | |
c7a34993 MM |
1154 | |
1155 | w = get_conf_word(d, where + PCI_EXP_DEVCTL2); | |
3afdb452 | 1156 | printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,", |
e79a4207 DL |
1157 | cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)), |
1158 | FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS), | |
1159 | FLAG(w, PCI_EXP_DEVCTL2_LTR), | |
3afdb452 | 1160 | FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ), |
e79a4207 | 1161 | cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w))); |
c7a34993 | 1162 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) |
e79a4207 | 1163 | printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI)); |
c7a34993 MM |
1164 | else |
1165 | printf("\n"); | |
ad431573 SB |
1166 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1167 | type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT || | |
1168 | type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) | |
1169 | { | |
c4cf2d1c | 1170 | printf("\t\t\t AtomicOpsCtl:"); |
ad431573 SB |
1171 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT || |
1172 | type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) | |
e79a4207 | 1173 | printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN)); |
ad431573 SB |
1174 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || |
1175 | type == PCI_EXP_TYPE_DOWNSTREAM) | |
e79a4207 | 1176 | printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK)); |
ad431573 SB |
1177 | printf("\n"); |
1178 | } | |
c7a34993 MM |
1179 | } |
1180 | ||
623ed0e1 BH |
1181 | static const char *cap_express_link2_speed_cap(int vector) |
1182 | { | |
1183 | /* | |
1184 | * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not | |
1185 | * permitted to skip support for any data rates between 2.5GT/s and the | |
1186 | * highest supported rate. | |
1187 | */ | |
1188 | if (vector & 0x60) | |
1189 | return "RsvdP"; | |
1190 | if (vector & 0x10) | |
1191 | return "2.5-32GT/s"; | |
1192 | if (vector & 0x08) | |
1193 | return "2.5-16GT/s"; | |
1194 | if (vector & 0x04) | |
1195 | return "2.5-8GT/s"; | |
1196 | if (vector & 0x02) | |
1197 | return "2.5-5GT/s"; | |
1198 | if (vector & 0x01) | |
1199 | return "2.5GT/s"; | |
1200 | ||
1201 | return "Unknown"; | |
1202 | } | |
1203 | ||
c7a34993 MM |
1204 | static const char *cap_express_link2_speed(int type) |
1205 | { | |
1206 | switch (type) | |
1207 | { | |
1208 | case 0: /* hardwire to 0 means only the 2.5GT/s is supported */ | |
1209 | case 1: | |
1210 | return "2.5GT/s"; | |
1211 | case 2: | |
1212 | return "5GT/s"; | |
4dc4ff43 MM |
1213 | case 3: |
1214 | return "8GT/s"; | |
9628600b GS |
1215 | case 4: |
1216 | return "16GT/s"; | |
caca31a0 GP |
1217 | case 5: |
1218 | return "32GT/s"; | |
5bdf63b6 GP |
1219 | case 6: |
1220 | return "64GT/s"; | |
c7a34993 MM |
1221 | default: |
1222 | return "Unknown"; | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | static const char *cap_express_link2_deemphasis(int type) | |
1227 | { | |
1228 | switch (type) | |
1229 | { | |
1230 | case 0: | |
1231 | return "-6dB"; | |
1232 | case 1: | |
1233 | return "-3.5dB"; | |
1234 | default: | |
1235 | return "Unknown"; | |
1236 | } | |
1237 | } | |
1238 | ||
ad140168 LB |
1239 | static const char *cap_express_link2_compliance_preset(int type) |
1240 | { | |
1241 | switch (type) | |
1242 | { | |
1243 | case 0: | |
1244 | return "-6dB de-emphasis, 0dB preshoot"; | |
1245 | case 1: | |
1246 | return "-3.5dB de-emphasis, 0dB preshoot"; | |
1247 | case 2: | |
1248 | return "-4.4dB de-emphasis, 0dB preshoot"; | |
1249 | case 3: | |
1250 | return "-2.5dB de-emphasis, 0dB preshoot"; | |
1251 | case 4: | |
1252 | return "0dB de-emphasis, 0dB preshoot"; | |
1253 | case 5: | |
1254 | return "0dB de-emphasis, 1.9dB preshoot"; | |
1255 | case 6: | |
1256 | return "0dB de-emphasis, 2.5dB preshoot"; | |
1257 | case 7: | |
1258 | return "-6.0dB de-emphasis, 3.5dB preshoot"; | |
1259 | case 8: | |
1260 | return "-3.5dB de-emphasis, 3.5dB preshoot"; | |
1261 | case 9: | |
1262 | return "0dB de-emphasis, 3.5dB preshoot"; | |
1263 | default: | |
1264 | return "Unknown"; | |
1265 | } | |
1266 | } | |
1267 | ||
c7a34993 MM |
1268 | static const char *cap_express_link2_transmargin(int type) |
1269 | { | |
1270 | switch (type) | |
1271 | { | |
1272 | case 0: | |
1273 | return "Normal Operating Range"; | |
1274 | case 1: | |
1275 | return "800-1200mV(full-swing)/400-700mV(half-swing)"; | |
1276 | case 2: | |
1277 | case 3: | |
1278 | case 4: | |
1279 | case 5: | |
1280 | return "200-400mV(full-swing)/100-200mV(half-swing)"; | |
1281 | default: | |
1282 | return "Unknown"; | |
1283 | } | |
1284 | } | |
1285 | ||
623ed0e1 BH |
1286 | static const char *cap_express_link2_crosslink_res(int crosslink) |
1287 | { | |
1288 | switch (crosslink) | |
1289 | { | |
1290 | case 0: | |
1291 | return "unsupported"; | |
1292 | case 1: | |
1293 | return "Upstream Port"; | |
1294 | case 2: | |
1295 | return "Downstream Port"; | |
1296 | default: | |
1297 | return "incomplete"; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | static const char *cap_express_link2_component(int presence) | |
1302 | { | |
1303 | switch (presence) | |
1304 | { | |
1305 | case 0: | |
1306 | return "Link Down - Not Determined"; | |
1307 | case 1: | |
1308 | return "Link Down - Not Present"; | |
1309 | case 2: | |
1310 | return "Link Down - Present"; | |
1311 | case 4: | |
1312 | return "Link Up - Present"; | |
1313 | case 5: | |
1314 | return "Link Up - Present and DRS Received"; | |
1315 | default: | |
1316 | return "Reserved"; | |
1317 | } | |
1318 | } | |
1319 | ||
37f8039d | 1320 | static void cap_express_link2(struct device *d, int where, int type) |
c7a34993 | 1321 | { |
623ed0e1 | 1322 | u32 l = 0; |
c7a34993 MM |
1323 | u16 w; |
1324 | ||
37f8039d BH |
1325 | if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) && |
1326 | (d->dev->dev != 0 || d->dev->func != 0))) { | |
623ed0e1 BH |
1327 | /* Link Capabilities 2 was reserved before PCIe r3.0 */ |
1328 | l = get_conf_long(d, where + PCI_EXP_LNKCAP2); | |
1329 | if (l) { | |
1330 | printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c " | |
1331 | "Retimer%c 2Retimers%c DRS%c\n", | |
1332 | cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)), | |
1333 | FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK), | |
1334 | FLAG(l, PCI_EXP_LNKCAP2_RETIMER), | |
1335 | FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS), | |
1336 | FLAG(l, PCI_EXP_LNKCAP2_DRS)); | |
1337 | } | |
1338 | ||
37f8039d BH |
1339 | w = get_conf_word(d, where + PCI_EXP_LNKCTL2); |
1340 | printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c", | |
c7a34993 MM |
1341 | cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)), |
1342 | FLAG(w, PCI_EXP_LNKCTL2_CMPLNC), | |
37f8039d BH |
1343 | FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS)); |
1344 | if (type == PCI_EXP_TYPE_DOWNSTREAM) | |
1345 | printf(", Selectable De-emphasis: %s", | |
1346 | cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w))); | |
1347 | printf("\n" | |
1348 | "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n" | |
ad140168 | 1349 | "\t\t\t Compliance Preset/De-emphasis: %s\n", |
c7a34993 MM |
1350 | cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)), |
1351 | FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC), | |
1352 | FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS), | |
ad140168 | 1353 | cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w))); |
37f8039d | 1354 | } |
c7a34993 MM |
1355 | |
1356 | w = get_conf_word(d, where + PCI_EXP_LNKSTA2); | |
018f413c BH |
1357 | printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n" |
1358 | "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n" | |
623ed0e1 | 1359 | "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s", |
4dc4ff43 MM |
1360 | cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)), |
1361 | FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP), | |
1362 | FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1), | |
1363 | FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2), | |
1364 | FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3), | |
623ed0e1 BH |
1365 | FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ), |
1366 | FLAG(w, PCI_EXP_LINKSTA2_RETIMER), | |
1367 | FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS), | |
1368 | cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w))); | |
1369 | ||
1370 | if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) { | |
1371 | printf(", DRS%c\n" | |
1372 | "\t\t\t DownstreamComp: %s\n", | |
1373 | FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD), | |
1374 | cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w))); | |
1375 | } else | |
1376 | printf("\n"); | |
c7a34993 MM |
1377 | } |
1378 | ||
1379 | static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) | |
1380 | { | |
1381 | /* No capabilities that require this field in PCIe rev2.0 spec. */ | |
1382 | } | |
1383 | ||
a1492b88 | 1384 | static int |
c7a34993 MM |
1385 | cap_express(struct device *d, int where, int cap) |
1386 | { | |
1387 | int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4; | |
1388 | int size; | |
1389 | int slot = 0; | |
17ebd1d1 | 1390 | int link = 1; |
c7a34993 MM |
1391 | |
1392 | printf("Express "); | |
1393 | if (verbose >= 2) | |
1394 | printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS); | |
1395 | switch (type) | |
1396 | { | |
1397 | case PCI_EXP_TYPE_ENDPOINT: | |
1398 | printf("Endpoint"); | |
1399 | break; | |
1400 | case PCI_EXP_TYPE_LEG_END: | |
1401 | printf("Legacy Endpoint"); | |
1402 | break; | |
1403 | case PCI_EXP_TYPE_ROOT_PORT: | |
1404 | slot = cap & PCI_EXP_FLAGS_SLOT; | |
1405 | printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); | |
1406 | break; | |
1407 | case PCI_EXP_TYPE_UPSTREAM: | |
1408 | printf("Upstream Port"); | |
1409 | break; | |
1410 | case PCI_EXP_TYPE_DOWNSTREAM: | |
1411 | slot = cap & PCI_EXP_FLAGS_SLOT; | |
1412 | printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); | |
1413 | break; | |
1414 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
77120d53 | 1415 | printf("PCI-Express to PCI/PCI-X Bridge"); |
c7a34993 MM |
1416 | break; |
1417 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
f41bb847 BH |
1418 | slot = cap & PCI_EXP_FLAGS_SLOT; |
1419 | printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)", | |
1420 | FLAG(cap, PCI_EXP_FLAGS_SLOT)); | |
c7a34993 MM |
1421 | break; |
1422 | case PCI_EXP_TYPE_ROOT_INT_EP: | |
17ebd1d1 | 1423 | link = 0; |
c7a34993 MM |
1424 | printf("Root Complex Integrated Endpoint"); |
1425 | break; | |
1426 | case PCI_EXP_TYPE_ROOT_EC: | |
17ebd1d1 | 1427 | link = 0; |
c7a34993 MM |
1428 | printf("Root Complex Event Collector"); |
1429 | break; | |
1430 | default: | |
1431 | printf("Unknown type %d", type); | |
1432 | } | |
1433 | printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); | |
1434 | if (verbose < 2) | |
a1492b88 | 1435 | return type; |
c7a34993 MM |
1436 | |
1437 | size = 16; | |
1438 | if (slot) | |
1439 | size = 24; | |
7155d510 | 1440 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) |
c7a34993 MM |
1441 | size = 32; |
1442 | if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) | |
a1492b88 | 1443 | return type; |
c7a34993 MM |
1444 | |
1445 | cap_express_dev(d, where, type); | |
17ebd1d1 BH |
1446 | if (link) |
1447 | cap_express_link(d, where, type); | |
c7a34993 MM |
1448 | if (slot) |
1449 | cap_express_slot(d, where); | |
7155d510 | 1450 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) |
c7a34993 MM |
1451 | cap_express_root(d, where); |
1452 | ||
1453 | if ((cap & PCI_EXP_FLAGS_VERS) < 2) | |
a1492b88 | 1454 | return type; |
c7a34993 MM |
1455 | |
1456 | size = 16; | |
1457 | if (slot) | |
1458 | size = 24; | |
1459 | if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size)) | |
a1492b88 | 1460 | return type; |
c7a34993 MM |
1461 | |
1462 | cap_express_dev2(d, where, type); | |
17ebd1d1 BH |
1463 | if (link) |
1464 | cap_express_link2(d, where, type); | |
c7a34993 MM |
1465 | if (slot) |
1466 | cap_express_slot2(d, where); | |
a1492b88 | 1467 | return type; |
c7a34993 MM |
1468 | } |
1469 | ||
1470 | static void | |
1471 | cap_msix(struct device *d, int where, int cap) | |
1472 | { | |
1473 | u32 off; | |
1474 | ||
04885ef7 | 1475 | printf("MSI-X: Enable%c Count=%d Masked%c\n", |
c7a34993 | 1476 | FLAG(cap, PCI_MSIX_ENABLE), |
04885ef7 MW |
1477 | (cap & PCI_MSIX_TABSIZE) + 1, |
1478 | FLAG(cap, PCI_MSIX_MASK)); | |
c7a34993 MM |
1479 | if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8)) |
1480 | return; | |
1481 | ||
1482 | off = get_conf_long(d, where + PCI_MSIX_TABLE); | |
1483 | printf("\t\tVector table: BAR=%d offset=%08x\n", | |
1484 | off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR); | |
1485 | off = get_conf_long(d, where + PCI_MSIX_PBA); | |
1486 | printf("\t\tPBA: BAR=%d offset=%08x\n", | |
1487 | off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR); | |
1488 | } | |
1489 | ||
1490 | static void | |
1491 | cap_slotid(int cap) | |
1492 | { | |
1493 | int esr = cap & 0xff; | |
1494 | int chs = cap >> 8; | |
1495 | ||
1496 | printf("Slot ID: %d slots, First%c, chassis %02x\n", | |
1497 | esr & PCI_SID_ESR_NSLOTS, | |
1498 | FLAG(esr, PCI_SID_ESR_FIC), | |
1499 | chs); | |
1500 | } | |
1501 | ||
1502 | static void | |
1503 | cap_ssvid(struct device *d, int where) | |
1504 | { | |
1505 | u16 subsys_v, subsys_d; | |
1506 | char ssnamebuf[256]; | |
1507 | ||
1508 | if (!config_fetch(d, where, 8)) | |
1509 | return; | |
1510 | subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR); | |
1511 | subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE); | |
1512 | printf("Subsystem: %s\n", | |
1513 | pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf), | |
1514 | PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE, | |
1515 | d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d)); | |
1516 | } | |
1517 | ||
1518 | static void | |
1519 | cap_debug_port(int cap) | |
1520 | { | |
1521 | int bar = cap >> 13; | |
1522 | int pos = cap & 0x1fff; | |
1523 | printf("Debug port: BAR=%d offset=%04x\n", bar, pos); | |
1524 | } | |
1525 | ||
99eb76e5 YZ |
1526 | static void |
1527 | cap_af(struct device *d, int where) | |
1528 | { | |
1529 | u8 reg; | |
1530 | ||
1531 | printf("PCI Advanced Features\n"); | |
1532 | if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3)) | |
1533 | return; | |
1534 | ||
1535 | reg = get_conf_byte(d, where + PCI_AF_CAP); | |
1536 | printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP), | |
1537 | FLAG(reg, PCI_AF_CAP_FLR)); | |
1538 | reg = get_conf_byte(d, where + PCI_AF_CTRL); | |
1539 | printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR)); | |
1540 | reg = get_conf_byte(d, where + PCI_AF_STATUS); | |
1541 | printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP)); | |
1542 | } | |
1543 | ||
be9c1b75 MM |
1544 | static void |
1545 | cap_sata_hba(struct device *d, int where, int cap) | |
1546 | { | |
1547 | u32 bars; | |
1548 | int bar; | |
1549 | ||
1550 | printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4)); | |
1551 | if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4)) | |
1552 | { | |
1553 | printf("\n"); | |
1554 | return; | |
1555 | } | |
1556 | ||
1557 | bars = get_conf_long(d, where + PCI_SATA_HBA_BARS); | |
1558 | bar = BITS(bars, 0, 4); | |
1559 | if (bar >= 4 && bar <= 9) | |
1560 | printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20)); | |
1561 | else if (bar == 15) | |
1562 | printf(" InCfgSpace\n"); | |
1563 | else | |
1564 | printf(" BAR??%d\n", bar); | |
1565 | } | |
1566 | ||
4cd841df DD |
1567 | static const char *cap_ea_property(int p, int is_secondary) |
1568 | { | |
1569 | switch (p) { | |
1570 | case 0x00: | |
1571 | return "memory space, non-prefetchable"; | |
1572 | case 0x01: | |
1573 | return "memory space, prefetchable"; | |
1574 | case 0x02: | |
1575 | return "I/O space"; | |
1576 | case 0x03: | |
1577 | return "VF memory space, prefetchable"; | |
1578 | case 0x04: | |
1579 | return "VF memory space, non-prefetchable"; | |
1580 | case 0x05: | |
1581 | return "allocation behind bridge, non-prefetchable memory"; | |
1582 | case 0x06: | |
1583 | return "allocation behind bridge, prefetchable memory"; | |
1584 | case 0x07: | |
1585 | return "allocation behind bridge, I/O space"; | |
1586 | case 0xfd: | |
1587 | return "memory space resource unavailable for use"; | |
1588 | case 0xfe: | |
1589 | return "I/O space resource unavailable for use"; | |
1590 | case 0xff: | |
1591 | if (is_secondary) | |
1592 | return "entry unavailable for use, PrimaryProperties should be used"; | |
1593 | else | |
1594 | return "entry unavailable for use"; | |
1595 | default: | |
1596 | return NULL; | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | static void cap_ea(struct device *d, int where, int cap) | |
1601 | { | |
1602 | int entry; | |
1603 | int entry_base = where + 4; | |
1604 | int num_entries = BITS(cap, 0, 6); | |
1605 | u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f; | |
1606 | ||
1607 | printf("Enhanced Allocation (EA): NumEntries=%u", num_entries); | |
1608 | if (htype == PCI_HEADER_TYPE_BRIDGE) { | |
1609 | byte fixed_sub, fixed_sec; | |
1610 | ||
1611 | entry_base += 4; | |
1612 | if (!config_fetch(d, where + 4, 2)) { | |
1613 | printf("\n"); | |
1614 | return; | |
1615 | } | |
1616 | fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY); | |
1617 | fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE); | |
1618 | printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub); | |
1619 | } | |
1620 | printf("\n"); | |
1621 | if (verbose < 2) | |
1622 | return; | |
1623 | ||
1624 | for (entry = 0; entry < num_entries; entry++) { | |
1625 | int max_offset_high_pos, has_base_high, has_max_offset_high; | |
1626 | u32 entry_header; | |
1627 | u32 base, max_offset; | |
1628 | int es, bei, pp, sp; | |
1629 | const char *prop_text; | |
1630 | ||
1631 | if (!config_fetch(d, entry_base, 4)) | |
1632 | return; | |
1633 | entry_header = get_conf_long(d, entry_base); | |
1634 | es = BITS(entry_header, 0, 3); | |
1635 | bei = BITS(entry_header, 4, 4); | |
1636 | pp = BITS(entry_header, 8, 8); | |
1637 | sp = BITS(entry_header, 16, 8); | |
1638 | if (!config_fetch(d, entry_base + 4, es * 4)) | |
1639 | return; | |
1640 | printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry, | |
1641 | FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE), | |
1642 | FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es); | |
1643 | printf("\t\t\t BAR Equivalent Indicator: "); | |
1644 | switch (bei) { | |
1645 | case 0: | |
1646 | case 1: | |
1647 | case 2: | |
1648 | case 3: | |
1649 | case 4: | |
1650 | case 5: | |
1651 | printf("BAR %u", bei); | |
1652 | break; | |
1653 | case 6: | |
1654 | printf("resource behind function"); | |
1655 | break; | |
1656 | case 7: | |
1657 | printf("not indicated"); | |
1658 | break; | |
1659 | case 8: | |
1660 | printf("expansion ROM"); | |
1661 | break; | |
1662 | case 9: | |
1663 | case 10: | |
1664 | case 11: | |
1665 | case 12: | |
1666 | case 13: | |
1667 | case 14: | |
1668 | printf("VF-BAR %u", bei - 9); | |
1669 | break; | |
1670 | default: | |
1671 | printf("reserved"); | |
1672 | break; | |
1673 | } | |
1674 | printf("\n"); | |
1675 | ||
1676 | prop_text = cap_ea_property(pp, 0); | |
1677 | printf("\t\t\t PrimaryProperties: "); | |
1678 | if (prop_text) | |
1679 | printf("%s\n", prop_text); | |
1680 | else | |
1681 | printf("[%02x]\n", pp); | |
1682 | ||
1683 | prop_text = cap_ea_property(sp, 1); | |
1684 | printf("\t\t\t SecondaryProperties: "); | |
1685 | if (prop_text) | |
1686 | printf("%s\n", prop_text); | |
1687 | else | |
1688 | printf("[%02x]\n", sp); | |
1689 | ||
1690 | base = get_conf_long(d, entry_base + 4); | |
1691 | has_base_high = ((base & 2) != 0); | |
1692 | base &= ~3; | |
1693 | ||
1694 | max_offset = get_conf_long(d, entry_base + 8); | |
1695 | has_max_offset_high = ((max_offset & 2) != 0); | |
1696 | max_offset |= 3; | |
1697 | max_offset_high_pos = entry_base + 12; | |
1698 | ||
1699 | printf("\t\t\t Base: "); | |
1700 | if (has_base_high) { | |
1701 | u32 base_high = get_conf_long(d, entry_base + 12); | |
1702 | ||
1703 | printf("%x", base_high); | |
1704 | max_offset_high_pos += 4; | |
1705 | } | |
1706 | printf("%08x\n", base); | |
1707 | ||
1708 | printf("\t\t\t MaxOffset: "); | |
1709 | if (has_max_offset_high) { | |
1710 | u32 max_offset_high = get_conf_long(d, max_offset_high_pos); | |
1711 | ||
1712 | printf("%x", max_offset_high); | |
1713 | } | |
1714 | printf("%08x\n", max_offset); | |
1715 | ||
1716 | entry_base += 4 + 4 * es; | |
1717 | } | |
1718 | } | |
1719 | ||
c7a34993 | 1720 | void |
21510591 | 1721 | show_caps(struct device *d, int where) |
c7a34993 MM |
1722 | { |
1723 | int can_have_ext_caps = 0; | |
a1492b88 | 1724 | int type = -1; |
c7a34993 MM |
1725 | |
1726 | if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) | |
1727 | { | |
c7a34993 | 1728 | byte been_there[256]; |
01de4db1 | 1729 | where = get_conf_byte(d, where) & ~3; |
c7a34993 MM |
1730 | memset(been_there, 0, 256); |
1731 | while (where) | |
1732 | { | |
1733 | int id, next, cap; | |
1734 | printf("\tCapabilities: "); | |
1735 | if (!config_fetch(d, where, 4)) | |
1736 | { | |
1737 | puts("<access denied>"); | |
1738 | break; | |
1739 | } | |
1740 | id = get_conf_byte(d, where + PCI_CAP_LIST_ID); | |
1741 | next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3; | |
1742 | cap = get_conf_word(d, where + PCI_CAP_FLAGS); | |
1743 | printf("[%02x] ", where); | |
1744 | if (been_there[where]++) | |
1745 | { | |
1746 | printf("<chain looped>\n"); | |
1747 | break; | |
1748 | } | |
1749 | if (id == 0xff) | |
1750 | { | |
1751 | printf("<chain broken>\n"); | |
1752 | break; | |
1753 | } | |
1754 | switch (id) | |
1755 | { | |
c508d1c9 BH |
1756 | case PCI_CAP_ID_NULL: |
1757 | printf("Null\n"); | |
1758 | break; | |
c7a34993 MM |
1759 | case PCI_CAP_ID_PM: |
1760 | cap_pm(d, where, cap); | |
1761 | break; | |
1762 | case PCI_CAP_ID_AGP: | |
1763 | cap_agp(d, where, cap); | |
1764 | break; | |
1765 | case PCI_CAP_ID_VPD: | |
1766 | cap_vpd(d); | |
1767 | break; | |
1768 | case PCI_CAP_ID_SLOTID: | |
1769 | cap_slotid(cap); | |
1770 | break; | |
1771 | case PCI_CAP_ID_MSI: | |
1772 | cap_msi(d, where, cap); | |
1773 | break; | |
1774 | case PCI_CAP_ID_CHSWP: | |
1775 | printf("CompactPCI hot-swap <?>\n"); | |
1776 | break; | |
1777 | case PCI_CAP_ID_PCIX: | |
1778 | cap_pcix(d, where); | |
1779 | can_have_ext_caps = 1; | |
1780 | break; | |
1781 | case PCI_CAP_ID_HT: | |
1782 | cap_ht(d, where, cap); | |
1783 | break; | |
1784 | case PCI_CAP_ID_VNDR: | |
7ff8a323 | 1785 | show_vendor_caps(d, where, cap); |
c7a34993 MM |
1786 | break; |
1787 | case PCI_CAP_ID_DBG: | |
1788 | cap_debug_port(cap); | |
1789 | break; | |
1790 | case PCI_CAP_ID_CCRC: | |
1791 | printf("CompactPCI central resource control <?>\n"); | |
1792 | break; | |
1793 | case PCI_CAP_ID_HOTPLUG: | |
1794 | printf("Hot-plug capable\n"); | |
1795 | break; | |
1796 | case PCI_CAP_ID_SSVID: | |
1797 | cap_ssvid(d, where); | |
1798 | break; | |
1799 | case PCI_CAP_ID_AGP3: | |
1800 | printf("AGP3 <?>\n"); | |
1801 | break; | |
1802 | case PCI_CAP_ID_SECURE: | |
1803 | printf("Secure device <?>\n"); | |
1804 | break; | |
1805 | case PCI_CAP_ID_EXP: | |
a1492b88 | 1806 | type = cap_express(d, where, cap); |
c7a34993 MM |
1807 | can_have_ext_caps = 1; |
1808 | break; | |
1809 | case PCI_CAP_ID_MSIX: | |
1810 | cap_msix(d, where, cap); | |
1811 | break; | |
1812 | case PCI_CAP_ID_SATA: | |
be9c1b75 | 1813 | cap_sata_hba(d, where, cap); |
c7a34993 MM |
1814 | break; |
1815 | case PCI_CAP_ID_AF: | |
99eb76e5 | 1816 | cap_af(d, where); |
c7a34993 | 1817 | break; |
4cd841df DD |
1818 | case PCI_CAP_ID_EA: |
1819 | cap_ea(d, where, cap); | |
1820 | break; | |
c7a34993 | 1821 | default: |
60a45a7e | 1822 | printf("Capability ID %#02x [%04x]\n", id, cap); |
c7a34993 MM |
1823 | } |
1824 | where = next; | |
1825 | } | |
1826 | } | |
1827 | if (can_have_ext_caps) | |
a1492b88 | 1828 | show_ext_caps(d, type); |
c7a34993 | 1829 | } |