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tests/tcg/aarch64: Add newline in pauth-1 printf
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CommitLineData
093bc2cd
AK
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879 18#include "cpu.h"
022c62cb
PB
19#include "exec/memory.h"
20#include "exec/address-spaces.h"
409ddd01 21#include "qapi/visitor.h"
1de7afc9 22#include "qemu/bitops.h"
8c56c1a5 23#include "qemu/error-report.h"
db725815 24#include "qemu/main-loop.h"
b6b71cb5 25#include "qemu/qemu-print.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
54d31236 32#include "sysemu/runstate.h"
14a48c1d 33#include "sysemu/tcg.h"
8072aae3 34#include "sysemu/accel.h"
8072aae3 35#include "hw/boards.h"
b08199c6 36#include "migration/vmstate.h"
67d95c15 37
d197063f
PB
38//#define DEBUG_UNASSIGNED
39
22bde714
JK
40static unsigned memory_region_transaction_depth;
41static bool memory_region_update_pending;
4dc56152 42static bool ioeventfd_update_pending;
ae7a2bca 43bool global_dirty_log;
7664e80c 44
eae3eb3e 45static QTAILQ_HEAD(, MemoryListener) memory_listeners
72e22d2f 46 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 47
0d673e36
AK
48static QTAILQ_HEAD(, AddressSpace) address_spaces
49 = QTAILQ_HEAD_INITIALIZER(address_spaces);
50
967dc9b1
AK
51static GHashTable *flat_views;
52
093bc2cd
AK
53typedef struct AddrRange AddrRange;
54
8417cebf 55/*
c9cdaa3a 56 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK
57 * (large MemoryRegion::alias_offset).
58 */
093bc2cd 59struct AddrRange {
08dafab4
AK
60 Int128 start;
61 Int128 size;
093bc2cd
AK
62};
63
08dafab4 64static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK
65{
66 return (AddrRange) { start, size };
67}
68
69static bool addrrange_equal(AddrRange r1, AddrRange r2)
70{
08dafab4 71 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK
72}
73
08dafab4 74static Int128 addrrange_end(AddrRange r)
093bc2cd 75{
08dafab4 76 return int128_add(r.start, r.size);
093bc2cd
AK
77}
78
08dafab4 79static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 80{
08dafab4 81 int128_addto(&range.start, delta);
093bc2cd
AK
82 return range;
83}
84
08dafab4
AK
85static bool addrrange_contains(AddrRange range, Int128 addr)
86{
87 return int128_ge(addr, range.start)
88 && int128_lt(addr, addrrange_end(range));
89}
90
093bc2cd
AK
91static bool addrrange_intersects(AddrRange r1, AddrRange r2)
92{
08dafab4
AK
93 return addrrange_contains(r1, r2.start)
94 || addrrange_contains(r2, r1.start);
093bc2cd
AK
95}
96
97static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
98{
08dafab4
AK
99 Int128 start = int128_max(r1.start, r2.start);
100 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
101 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK
102}
103
0e0d36b4
AK
104enum ListenerDirection { Forward, Reverse };
105
7376e582 106#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
107 do { \
108 MemoryListener *_listener; \
109 \
110 switch (_direction) { \
111 case Forward: \
112 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
113 if (_listener->_callback) { \
114 _listener->_callback(_listener, ##_args); \
115 } \
0e0d36b4
AK
116 } \
117 break; \
118 case Reverse: \
eae3eb3e 119 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
975aefe0
AK
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
0e0d36b4
AK
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK
131 do { \
132 MemoryListener *_listener; \
133 \
134 switch (_direction) { \
135 case Forward: \
eae3eb3e 136 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
9a54635d 137 if (_listener->_callback) { \
7376e582
AK
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
eae3eb3e 143 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
9a54635d 144 if (_listener->_callback) { \
7376e582
AK
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
16620684
AK
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
093bc2cd
AK
162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
3e9d69e7
AK
167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
AK
172};
173
73bb753d
TB
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
3e9d69e7 176{
73bb753d 177 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 178 return true;
73bb753d 179 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 180 return false;
73bb753d 181 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 182 return true;
73bb753d 183 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 184 return false;
73bb753d 185 } else if (a->match_data < b->match_data) {
3e9d69e7 186 return true;
73bb753d 187 } else if (a->match_data > b->match_data) {
3e9d69e7 188 return false;
73bb753d
TB
189 } else if (a->match_data) {
190 if (a->data < b->data) {
3e9d69e7 191 return true;
73bb753d 192 } else if (a->data > b->data) {
3e9d69e7
AK
193 return false;
194 }
195 }
73bb753d 196 if (a->e < b->e) {
3e9d69e7 197 return true;
73bb753d 198 } else if (a->e > b->e) {
3e9d69e7
AK
199 return false;
200 }
201 return false;
202}
203
73bb753d
TB
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
3e9d69e7
AK
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd
AK
211/* Range of memory in the global map. Addresses are absolute. */
212struct FlatRange {
213 MemoryRegion *mr;
a8170e5e 214 hwaddr offset_in_region;
093bc2cd 215 AddrRange addr;
5a583347 216 uint8_t dirty_log_mask;
b138e654 217 bool romd_mode;
fb1cd6f9 218 bool readonly;
c26763f8 219 bool nonvolatile;
093bc2cd
AK
220};
221
093bc2cd
AK
222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
9c1f8f44 225static inline MemoryRegionSection
16620684 226section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
16620684 230 .fv = fv,
9c1f8f44
PB
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
c26763f8 235 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB
236 };
237}
238
093bc2cd
AK
239static bool flatrange_equal(FlatRange *a, FlatRange *b)
240{
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 243 && a->offset_in_region == b->offset_in_region
b138e654 244 && a->romd_mode == b->romd_mode
c26763f8
MAL
245 && a->readonly == b->readonly
246 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK
247}
248
89c177bb 249static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 250{
cc94cd6d
AK
251 FlatView *view;
252
253 view = g_new0(FlatView, 1);
856d7245 254 view->ref = 1;
89c177bb
AK
255 view->root = mr_root;
256 memory_region_ref(mr_root);
02d9651d 257 trace_flatview_new(view, mr_root);
cc94cd6d
AK
258
259 return view;
093bc2cd
AK
260}
261
262/* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266{
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 269 view->ranges = g_realloc(view->ranges,
093bc2cd
AK
270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
dfde4e6e 275 memory_region_ref(range->mr);
093bc2cd
AK
276 ++view->nr;
277}
278
279static void flatview_destroy(FlatView *view)
280{
dfde4e6e
PB
281 int i;
282
02d9651d 283 trace_flatview_destroy(view, view->root);
66a6df1d
AK
284 if (view->dispatch) {
285 address_space_dispatch_free(view->dispatch);
286 }
dfde4e6e
PB
287 for (i = 0; i < view->nr; i++) {
288 memory_region_unref(view->ranges[i].mr);
289 }
7267c094 290 g_free(view->ranges);
89c177bb 291 memory_region_unref(view->root);
a9a0c06d 292 g_free(view);
093bc2cd
AK
293}
294
447b0d0b 295static bool flatview_ref(FlatView *view)
856d7245 296{
447b0d0b 297 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
298}
299
48564041 300void flatview_unref(FlatView *view)
856d7245
PB
301{
302 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 303 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 304 assert(view->root);
66a6df1d 305 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
306 }
307}
308
3d8e6bf9
AK
309static bool can_merge(FlatRange *r1, FlatRange *r2)
310{
08dafab4 311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 312 && r1->mr == r2->mr
08dafab4
AK
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
d0a9b5bc 316 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 317 && r1->romd_mode == r2->romd_mode
c26763f8
MAL
318 && r1->readonly == r2->readonly
319 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK
320}
321
8508e024 322/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
323static void flatview_simplify(FlatView *view)
324{
838ec117 325 unsigned i, j, k;
3d8e6bf9
AK
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
333 ++j;
334 }
335 ++i;
838ec117
KW
336 for (k = i; k < j; k++) {
337 memory_region_unref(view->ranges[k].mr);
338 }
3d8e6bf9
AK
339 memmove(&view->ranges[i], &view->ranges[j],
340 (view->nr - j) * sizeof(view->ranges[j]));
341 view->nr -= j - i;
342 }
343}
344
e7342aa3
PB
345static bool memory_region_big_endian(MemoryRegion *mr)
346{
347#ifdef TARGET_WORDS_BIGENDIAN
348 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
349#else
350 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
351#endif
352}
353
9bf825bf 354static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
e11ef3d1 355{
9bf825bf
TN
356 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
357 switch (op & MO_SIZE) {
358 case MO_8:
e11ef3d1 359 break;
9bf825bf 360 case MO_16:
e11ef3d1
PB
361 *data = bswap16(*data);
362 break;
9bf825bf 363 case MO_32:
e11ef3d1
PB
364 *data = bswap32(*data);
365 break;
9bf825bf 366 case MO_64:
e11ef3d1
PB
367 *data = bswap64(*data);
368 break;
369 default:
9bf825bf 370 g_assert_not_reached();
e11ef3d1
PB
371 }
372 }
373}
374
3c754a93 375static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 376 signed shift,
3c754a93
PMD
377 uint64_t mask,
378 uint64_t tmp)
379{
98f52cdb
PMD
380 if (shift >= 0) {
381 *value |= (tmp & mask) << shift;
382 } else {
383 *value |= (tmp & mask) >> -shift;
384 }
3c754a93
PMD
385}
386
387static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 388 signed shift,
3c754a93
PMD
389 uint64_t mask)
390{
98f52cdb
PMD
391 uint64_t tmp;
392
393 if (shift >= 0) {
394 tmp = (*value >> shift) & mask;
395 } else {
396 tmp = (*value << -shift) & mask;
397 }
398
399 return tmp;
3c754a93
PMD
400}
401
4779dc1d
HB
402static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
403{
404 MemoryRegion *root;
405 hwaddr abs_addr = offset;
406
407 abs_addr += mr->addr;
408 for (root = mr; root->container; ) {
409 root = root->container;
410 abs_addr += root->addr;
411 }
412
413 return abs_addr;
414}
415
5a68be94
HB
416static int get_cpu_index(void)
417{
418 if (current_cpu) {
419 return current_cpu->cpu_index;
420 }
421 return -1;
422}
423
cc05c43a 424static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
425 hwaddr addr,
426 uint64_t *value,
427 unsigned size,
98f52cdb 428 signed shift,
cc05c43a
PM
429 uint64_t mask,
430 MemTxAttrs attrs)
ce5d2f33 431{
ce5d2f33
PB
432 uint64_t tmp;
433
cc05c43a 434 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 435 if (mr->subpage) {
5a68be94 436 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 437 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 438 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 439 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 440 }
3c754a93 441 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 442 return MEMTX_OK;
ce5d2f33
PB
443}
444
cc05c43a
PM
445static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
446 hwaddr addr,
447 uint64_t *value,
448 unsigned size,
98f52cdb 449 signed shift,
cc05c43a
PM
450 uint64_t mask,
451 MemTxAttrs attrs)
164a4dcd 452{
cc05c43a
PM
453 uint64_t tmp = 0;
454 MemTxResult r;
164a4dcd 455
cc05c43a 456 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 457 if (mr->subpage) {
5a68be94 458 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 459 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 460 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 461 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 462 }
3c754a93 463 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 464 return r;
164a4dcd
AK
465}
466
cc05c43a
PM
467static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
468 hwaddr addr,
469 uint64_t *value,
470 unsigned size,
98f52cdb 471 signed shift,
cc05c43a
PM
472 uint64_t mask,
473 MemTxAttrs attrs)
164a4dcd 474{
3c754a93 475 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 476
23d92d68 477 if (mr->subpage) {
5a68be94 478 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 479 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 480 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 481 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 482 }
164a4dcd 483 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 484 return MEMTX_OK;
164a4dcd
AK
485}
486
cc05c43a
PM
487static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
488 hwaddr addr,
489 uint64_t *value,
490 unsigned size,
98f52cdb 491 signed shift,
cc05c43a
PM
492 uint64_t mask,
493 MemTxAttrs attrs)
494{
3c754a93 495 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 496
23d92d68 497 if (mr->subpage) {
5a68be94 498 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 499 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 500 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 501 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 502 }
cc05c43a
PM
503 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
504}
505
506static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
507 uint64_t *value,
508 unsigned size,
509 unsigned access_size_min,
510 unsigned access_size_max,
05e015f7
KF
511 MemTxResult (*access_fn)
512 (MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
98f52cdb 516 signed shift,
05e015f7
KF
517 uint64_t mask,
518 MemTxAttrs attrs),
cc05c43a
PM
519 MemoryRegion *mr,
520 MemTxAttrs attrs)
164a4dcd
AK
521{
522 uint64_t access_mask;
523 unsigned access_size;
524 unsigned i;
cc05c43a 525 MemTxResult r = MEMTX_OK;
164a4dcd
AK
526
527 if (!access_size_min) {
528 access_size_min = 1;
529 }
530 if (!access_size_max) {
531 access_size_max = 4;
532 }
ce5d2f33
PB
533
534 /* FIXME: support unaligned access? */
164a4dcd 535 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 536 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB
537 if (memory_region_big_endian(mr)) {
538 for (i = 0; i < size; i += access_size) {
05e015f7 539 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 540 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
541 }
542 } else {
543 for (i = 0; i < size; i += access_size) {
05e015f7 544 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 545 access_mask, attrs);
e7342aa3 546 }
164a4dcd 547 }
cc05c43a 548 return r;
164a4dcd
AK
549}
550
e2177955
AK
551static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
552{
0d673e36
AK
553 AddressSpace *as;
554
feca4ac1
PB
555 while (mr->container) {
556 mr = mr->container;
e2177955 557 }
0d673e36
AK
558 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
559 if (mr == as->root) {
560 return as;
561 }
e2177955 562 }
eed2bacf 563 return NULL;
e2177955
AK
564}
565
093bc2cd
AK
566/* Render a memory region into the global view. Ranges in @view obscure
567 * ranges in @mr.
568 */
569static void render_memory_region(FlatView *view,
570 MemoryRegion *mr,
08dafab4 571 Int128 base,
fb1cd6f9 572 AddrRange clip,
c26763f8
MAL
573 bool readonly,
574 bool nonvolatile)
093bc2cd
AK
575{
576 MemoryRegion *subregion;
577 unsigned i;
a8170e5e 578 hwaddr offset_in_region;
08dafab4
AK
579 Int128 remain;
580 Int128 now;
093bc2cd
AK
581 FlatRange fr;
582 AddrRange tmp;
583
6bba19ba
AK
584 if (!mr->enabled) {
585 return;
586 }
587
08dafab4 588 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 589 readonly |= mr->readonly;
c26763f8 590 nonvolatile |= mr->nonvolatile;
093bc2cd
AK
591
592 tmp = addrrange_make(base, mr->size);
593
594 if (!addrrange_intersects(tmp, clip)) {
595 return;
596 }
597
598 clip = addrrange_intersection(tmp, clip);
599
600 if (mr->alias) {
08dafab4
AK
601 int128_subfrom(&base, int128_make64(mr->alias->addr));
602 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL
603 render_memory_region(view, mr->alias, base, clip,
604 readonly, nonvolatile);
093bc2cd
AK
605 return;
606 }
607
608 /* Render subregions in priority order. */
609 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL
610 render_memory_region(view, subregion, base, clip,
611 readonly, nonvolatile);
093bc2cd
AK
612 }
613
14a3c10a 614 if (!mr->terminates) {
093bc2cd
AK
615 return;
616 }
617
08dafab4 618 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
619 base = clip.start;
620 remain = clip.size;
621
2eb74e1a 622 fr.mr = mr;
6f6a5ef3 623 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 624 fr.romd_mode = mr->romd_mode;
2eb74e1a 625 fr.readonly = readonly;
c26763f8 626 fr.nonvolatile = nonvolatile;
2eb74e1a 627
093bc2cd 628 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
629 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
630 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
631 continue;
632 }
08dafab4
AK
633 if (int128_lt(base, view->ranges[i].addr.start)) {
634 now = int128_min(remain,
635 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
636 fr.offset_in_region = offset_in_region;
637 fr.addr = addrrange_make(base, now);
638 flatview_insert(view, i, &fr);
639 ++i;
08dafab4
AK
640 int128_addto(&base, now);
641 offset_in_region += int128_get64(now);
642 int128_subfrom(&remain, now);
093bc2cd 643 }
d26a8cae
AK
644 now = int128_sub(int128_min(int128_add(base, remain),
645 addrrange_end(view->ranges[i].addr)),
646 base);
647 int128_addto(&base, now);
648 offset_in_region += int128_get64(now);
649 int128_subfrom(&remain, now);
093bc2cd 650 }
08dafab4 651 if (int128_nz(remain)) {
093bc2cd
AK
652 fr.offset_in_region = offset_in_region;
653 fr.addr = addrrange_make(base, remain);
654 flatview_insert(view, i, &fr);
655 }
656}
657
89c177bb
AK
658static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
659{
e673ba9a
PB
660 while (mr->enabled) {
661 if (mr->alias) {
662 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
663 /* The alias is included in its entirety. Use it as
664 * the "real" root, so that we can share more FlatViews.
665 */
666 mr = mr->alias;
667 continue;
668 }
669 } else if (!mr->terminates) {
670 unsigned int found = 0;
671 MemoryRegion *child, *next = NULL;
672 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
673 if (child->enabled) {
674 if (++found > 1) {
675 next = NULL;
676 break;
677 }
678 if (!child->addr && int128_ge(mr->size, child->size)) {
679 /* A child is included in its entirety. If it's the only
680 * enabled one, use it in the hope of finding an alias down the
681 * way. This will also let us share FlatViews.
682 */
683 next = child;
684 }
685 }
686 }
092aa2fc
AK
687 if (found == 0) {
688 return NULL;
689 }
e673ba9a
PB
690 if (next) {
691 mr = next;
692 continue;
693 }
694 }
695
092aa2fc 696 return mr;
89c177bb
AK
697 }
698
092aa2fc 699 return NULL;
89c177bb
AK
700}
701
093bc2cd 702/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 703static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 704{
9bf561e3 705 int i;
a9a0c06d 706 FlatView *view;
093bc2cd 707
89c177bb 708 view = flatview_new(mr);
093bc2cd 709
83f3c251 710 if (mr) {
a9a0c06d 711 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL
712 addrrange_make(int128_zero(), int128_2_64()),
713 false, false);
83f3c251 714 }
a9a0c06d 715 flatview_simplify(view);
093bc2cd 716
9bf561e3
AK
717 view->dispatch = address_space_dispatch_new(view);
718 for (i = 0; i < view->nr; i++) {
719 MemoryRegionSection mrs =
720 section_from_flat_range(&view->ranges[i], view);
721 flatview_add_to_dispatch(view, &mrs);
722 }
723 address_space_dispatch_compact(view->dispatch);
967dc9b1 724 g_hash_table_replace(flat_views, mr, view);
9bf561e3 725
093bc2cd
AK
726 return view;
727}
728
3e9d69e7
AK
729static void address_space_add_del_ioeventfds(AddressSpace *as,
730 MemoryRegionIoeventfd *fds_new,
731 unsigned fds_new_nb,
732 MemoryRegionIoeventfd *fds_old,
733 unsigned fds_old_nb)
734{
735 unsigned iold, inew;
80a1ea37
AK
736 MemoryRegionIoeventfd *fd;
737 MemoryRegionSection section;
3e9d69e7
AK
738
739 /* Generate a symmetric difference of the old and new fd sets, adding
740 * and deleting as necessary.
741 */
742
743 iold = inew = 0;
744 while (iold < fds_old_nb || inew < fds_new_nb) {
745 if (iold < fds_old_nb
746 && (inew == fds_new_nb
73bb753d
TB
747 || memory_region_ioeventfd_before(&fds_old[iold],
748 &fds_new[inew]))) {
80a1ea37
AK
749 fd = &fds_old[iold];
750 section = (MemoryRegionSection) {
16620684 751 .fv = address_space_to_flatview(as),
80a1ea37 752 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 753 .size = fd->addr.size,
80a1ea37 754 };
9a54635d 755 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 756 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
757 ++iold;
758 } else if (inew < fds_new_nb
759 && (iold == fds_old_nb
73bb753d
TB
760 || memory_region_ioeventfd_before(&fds_new[inew],
761 &fds_old[iold]))) {
80a1ea37
AK
762 fd = &fds_new[inew];
763 section = (MemoryRegionSection) {
16620684 764 .fv = address_space_to_flatview(as),
80a1ea37 765 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 766 .size = fd->addr.size,
80a1ea37 767 };
9a54635d 768 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 769 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
770 ++inew;
771 } else {
772 ++iold;
773 ++inew;
774 }
775 }
776}
777
48564041 778FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB
779{
780 FlatView *view;
781
694ea274 782 RCU_READ_LOCK_GUARD();
447b0d0b 783 do {
16620684 784 view = address_space_to_flatview(as);
447b0d0b
PB
785 /* If somebody has replaced as->current_map concurrently,
786 * flatview_ref returns false.
787 */
788 } while (!flatview_ref(view));
856d7245
PB
789 return view;
790}
791
3e9d69e7
AK
792static void address_space_update_ioeventfds(AddressSpace *as)
793{
99e86347 794 FlatView *view;
3e9d69e7
AK
795 FlatRange *fr;
796 unsigned ioeventfd_nb = 0;
920d557e
SH
797 unsigned ioeventfd_max;
798 MemoryRegionIoeventfd *ioeventfds;
3e9d69e7
AK
799 AddrRange tmp;
800 unsigned i;
801
920d557e
SH
802 /*
803 * It is likely that the number of ioeventfds hasn't changed much, so use
804 * the previous size as the starting value, with some headroom to avoid
805 * gratuitous reallocations.
806 */
807 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
808 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
809
856d7245 810 view = address_space_get_flatview(as);
99e86347 811 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
812 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
813 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
814 int128_sub(fr->addr.start,
815 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
816 if (addrrange_intersects(fr->addr, tmp)) {
817 ++ioeventfd_nb;
920d557e
SH
818 if (ioeventfd_nb > ioeventfd_max) {
819 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
820 ioeventfds = g_realloc(ioeventfds,
821 ioeventfd_max * sizeof(*ioeventfds));
822 }
3e9d69e7
AK
823 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
824 ioeventfds[ioeventfd_nb-1].addr = tmp;
825 }
826 }
827 }
828
829 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
830 as->ioeventfds, as->ioeventfd_nb);
831
7267c094 832 g_free(as->ioeventfds);
3e9d69e7
AK
833 as->ioeventfds = ioeventfds;
834 as->ioeventfd_nb = ioeventfd_nb;
856d7245 835 flatview_unref(view);
3e9d69e7
AK
836}
837
23f1174a
PX
838/*
839 * Notify the memory listeners about the coalesced IO change events of
840 * range `cmr'. Only the part that has intersection of the specified
841 * FlatRange will be sent.
842 */
843static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
844 CoalescedMemoryRange *cmr, bool add)
845{
846 AddrRange tmp;
847
848 tmp = addrrange_shift(cmr->addr,
849 int128_sub(fr->addr.start,
850 int128_make64(fr->offset_in_region)));
851 if (!addrrange_intersects(tmp, fr->addr)) {
852 return;
853 }
854 tmp = addrrange_intersection(tmp, fr->addr);
855
856 if (add) {
857 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
858 int128_get64(tmp.start),
859 int128_get64(tmp.size));
860 } else {
861 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
862 int128_get64(tmp.start),
863 int128_get64(tmp.size));
864 }
865}
866
909bf763
PB
867static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
868{
23f1174a
PX
869 CoalescedMemoryRange *cmr;
870
23f1174a
PX
871 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
872 flat_range_coalesced_io_notify(fr, as, cmr, false);
873 }
909bf763
PB
874}
875
876static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
877{
878 MemoryRegion *mr = fr->mr;
879 CoalescedMemoryRange *cmr;
909bf763 880
1f7af804
PB
881 if (QTAILQ_EMPTY(&mr->coalesced)) {
882 return;
883 }
884
909bf763 885 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
23f1174a 886 flat_range_coalesced_io_notify(fr, as, cmr, true);
909bf763
PB
887 }
888}
889
b8af1afb 890static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
891 const FlatView *old_view,
892 const FlatView *new_view,
b8af1afb 893 bool adding)
093bc2cd 894{
093bc2cd
AK
895 unsigned iold, inew;
896 FlatRange *frold, *frnew;
093bc2cd
AK
897
898 /* Generate a symmetric difference of the old and new memory maps.
899 * Kill ranges in the old map, and instantiate ranges in the new map.
900 */
901 iold = inew = 0;
a9a0c06d
PB
902 while (iold < old_view->nr || inew < new_view->nr) {
903 if (iold < old_view->nr) {
904 frold = &old_view->ranges[iold];
093bc2cd
AK
905 } else {
906 frold = NULL;
907 }
a9a0c06d
PB
908 if (inew < new_view->nr) {
909 frnew = &new_view->ranges[inew];
093bc2cd
AK
910 } else {
911 frnew = NULL;
912 }
913
914 if (frold
915 && (!frnew
08dafab4
AK
916 || int128_lt(frold->addr.start, frnew->addr.start)
917 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 918 && !flatrange_equal(frold, frnew)))) {
41a6e477 919 /* In old but not in new, or in both but attributes changed. */
093bc2cd 920
b8af1afb 921 if (!adding) {
3ac7d43a 922 flat_range_coalesced_io_del(frold, as);
72e22d2f 923 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
924 }
925
093bc2cd
AK
926 ++iold;
927 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 928 /* In both and unchanged (except logging may have changed) */
093bc2cd 929
4f826024 930 if (adding) {
50c1e149 931 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
932 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
933 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
934 frold->dirty_log_mask,
935 frnew->dirty_log_mask);
936 }
937 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
938 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
939 frold->dirty_log_mask,
940 frnew->dirty_log_mask);
b8af1afb 941 }
5a583347
AK
942 }
943
093bc2cd
AK
944 ++iold;
945 ++inew;
093bc2cd
AK
946 } else {
947 /* In new */
948
b8af1afb 949 if (adding) {
72e22d2f 950 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
3ac7d43a 951 flat_range_coalesced_io_add(frnew, as);
b8af1afb
AK
952 }
953
093bc2cd
AK
954 ++inew;
955 }
956 }
b8af1afb
AK
957}
958
967dc9b1
AK
959static void flatviews_init(void)
960{
092aa2fc
AK
961 static FlatView *empty_view;
962
967dc9b1
AK
963 if (flat_views) {
964 return;
965 }
966
967 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
968 (GDestroyNotify) flatview_unref);
092aa2fc
AK
969 if (!empty_view) {
970 empty_view = generate_memory_topology(NULL);
971 /* We keep it alive forever in the global variable. */
972 flatview_ref(empty_view);
973 } else {
974 g_hash_table_replace(flat_views, NULL, empty_view);
975 flatview_ref(empty_view);
976 }
967dc9b1
AK
977}
978
979static void flatviews_reset(void)
980{
981 AddressSpace *as;
982
983 if (flat_views) {
984 g_hash_table_unref(flat_views);
985 flat_views = NULL;
986 }
987 flatviews_init();
988
989 /* Render unique FVs */
990 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
991 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
992
993 if (g_hash_table_lookup(flat_views, physmr)) {
994 continue;
995 }
996
997 generate_memory_topology(physmr);
998 }
999}
1000
1001static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1002{
67ace39b 1003 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
1004 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1005 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1006
1007 assert(new_view);
1008
67ace39b
AK
1009 if (old_view == new_view) {
1010 return;
1011 }
1012
1013 if (old_view) {
1014 flatview_ref(old_view);
1015 }
1016
967dc9b1 1017 flatview_ref(new_view);
9a62e24f
AK
1018
1019 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1020 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1021
1022 if (!old_view2) {
1023 old_view2 = &tmpview;
1024 }
1025 address_space_update_topology_pass(as, old_view2, new_view, false);
1026 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1027 }
b8af1afb 1028
374f2981
PB
1029 /* Writes are protected by the BQL. */
1030 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1031 if (old_view) {
1032 flatview_unref(old_view);
1033 }
856d7245
PB
1034
1035 /* Note that all the old MemoryRegions are still alive up to this
1036 * point. This relieves most MemoryListeners from the need to
1037 * ref/unref the MemoryRegions they get---unless they use them
1038 * outside the iothread mutex, in which case precise reference
1039 * counting is necessary.
1040 */
67ace39b
AK
1041 if (old_view) {
1042 flatview_unref(old_view);
1043 }
093bc2cd
AK
1044}
1045
202fc01b
AK
1046static void address_space_update_topology(AddressSpace *as)
1047{
1048 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1049
1050 flatviews_init();
1051 if (!g_hash_table_lookup(flat_views, physmr)) {
1052 generate_memory_topology(physmr);
1053 }
1054 address_space_set_flatview(as);
1055}
1056
4ef4db86
AK
1057void memory_region_transaction_begin(void)
1058{
bb880ded 1059 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1060 ++memory_region_transaction_depth;
1061}
1062
1063void memory_region_transaction_commit(void)
1064{
0d673e36
AK
1065 AddressSpace *as;
1066
4ef4db86 1067 assert(memory_region_transaction_depth);
8d04fb55
JK
1068 assert(qemu_mutex_iothread_locked());
1069
4ef4db86 1070 --memory_region_transaction_depth;
4dc56152
GA
1071 if (!memory_region_transaction_depth) {
1072 if (memory_region_update_pending) {
967dc9b1
AK
1073 flatviews_reset();
1074
4dc56152 1075 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1076
4dc56152 1077 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1078 address_space_set_flatview(as);
02218487 1079 address_space_update_ioeventfds(as);
4dc56152 1080 }
ade9c1aa 1081 memory_region_update_pending = false;
0b152095 1082 ioeventfd_update_pending = false;
4dc56152
GA
1083 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1084 } else if (ioeventfd_update_pending) {
1085 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1086 address_space_update_ioeventfds(as);
1087 }
ade9c1aa 1088 ioeventfd_update_pending = false;
4dc56152 1089 }
4dc56152 1090 }
4ef4db86
AK
1091}
1092
545e92e0
AK
1093static void memory_region_destructor_none(MemoryRegion *mr)
1094{
1095}
1096
1097static void memory_region_destructor_ram(MemoryRegion *mr)
1098{
f1060c55 1099 qemu_ram_free(mr->ram_block);
545e92e0
AK
1100}
1101
b4fefef9
PC
1102static bool memory_region_need_escape(char c)
1103{
1104 return c == '/' || c == '[' || c == '\\' || c == ']';
1105}
1106
1107static char *memory_region_escape_name(const char *name)
1108{
1109 const char *p;
1110 char *escaped, *q;
1111 uint8_t c;
1112 size_t bytes = 0;
1113
1114 for (p = name; *p; p++) {
1115 bytes += memory_region_need_escape(*p) ? 4 : 1;
1116 }
1117 if (bytes == p - name) {
1118 return g_memdup(name, bytes + 1);
1119 }
1120
1121 escaped = g_malloc(bytes + 1);
1122 for (p = name, q = escaped; *p; p++) {
1123 c = *p;
1124 if (unlikely(memory_region_need_escape(c))) {
1125 *q++ = '\\';
1126 *q++ = 'x';
1127 *q++ = "0123456789abcdef"[c >> 4];
1128 c = "0123456789abcdef"[c & 15];
1129 }
1130 *q++ = c;
1131 }
1132 *q = 0;
1133 return escaped;
1134}
1135
3df9d748
AK
1136static void memory_region_do_init(MemoryRegion *mr,
1137 Object *owner,
1138 const char *name,
1139 uint64_t size)
093bc2cd 1140{
08dafab4
AK
1141 mr->size = int128_make64(size);
1142 if (size == UINT64_MAX) {
1143 mr->size = int128_2_64();
1144 }
302fa283 1145 mr->name = g_strdup(name);
612263cf 1146 mr->owner = owner;
58eaa217 1147 mr->ram_block = NULL;
b4fefef9
PC
1148
1149 if (name) {
843ef73a
PC
1150 char *escaped_name = memory_region_escape_name(name);
1151 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1152
1153 if (!owner) {
1154 owner = container_get(qdev_get_machine(), "/unattached");
1155 }
1156
843ef73a 1157 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1158 object_unref(OBJECT(mr));
843ef73a
PC
1159 g_free(name_array);
1160 g_free(escaped_name);
b4fefef9
PC
1161 }
1162}
1163
3df9d748
AK
1164void memory_region_init(MemoryRegion *mr,
1165 Object *owner,
1166 const char *name,
1167 uint64_t size)
1168{
1169 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1170 memory_region_do_init(mr, owner, name, size);
1171}
1172
d7bce999
EB
1173static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1174 void *opaque, Error **errp)
409ddd01
PC
1175{
1176 MemoryRegion *mr = MEMORY_REGION(obj);
1177 uint64_t value = mr->addr;
1178
51e72bc1 1179 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1180}
1181
d7bce999
EB
1182static void memory_region_get_container(Object *obj, Visitor *v,
1183 const char *name, void *opaque,
1184 Error **errp)
409ddd01
PC
1185{
1186 MemoryRegion *mr = MEMORY_REGION(obj);
1187 gchar *path = (gchar *)"";
1188
1189 if (mr->container) {
1190 path = object_get_canonical_path(OBJECT(mr->container));
1191 }
51e72bc1 1192 visit_type_str(v, name, &path, errp);
409ddd01
PC
1193 if (mr->container) {
1194 g_free(path);
1195 }
1196}
1197
1198static Object *memory_region_resolve_container(Object *obj, void *opaque,
1199 const char *part)
1200{
1201 MemoryRegion *mr = MEMORY_REGION(obj);
1202
1203 return OBJECT(mr->container);
1204}
1205
d7bce999
EB
1206static void memory_region_get_priority(Object *obj, Visitor *v,
1207 const char *name, void *opaque,
1208 Error **errp)
d33382da
PC
1209{
1210 MemoryRegion *mr = MEMORY_REGION(obj);
1211 int32_t value = mr->priority;
1212
51e72bc1 1213 visit_type_int32(v, name, &value, errp);
d33382da
PC
1214}
1215
d7bce999
EB
1216static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1217 void *opaque, Error **errp)
52aef7bb
PC
1218{
1219 MemoryRegion *mr = MEMORY_REGION(obj);
1220 uint64_t value = memory_region_size(mr);
1221
51e72bc1 1222 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1223}
1224
b4fefef9
PC
1225static void memory_region_initfn(Object *obj)
1226{
1227 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1228 ObjectProperty *op;
b4fefef9
PC
1229
1230 mr->ops = &unassigned_mem_ops;
6bba19ba 1231 mr->enabled = true;
5f9a5ea1 1232 mr->romd_mode = true;
196ea131 1233 mr->global_locking = true;
545e92e0 1234 mr->destructor = memory_region_destructor_none;
093bc2cd 1235 QTAILQ_INIT(&mr->subregions);
093bc2cd 1236 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1237
1238 op = object_property_add(OBJECT(mr), "container",
1239 "link<" TYPE_MEMORY_REGION ">",
1240 memory_region_get_container,
1241 NULL, /* memory_region_set_container */
1242 NULL, NULL, &error_abort);
1243 op->resolve = memory_region_resolve_container;
1244
1245 object_property_add(OBJECT(mr), "addr", "uint64",
1246 memory_region_get_addr,
1247 NULL, /* memory_region_set_addr */
1248 NULL, NULL, &error_abort);
d33382da
PC
1249 object_property_add(OBJECT(mr), "priority", "uint32",
1250 memory_region_get_priority,
1251 NULL, /* memory_region_set_priority */
1252 NULL, NULL, &error_abort);
52aef7bb
PC
1253 object_property_add(OBJECT(mr), "size", "uint64",
1254 memory_region_get_size,
1255 NULL, /* memory_region_set_size, */
1256 NULL, NULL, &error_abort);
093bc2cd
AK
1257}
1258
3df9d748
AK
1259static void iommu_memory_region_initfn(Object *obj)
1260{
1261 MemoryRegion *mr = MEMORY_REGION(obj);
1262
1263 mr->is_iommu = true;
1264}
1265
b018ddf6
PB
1266static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1267 unsigned size)
1268{
1269#ifdef DEBUG_UNASSIGNED
1270 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1271#endif
68a7439a 1272 return 0;
b018ddf6
PB
1273}
1274
1275static void unassigned_mem_write(void *opaque, hwaddr addr,
1276 uint64_t val, unsigned size)
1277{
1278#ifdef DEBUG_UNASSIGNED
1279 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1280#endif
b018ddf6
PB
1281}
1282
d197063f 1283static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM
1284 unsigned size, bool is_write,
1285 MemTxAttrs attrs)
d197063f
PB
1286{
1287 return false;
1288}
1289
1290const MemoryRegionOps unassigned_mem_ops = {
1291 .valid.accepts = unassigned_mem_accepts,
1292 .endianness = DEVICE_NATIVE_ENDIAN,
1293};
1294
4a2e242b
AW
1295static uint64_t memory_region_ram_device_read(void *opaque,
1296 hwaddr addr, unsigned size)
1297{
1298 MemoryRegion *mr = opaque;
1299 uint64_t data = (uint64_t)~0;
1300
1301 switch (size) {
1302 case 1:
1303 data = *(uint8_t *)(mr->ram_block->host + addr);
1304 break;
1305 case 2:
1306 data = *(uint16_t *)(mr->ram_block->host + addr);
1307 break;
1308 case 4:
1309 data = *(uint32_t *)(mr->ram_block->host + addr);
1310 break;
1311 case 8:
1312 data = *(uint64_t *)(mr->ram_block->host + addr);
1313 break;
1314 }
1315
1316 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1317
1318 return data;
1319}
1320
1321static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1322 uint64_t data, unsigned size)
1323{
1324 MemoryRegion *mr = opaque;
1325
1326 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1327
1328 switch (size) {
1329 case 1:
1330 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1331 break;
1332 case 2:
1333 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1334 break;
1335 case 4:
1336 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1337 break;
1338 case 8:
1339 *(uint64_t *)(mr->ram_block->host + addr) = data;
1340 break;
1341 }
1342}
1343
1344static const MemoryRegionOps ram_device_mem_ops = {
1345 .read = memory_region_ram_device_read,
1346 .write = memory_region_ram_device_write,
c99a29e7 1347 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1348 .valid = {
1349 .min_access_size = 1,
1350 .max_access_size = 8,
1351 .unaligned = true,
1352 },
1353 .impl = {
1354 .min_access_size = 1,
1355 .max_access_size = 8,
1356 .unaligned = true,
1357 },
1358};
1359
d2702032
PB
1360bool memory_region_access_valid(MemoryRegion *mr,
1361 hwaddr addr,
1362 unsigned size,
6d7b9a6c
PM
1363 bool is_write,
1364 MemTxAttrs attrs)
093bc2cd 1365{
a014ed07
PB
1366 int access_size_min, access_size_max;
1367 int access_size, i;
897fa7cf 1368
093bc2cd
AK
1369 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1370 return false;
1371 }
1372
a014ed07 1373 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1374 return true;
1375 }
1376
a014ed07
PB
1377 access_size_min = mr->ops->valid.min_access_size;
1378 if (!mr->ops->valid.min_access_size) {
1379 access_size_min = 1;
1380 }
1381
1382 access_size_max = mr->ops->valid.max_access_size;
1383 if (!mr->ops->valid.max_access_size) {
1384 access_size_max = 4;
1385 }
1386
1387 access_size = MAX(MIN(size, access_size_max), access_size_min);
1388 for (i = 0; i < size; i += access_size) {
1389 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
8372d383 1390 is_write, attrs)) {
a014ed07
PB
1391 return false;
1392 }
093bc2cd 1393 }
a014ed07 1394
093bc2cd
AK
1395 return true;
1396}
1397
cc05c43a
PM
1398static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1399 hwaddr addr,
1400 uint64_t *pval,
1401 unsigned size,
1402 MemTxAttrs attrs)
093bc2cd 1403{
cc05c43a 1404 *pval = 0;
093bc2cd 1405
ce5d2f33 1406 if (mr->ops->read) {
cc05c43a
PM
1407 return access_with_adjusted_size(addr, pval, size,
1408 mr->ops->impl.min_access_size,
1409 mr->ops->impl.max_access_size,
1410 memory_region_read_accessor,
1411 mr, attrs);
62a0db94 1412 } else {
cc05c43a
PM
1413 return access_with_adjusted_size(addr, pval, size,
1414 mr->ops->impl.min_access_size,
1415 mr->ops->impl.max_access_size,
1416 memory_region_read_with_attrs_accessor,
1417 mr, attrs);
74901c3b 1418 }
093bc2cd
AK
1419}
1420
3b643495
PM
1421MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1422 hwaddr addr,
1423 uint64_t *pval,
e67c9046 1424 MemOp op,
3b643495 1425 MemTxAttrs attrs)
a621f38d 1426{
e67c9046 1427 unsigned size = memop_size(op);
cc05c43a
PM
1428 MemTxResult r;
1429
6d7b9a6c 1430 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1431 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1432 return MEMTX_DECODE_ERROR;
791af8c8 1433 }
a621f38d 1434
cc05c43a 1435 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
9bf825bf 1436 adjust_endianness(mr, pval, op);
cc05c43a 1437 return r;
a621f38d 1438}
093bc2cd 1439
8c56c1a5
PF
1440/* Return true if an eventfd was signalled */
1441static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1442 hwaddr addr,
1443 uint64_t data,
1444 unsigned size,
1445 MemTxAttrs attrs)
1446{
1447 MemoryRegionIoeventfd ioeventfd = {
1448 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1449 .data = data,
1450 };
1451 unsigned i;
1452
1453 for (i = 0; i < mr->ioeventfd_nb; i++) {
1454 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1455 ioeventfd.e = mr->ioeventfds[i].e;
1456
73bb753d 1457 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF
1458 event_notifier_set(ioeventfd.e);
1459 return true;
1460 }
1461 }
1462
1463 return false;
1464}
1465
3b643495
PM
1466MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1467 hwaddr addr,
1468 uint64_t data,
e67c9046 1469 MemOp op,
3b643495 1470 MemTxAttrs attrs)
a621f38d 1471{
e67c9046
TN
1472 unsigned size = memop_size(op);
1473
6d7b9a6c 1474 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1475 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1476 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1477 }
1478
9bf825bf 1479 adjust_endianness(mr, &data, op);
a621f38d 1480
8c56c1a5
PF
1481 if ((!kvm_eventfds_enabled()) &&
1482 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1483 return MEMTX_OK;
1484 }
1485
ce5d2f33 1486 if (mr->ops->write) {
cc05c43a
PM
1487 return access_with_adjusted_size(addr, &data, size,
1488 mr->ops->impl.min_access_size,
1489 mr->ops->impl.max_access_size,
1490 memory_region_write_accessor, mr,
1491 attrs);
62a0db94 1492 } else {
cc05c43a
PM
1493 return
1494 access_with_adjusted_size(addr, &data, size,
1495 mr->ops->impl.min_access_size,
1496 mr->ops->impl.max_access_size,
1497 memory_region_write_with_attrs_accessor,
1498 mr, attrs);
74901c3b 1499 }
093bc2cd
AK
1500}
1501
093bc2cd 1502void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1503 Object *owner,
093bc2cd
AK
1504 const MemoryRegionOps *ops,
1505 void *opaque,
1506 const char *name,
1507 uint64_t size)
1508{
2c9b15ca 1509 memory_region_init(mr, owner, name, size);
6d6d2abf 1510 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1511 mr->opaque = opaque;
14a3c10a 1512 mr->terminates = true;
093bc2cd
AK
1513}
1514
1cfe48c1
PM
1515void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1516 Object *owner,
1517 const char *name,
1518 uint64_t size,
1519 Error **errp)
06329cce
MA
1520{
1521 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1522}
1523
1524void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1525 Object *owner,
1526 const char *name,
1527 uint64_t size,
1528 bool share,
1529 Error **errp)
093bc2cd 1530{
1cd3d492 1531 Error *err = NULL;
2c9b15ca 1532 memory_region_init(mr, owner, name, size);
8ea9252a 1533 mr->ram = true;
14a3c10a 1534 mr->terminates = true;
545e92e0 1535 mr->destructor = memory_region_destructor_ram;
1cd3d492 1536 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
677e7805 1537 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1538 if (err) {
1539 mr->size = int128_zero();
1540 object_unparent(OBJECT(mr));
1541 error_propagate(errp, err);
1542 }
0b183fc8
PB
1543}
1544
60786ef3
MT
1545void memory_region_init_resizeable_ram(MemoryRegion *mr,
1546 Object *owner,
1547 const char *name,
1548 uint64_t size,
1549 uint64_t max_size,
1550 void (*resized)(const char*,
1551 uint64_t length,
1552 void *host),
1553 Error **errp)
1554{
1cd3d492 1555 Error *err = NULL;
60786ef3
MT
1556 memory_region_init(mr, owner, name, size);
1557 mr->ram = true;
1558 mr->terminates = true;
1559 mr->destructor = memory_region_destructor_ram;
8e41fb63 1560 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1561 mr, &err);
677e7805 1562 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1563 if (err) {
1564 mr->size = int128_zero();
1565 object_unparent(OBJECT(mr));
1566 error_propagate(errp, err);
1567 }
60786ef3
MT
1568}
1569
d5dbde46 1570#ifdef CONFIG_POSIX
0b183fc8
PB
1571void memory_region_init_ram_from_file(MemoryRegion *mr,
1572 struct Object *owner,
1573 const char *name,
1574 uint64_t size,
98376843 1575 uint64_t align,
cbfc0171 1576 uint32_t ram_flags,
7f56e740
PB
1577 const char *path,
1578 Error **errp)
0b183fc8 1579{
1cd3d492 1580 Error *err = NULL;
0b183fc8
PB
1581 memory_region_init(mr, owner, name, size);
1582 mr->ram = true;
1583 mr->terminates = true;
1584 mr->destructor = memory_region_destructor_ram;
98376843 1585 mr->align = align;
1cd3d492 1586 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
677e7805 1587 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1588 if (err) {
1589 mr->size = int128_zero();
1590 object_unparent(OBJECT(mr));
1591 error_propagate(errp, err);
1592 }
093bc2cd 1593}
fea617c5
MAL
1594
1595void memory_region_init_ram_from_fd(MemoryRegion *mr,
1596 struct Object *owner,
1597 const char *name,
1598 uint64_t size,
1599 bool share,
1600 int fd,
1601 Error **errp)
1602{
1cd3d492 1603 Error *err = NULL;
fea617c5
MAL
1604 memory_region_init(mr, owner, name, size);
1605 mr->ram = true;
1606 mr->terminates = true;
1607 mr->destructor = memory_region_destructor_ram;
cbfc0171
JH
1608 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1609 share ? RAM_SHARED : 0,
1cd3d492 1610 fd, &err);
fea617c5 1611 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1612 if (err) {
1613 mr->size = int128_zero();
1614 object_unparent(OBJECT(mr));
1615 error_propagate(errp, err);
1616 }
fea617c5 1617}
0b183fc8 1618#endif
093bc2cd
AK
1619
1620void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1621 Object *owner,
093bc2cd
AK
1622 const char *name,
1623 uint64_t size,
1624 void *ptr)
1625{
2c9b15ca 1626 memory_region_init(mr, owner, name, size);
8ea9252a 1627 mr->ram = true;
14a3c10a 1628 mr->terminates = true;
fc3e7665 1629 mr->destructor = memory_region_destructor_ram;
677e7805 1630 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1631
1632 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1633 assert(ptr != NULL);
8e41fb63 1634 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1635}
1636
21e00fa5
AW
1637void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1638 Object *owner,
1639 const char *name,
1640 uint64_t size,
1641 void *ptr)
e4dc3f59 1642{
2ddb89b0
BS
1643 memory_region_init(mr, owner, name, size);
1644 mr->ram = true;
1645 mr->terminates = true;
21e00fa5 1646 mr->ram_device = true;
4a2e242b
AW
1647 mr->ops = &ram_device_mem_ops;
1648 mr->opaque = mr;
2ddb89b0
BS
1649 mr->destructor = memory_region_destructor_ram;
1650 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1651 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1652 assert(ptr != NULL);
1653 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
e4dc3f59
ND
1654}
1655
093bc2cd 1656void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1657 Object *owner,
093bc2cd
AK
1658 const char *name,
1659 MemoryRegion *orig,
a8170e5e 1660 hwaddr offset,
093bc2cd
AK
1661 uint64_t size)
1662{
2c9b15ca 1663 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1664 mr->alias = orig;
1665 mr->alias_offset = offset;
1666}
1667
b59821a9
PM
1668void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1669 struct Object *owner,
1670 const char *name,
1671 uint64_t size,
1672 Error **errp)
a1777f7f 1673{
1cd3d492 1674 Error *err = NULL;
a1777f7f
PM
1675 memory_region_init(mr, owner, name, size);
1676 mr->ram = true;
1677 mr->readonly = true;
1678 mr->terminates = true;
1679 mr->destructor = memory_region_destructor_ram;
1cd3d492 1680 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
a1777f7f 1681 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1682 if (err) {
1683 mr->size = int128_zero();
1684 object_unparent(OBJECT(mr));
1685 error_propagate(errp, err);
1686 }
a1777f7f
PM
1687}
1688
b59821a9
PM
1689void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1690 Object *owner,
1691 const MemoryRegionOps *ops,
1692 void *opaque,
1693 const char *name,
1694 uint64_t size,
1695 Error **errp)
d0a9b5bc 1696{
1cd3d492 1697 Error *err = NULL;
39e0b03d 1698 assert(ops);
2c9b15ca 1699 memory_region_init(mr, owner, name, size);
7bc2b9cd 1700 mr->ops = ops;
75f5941c 1701 mr->opaque = opaque;
d0a9b5bc 1702 mr->terminates = true;
75c578dc 1703 mr->rom_device = true;
58268c8d 1704 mr->destructor = memory_region_destructor_ram;
1cd3d492
IM
1705 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1706 if (err) {
1707 mr->size = int128_zero();
1708 object_unparent(OBJECT(mr));
1709 error_propagate(errp, err);
1710 }
d0a9b5bc
AK
1711}
1712
1221a474
AK
1713void memory_region_init_iommu(void *_iommu_mr,
1714 size_t instance_size,
1715 const char *mrtypename,
2c9b15ca 1716 Object *owner,
30951157
AK
1717 const char *name,
1718 uint64_t size)
1719{
1221a474 1720 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1721 struct MemoryRegion *mr;
1722
1221a474
AK
1723 object_initialize(_iommu_mr, instance_size, mrtypename);
1724 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1725 memory_region_do_init(mr, owner, name, size);
1726 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1727 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1728 QLIST_INIT(&iommu_mr->iommu_notify);
1729 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1730}
1731
b4fefef9 1732static void memory_region_finalize(Object *obj)
093bc2cd 1733{
b4fefef9
PC
1734 MemoryRegion *mr = MEMORY_REGION(obj);
1735
2e2b8eb7
PB
1736 assert(!mr->container);
1737
1738 /* We know the region is not visible in any address space (it
1739 * does not have a container and cannot be a root either because
1740 * it has no references, so we can blindly clear mr->enabled.
1741 * memory_region_set_enabled instead could trigger a transaction
1742 * and cause an infinite loop.
1743 */
1744 mr->enabled = false;
1745 memory_region_transaction_begin();
1746 while (!QTAILQ_EMPTY(&mr->subregions)) {
1747 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1748 memory_region_del_subregion(mr, subregion);
1749 }
1750 memory_region_transaction_commit();
1751
545e92e0 1752 mr->destructor(mr);
093bc2cd 1753 memory_region_clear_coalescing(mr);
302fa283 1754 g_free((char *)mr->name);
7267c094 1755 g_free(mr->ioeventfds);
093bc2cd
AK
1756}
1757
803c0816
PB
1758Object *memory_region_owner(MemoryRegion *mr)
1759{
22a893e4
PB
1760 Object *obj = OBJECT(mr);
1761 return obj->parent;
803c0816
PB
1762}
1763
46637be2
PB
1764void memory_region_ref(MemoryRegion *mr)
1765{
22a893e4
PB
1766 /* MMIO callbacks most likely will access data that belongs
1767 * to the owner, hence the need to ref/unref the owner whenever
1768 * the memory region is in use.
1769 *
1770 * The memory region is a child of its owner. As long as the
1771 * owner doesn't call unparent itself on the memory region,
1772 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1773 * Memory regions without an owner are supposed to never go away;
1774 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1775 */
612263cf
PB
1776 if (mr && mr->owner) {
1777 object_ref(mr->owner);
46637be2
PB
1778 }
1779}
1780
1781void memory_region_unref(MemoryRegion *mr)
1782{
612263cf
PB
1783 if (mr && mr->owner) {
1784 object_unref(mr->owner);
46637be2
PB
1785 }
1786}
1787
093bc2cd
AK
1788uint64_t memory_region_size(MemoryRegion *mr)
1789{
08dafab4
AK
1790 if (int128_eq(mr->size, int128_2_64())) {
1791 return UINT64_MAX;
1792 }
1793 return int128_get64(mr->size);
093bc2cd
AK
1794}
1795
5d546d4b 1796const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1797{
d1dd32af
PC
1798 if (!mr->name) {
1799 ((MemoryRegion *)mr)->name =
1800 object_get_canonical_path_component(OBJECT(mr));
1801 }
302fa283 1802 return mr->name;
8991c79b
AK
1803}
1804
21e00fa5 1805bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1806{
21e00fa5 1807 return mr->ram_device;
e4dc3f59
ND
1808}
1809
2d1a35be 1810uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1811{
6f6a5ef3 1812 uint8_t mask = mr->dirty_log_mask;
adaad61c 1813 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1814 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1815 }
1816 return mask;
55043ba3
AK
1817}
1818
2d1a35be
PB
1819bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1820{
1821 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1822}
1823
549d4005
EA
1824static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1825 Error **errp)
5bf3d319
PX
1826{
1827 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1828 IOMMUNotifier *iommu_notifier;
1221a474 1829 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
549d4005 1830 int ret = 0;
5bf3d319 1831
3df9d748 1832 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1833 flags |= iommu_notifier->notifier_flags;
1834 }
1835
1221a474 1836 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
549d4005
EA
1837 ret = imrc->notify_flag_changed(iommu_mr,
1838 iommu_mr->iommu_notify_flags,
1839 flags, errp);
5bf3d319
PX
1840 }
1841
549d4005
EA
1842 if (!ret) {
1843 iommu_mr->iommu_notify_flags = flags;
1844 }
1845 return ret;
5bf3d319
PX
1846}
1847
549d4005
EA
1848int memory_region_register_iommu_notifier(MemoryRegion *mr,
1849 IOMMUNotifier *n, Error **errp)
06866575 1850{
3df9d748 1851 IOMMUMemoryRegion *iommu_mr;
549d4005 1852 int ret;
3df9d748 1853
efcd38c5 1854 if (mr->alias) {
549d4005 1855 return memory_region_register_iommu_notifier(mr->alias, n, errp);
efcd38c5
JW
1856 }
1857
cdb30812 1858 /* We need to register for at least one bitfield */
3df9d748 1859 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1860 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1861 assert(n->start <= n->end);
cb1efcf4
PM
1862 assert(n->iommu_idx >= 0 &&
1863 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1864
3df9d748 1865 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
549d4005
EA
1866 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1867 if (ret) {
1868 QLIST_REMOVE(n, node);
1869 }
1870 return ret;
06866575
DG
1871}
1872
3df9d748 1873uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1874{
1221a474
AK
1875 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1876
1877 if (imrc->get_min_page_size) {
1878 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1879 }
1880 return TARGET_PAGE_SIZE;
1881}
1882
3df9d748 1883void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1884{
3df9d748 1885 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1886 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1887 hwaddr addr, granularity;
a788f227
DG
1888 IOMMUTLBEntry iotlb;
1889
faa362e3 1890 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1891 if (imrc->replay) {
1892 imrc->replay(iommu_mr, n);
faa362e3
PX
1893 return;
1894 }
1895
3df9d748 1896 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1897
a788f227 1898 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1899 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG
1900 if (iotlb.perm != IOMMU_NONE) {
1901 n->notify(n, &iotlb);
1902 }
1903
1904 /* if (2^64 - MR size) < granularity, it's possible to get an
1905 * infinite loop here. This should catch such a wraparound */
1906 if ((addr + granularity) < addr) {
1907 break;
1908 }
1909 }
1910}
1911
cdb30812
PX
1912void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1913 IOMMUNotifier *n)
06866575 1914{
3df9d748
AK
1915 IOMMUMemoryRegion *iommu_mr;
1916
efcd38c5
JW
1917 if (mr->alias) {
1918 memory_region_unregister_iommu_notifier(mr->alias, n);
1919 return;
1920 }
cdb30812 1921 QLIST_REMOVE(n, node);
3df9d748 1922 iommu_mr = IOMMU_MEMORY_REGION(mr);
549d4005 1923 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
06866575
DG
1924}
1925
bd2bfa4c
PX
1926void memory_region_notify_one(IOMMUNotifier *notifier,
1927 IOMMUTLBEntry *entry)
06866575 1928{
cdb30812 1929 IOMMUNotifierFlag request_flags;
03c7140c 1930 hwaddr entry_end = entry->iova + entry->addr_mask;
cdb30812 1931
bd2bfa4c
PX
1932 /*
1933 * Skip the notification if the notification does not overlap
1934 * with registered range.
1935 */
03c7140c 1936 if (notifier->start > entry_end || notifier->end < entry->iova) {
bd2bfa4c
PX
1937 return;
1938 }
cdb30812 1939
03c7140c
YZ
1940 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1941
bd2bfa4c 1942 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1943 request_flags = IOMMU_NOTIFIER_MAP;
1944 } else {
1945 request_flags = IOMMU_NOTIFIER_UNMAP;
1946 }
1947
bd2bfa4c
PX
1948 if (notifier->notifier_flags & request_flags) {
1949 notifier->notify(notifier, entry);
1950 }
1951}
1952
3df9d748 1953void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1954 int iommu_idx,
bd2bfa4c
PX
1955 IOMMUTLBEntry entry)
1956{
1957 IOMMUNotifier *iommu_notifier;
1958
3df9d748 1959 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1960
3df9d748 1961 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4
PM
1962 if (iommu_notifier->iommu_idx == iommu_idx) {
1963 memory_region_notify_one(iommu_notifier, &entry);
1964 }
cdb30812 1965 }
06866575
DG
1966}
1967
f1334de6
AK
1968int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1969 enum IOMMUMemoryRegionAttr attr,
1970 void *data)
1971{
1972 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1973
1974 if (!imrc->get_attr) {
1975 return -EINVAL;
1976 }
1977
1978 return imrc->get_attr(iommu_mr, attr, data);
1979}
1980
21f40209
PM
1981int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1982 MemTxAttrs attrs)
1983{
1984 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1985
1986 if (!imrc->attrs_to_index) {
1987 return 0;
1988 }
1989
1990 return imrc->attrs_to_index(iommu_mr, attrs);
1991}
1992
1993int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1994{
1995 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1996
1997 if (!imrc->num_indexes) {
1998 return 1;
1999 }
2000
2001 return imrc->num_indexes(iommu_mr);
2002}
2003
093bc2cd
AK
2004void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2005{
5a583347 2006 uint8_t mask = 1 << client;
deb809ed 2007 uint8_t old_logging;
5a583347 2008
dbddac6d 2009 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
2010 old_logging = mr->vga_logging_count;
2011 mr->vga_logging_count += log ? 1 : -1;
2012 if (!!old_logging == !!mr->vga_logging_count) {
2013 return;
2014 }
2015
59023ef4 2016 memory_region_transaction_begin();
5a583347 2017 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 2018 memory_region_update_pending |= mr->enabled;
59023ef4 2019 memory_region_transaction_commit();
093bc2cd
AK
2020}
2021
a8170e5e
AK
2022void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2023 hwaddr size)
093bc2cd 2024{
8e41fb63
FZ
2025 assert(mr->ram_block);
2026 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2027 size,
58d2707e 2028 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
2029}
2030
0fe1eca7 2031static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2032{
0a752eee 2033 MemoryListener *listener;
0d673e36 2034 AddressSpace *as;
0a752eee 2035 FlatView *view;
5a583347
AK
2036 FlatRange *fr;
2037
0a752eee
PB
2038 /* If the same address space has multiple log_sync listeners, we
2039 * visit that address space's FlatView multiple times. But because
2040 * log_sync listeners are rare, it's still cheaper than walking each
2041 * address space once.
2042 */
2043 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2044 if (!listener->log_sync) {
2045 continue;
2046 }
2047 as = listener->address_space;
2048 view = address_space_get_flatview(as);
99e86347 2049 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2050 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2051 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2052 listener->log_sync(listener, &mrs);
0d673e36 2053 }
5a583347 2054 }
856d7245 2055 flatview_unref(view);
5a583347 2056 }
093bc2cd
AK
2057}
2058
077874e0
PX
2059void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2060 hwaddr len)
2061{
2062 MemoryRegionSection mrs;
2063 MemoryListener *listener;
2064 AddressSpace *as;
2065 FlatView *view;
2066 FlatRange *fr;
2067 hwaddr sec_start, sec_end, sec_size;
2068
2069 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2070 if (!listener->log_clear) {
2071 continue;
2072 }
2073 as = listener->address_space;
2074 view = address_space_get_flatview(as);
2075 FOR_EACH_FLAT_RANGE(fr, view) {
2076 if (!fr->dirty_log_mask || fr->mr != mr) {
2077 /*
2078 * Clear dirty bitmap operation only applies to those
2079 * regions whose dirty logging is at least enabled
2080 */
2081 continue;
2082 }
2083
2084 mrs = section_from_flat_range(fr, view);
2085
2086 sec_start = MAX(mrs.offset_within_region, start);
2087 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2088 sec_end = MIN(sec_end, start + len);
2089
2090 if (sec_start >= sec_end) {
2091 /*
2092 * If this memory region section has no intersection
2093 * with the requested range, skip.
2094 */
2095 continue;
2096 }
2097
2098 /* Valid case; shrink the section if needed */
2099 mrs.offset_within_address_space +=
2100 sec_start - mrs.offset_within_region;
2101 mrs.offset_within_region = sec_start;
2102 sec_size = sec_end - sec_start;
2103 mrs.size = int128_make64(sec_size);
2104 listener->log_clear(listener, &mrs);
2105 }
2106 flatview_unref(view);
2107 }
2108}
2109
0fe1eca7
PB
2110DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2111 hwaddr addr,
2112 hwaddr size,
2113 unsigned client)
2114{
9458a9a1 2115 DirtyBitmapSnapshot *snapshot;
0fe1eca7
PB
2116 assert(mr->ram_block);
2117 memory_region_sync_dirty_bitmap(mr);
9458a9a1
PB
2118 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2119 memory_global_after_dirty_log_sync();
2120 return snapshot;
0fe1eca7
PB
2121}
2122
2123bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2124 hwaddr addr, hwaddr size)
2125{
2126 assert(mr->ram_block);
2127 return cpu_physical_memory_snapshot_get_dirty(snap,
2128 memory_region_get_ram_addr(mr) + addr, size);
2129}
2130
093bc2cd
AK
2131void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2132{
fb1cd6f9 2133 if (mr->readonly != readonly) {
59023ef4 2134 memory_region_transaction_begin();
fb1cd6f9 2135 mr->readonly = readonly;
22bde714 2136 memory_region_update_pending |= mr->enabled;
59023ef4 2137 memory_region_transaction_commit();
fb1cd6f9 2138 }
093bc2cd
AK
2139}
2140
c26763f8
MAL
2141void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2142{
2143 if (mr->nonvolatile != nonvolatile) {
2144 memory_region_transaction_begin();
2145 mr->nonvolatile = nonvolatile;
2146 memory_region_update_pending |= mr->enabled;
2147 memory_region_transaction_commit();
2148 }
2149}
2150
5f9a5ea1 2151void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2152{
5f9a5ea1 2153 if (mr->romd_mode != romd_mode) {
59023ef4 2154 memory_region_transaction_begin();
5f9a5ea1 2155 mr->romd_mode = romd_mode;
22bde714 2156 memory_region_update_pending |= mr->enabled;
59023ef4 2157 memory_region_transaction_commit();
d0a9b5bc
AK
2158 }
2159}
2160
a8170e5e
AK
2161void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2162 hwaddr size, unsigned client)
093bc2cd 2163{
8e41fb63
FZ
2164 assert(mr->ram_block);
2165 cpu_physical_memory_test_and_clear_dirty(
2166 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2167}
2168
a35ba7be
PB
2169int memory_region_get_fd(MemoryRegion *mr)
2170{
4ff87573
PB
2171 int fd;
2172
694ea274 2173 RCU_READ_LOCK_GUARD();
4ff87573
PB
2174 while (mr->alias) {
2175 mr = mr->alias;
a35ba7be 2176 }
4ff87573 2177 fd = mr->ram_block->fd;
a35ba7be 2178
4ff87573
PB
2179 return fd;
2180}
a35ba7be 2181
093bc2cd
AK
2182void *memory_region_get_ram_ptr(MemoryRegion *mr)
2183{
49b24afc
PB
2184 void *ptr;
2185 uint64_t offset = 0;
093bc2cd 2186
694ea274 2187 RCU_READ_LOCK_GUARD();
49b24afc
PB
2188 while (mr->alias) {
2189 offset += mr->alias_offset;
2190 mr = mr->alias;
2191 }
8e41fb63 2192 assert(mr->ram_block);
0878d0e1 2193 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
093bc2cd 2194
0878d0e1 2195 return ptr;
093bc2cd
AK
2196}
2197
07bdaa41
PB
2198MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2199{
2200 RAMBlock *block;
2201
2202 block = qemu_ram_block_from_host(ptr, false, offset);
2203 if (!block) {
2204 return NULL;
2205 }
2206
2207 return block->mr;
2208}
2209
7ebb2745
FZ
2210ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2211{
2212 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2213}
2214
37d7c084
PB
2215void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2216{
8e41fb63 2217 assert(mr->ram_block);
37d7c084 2218
fa53a0e5 2219 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2220}
2221
61c490e2
BM
2222
2223void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
2224{
2225 /*
2226 * Might be extended case needed to cover
2227 * different types of memory regions
2228 */
2229 if (mr->ram_block && mr->dirty_log_mask) {
2230 qemu_ram_writeback(mr->ram_block, addr, size);
2231 }
2232}
2233
b960fc17
PX
2234/*
2235 * Call proper memory listeners about the change on the newly
2236 * added/removed CoalescedMemoryRange.
2237 */
2238static void memory_region_update_coalesced_range(MemoryRegion *mr,
2239 CoalescedMemoryRange *cmr,
2240 bool add)
093bc2cd 2241{
b960fc17 2242 AddressSpace *as;
99e86347 2243 FlatView *view;
093bc2cd 2244 FlatRange *fr;
093bc2cd 2245
0d673e36 2246 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b960fc17
PX
2247 view = address_space_get_flatview(as);
2248 FOR_EACH_FLAT_RANGE(fr, view) {
2249 if (fr->mr == mr) {
2250 flat_range_coalesced_io_notify(fr, as, cmr, add);
2251 }
2252 }
2253 flatview_unref(view);
0d673e36
AK
2254 }
2255}
2256
093bc2cd
AK
2257void memory_region_set_coalescing(MemoryRegion *mr)
2258{
2259 memory_region_clear_coalescing(mr);
08dafab4 2260 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2261}
2262
2263void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2264 hwaddr offset,
093bc2cd
AK
2265 uint64_t size)
2266{
7267c094 2267 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2268
08dafab4 2269 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd 2270 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
b960fc17 2271 memory_region_update_coalesced_range(mr, cmr, true);
d410515e 2272 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2273}
2274
2275void memory_region_clear_coalescing(MemoryRegion *mr)
2276{
2277 CoalescedMemoryRange *cmr;
9c1aa1c2
PX
2278
2279 if (QTAILQ_EMPTY(&mr->coalesced)) {
2280 return;
2281 }
093bc2cd 2282
d410515e
JK
2283 qemu_flush_coalesced_mmio_buffer();
2284 mr->flush_coalesced_mmio = false;
2285
093bc2cd
AK
2286 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2287 cmr = QTAILQ_FIRST(&mr->coalesced);
2288 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
b960fc17 2289 memory_region_update_coalesced_range(mr, cmr, false);
7267c094 2290 g_free(cmr);
ab5b3db5 2291 }
093bc2cd
AK
2292}
2293
d410515e
JK
2294void memory_region_set_flush_coalesced(MemoryRegion *mr)
2295{
2296 mr->flush_coalesced_mmio = true;
2297}
2298
2299void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2300{
2301 qemu_flush_coalesced_mmio_buffer();
2302 if (QTAILQ_EMPTY(&mr->coalesced)) {
2303 mr->flush_coalesced_mmio = false;
2304 }
2305}
2306
196ea131
JK
2307void memory_region_clear_global_locking(MemoryRegion *mr)
2308{
2309 mr->global_locking = false;
2310}
2311
8c56c1a5
PF
2312static bool userspace_eventfd_warning;
2313
3e9d69e7 2314void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2315 hwaddr addr,
3e9d69e7
AK
2316 unsigned size,
2317 bool match_data,
2318 uint64_t data,
753d5e14 2319 EventNotifier *e)
3e9d69e7
AK
2320{
2321 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2322 .addr.start = int128_make64(addr),
2323 .addr.size = int128_make64(size),
3e9d69e7
AK
2324 .match_data = match_data,
2325 .data = data,
753d5e14 2326 .e = e,
3e9d69e7
AK
2327 };
2328 unsigned i;
2329
8c56c1a5
PF
2330 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2331 userspace_eventfd_warning))) {
2332 userspace_eventfd_warning = true;
2333 error_report("Using eventfd without MMIO binding in KVM. "
2334 "Suboptimal performance expected");
2335 }
2336
b8aecea2 2337 if (size) {
9bf825bf 2338 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2339 }
59023ef4 2340 memory_region_transaction_begin();
3e9d69e7 2341 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2342 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2343 break;
2344 }
2345 }
2346 ++mr->ioeventfd_nb;
7267c094 2347 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2348 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2349 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2350 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2351 mr->ioeventfds[i] = mrfd;
4dc56152 2352 ioeventfd_update_pending |= mr->enabled;
59023ef4 2353 memory_region_transaction_commit();
3e9d69e7
AK
2354}
2355
2356void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2357 hwaddr addr,
3e9d69e7
AK
2358 unsigned size,
2359 bool match_data,
2360 uint64_t data,
753d5e14 2361 EventNotifier *e)
3e9d69e7
AK
2362{
2363 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2364 .addr.start = int128_make64(addr),
2365 .addr.size = int128_make64(size),
3e9d69e7
AK
2366 .match_data = match_data,
2367 .data = data,
753d5e14 2368 .e = e,
3e9d69e7
AK
2369 };
2370 unsigned i;
2371
b8aecea2 2372 if (size) {
9bf825bf 2373 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2374 }
59023ef4 2375 memory_region_transaction_begin();
3e9d69e7 2376 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2377 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2378 break;
2379 }
2380 }
2381 assert(i != mr->ioeventfd_nb);
2382 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2383 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2384 --mr->ioeventfd_nb;
7267c094 2385 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2386 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2387 ioeventfd_update_pending |= mr->enabled;
59023ef4 2388 memory_region_transaction_commit();
3e9d69e7
AK
2389}
2390
feca4ac1 2391static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2392{
feca4ac1 2393 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2394 MemoryRegion *other;
2395
59023ef4
JK
2396 memory_region_transaction_begin();
2397
dfde4e6e 2398 memory_region_ref(subregion);
093bc2cd
AK
2399 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2400 if (subregion->priority >= other->priority) {
2401 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2402 goto done;
2403 }
2404 }
2405 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2406done:
22bde714 2407 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2408 memory_region_transaction_commit();
093bc2cd
AK
2409}
2410
0598701a
PC
2411static void memory_region_add_subregion_common(MemoryRegion *mr,
2412 hwaddr offset,
2413 MemoryRegion *subregion)
2414{
feca4ac1
PB
2415 assert(!subregion->container);
2416 subregion->container = mr;
0598701a 2417 subregion->addr = offset;
feca4ac1 2418 memory_region_update_container_subregions(subregion);
0598701a 2419}
093bc2cd
AK
2420
2421void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2422 hwaddr offset,
093bc2cd
AK
2423 MemoryRegion *subregion)
2424{
093bc2cd
AK
2425 subregion->priority = 0;
2426 memory_region_add_subregion_common(mr, offset, subregion);
2427}
2428
2429void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2430 hwaddr offset,
093bc2cd 2431 MemoryRegion *subregion,
a1ff8ae0 2432 int priority)
093bc2cd 2433{
093bc2cd
AK
2434 subregion->priority = priority;
2435 memory_region_add_subregion_common(mr, offset, subregion);
2436}
2437
2438void memory_region_del_subregion(MemoryRegion *mr,
2439 MemoryRegion *subregion)
2440{
59023ef4 2441 memory_region_transaction_begin();
feca4ac1
PB
2442 assert(subregion->container == mr);
2443 subregion->container = NULL;
093bc2cd 2444 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2445 memory_region_unref(subregion);
22bde714 2446 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2447 memory_region_transaction_commit();
6bba19ba
AK
2448}
2449
2450void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2451{
2452 if (enabled == mr->enabled) {
2453 return;
2454 }
59023ef4 2455 memory_region_transaction_begin();
6bba19ba 2456 mr->enabled = enabled;
22bde714 2457 memory_region_update_pending = true;
59023ef4 2458 memory_region_transaction_commit();
093bc2cd 2459}
1c0ffa58 2460
e7af4c67
MT
2461void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2462{
2463 Int128 s = int128_make64(size);
2464
2465 if (size == UINT64_MAX) {
2466 s = int128_2_64();
2467 }
2468 if (int128_eq(s, mr->size)) {
2469 return;
2470 }
2471 memory_region_transaction_begin();
2472 mr->size = s;
2473 memory_region_update_pending = true;
2474 memory_region_transaction_commit();
2475}
2476
67891b8a 2477static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2478{
feca4ac1 2479 MemoryRegion *container = mr->container;
2282e1af 2480
feca4ac1 2481 if (container) {
67891b8a
PC
2482 memory_region_transaction_begin();
2483 memory_region_ref(mr);
feca4ac1
PB
2484 memory_region_del_subregion(container, mr);
2485 mr->container = container;
2486 memory_region_update_container_subregions(mr);
67891b8a
PC
2487 memory_region_unref(mr);
2488 memory_region_transaction_commit();
2282e1af 2489 }
67891b8a 2490}
2282e1af 2491
67891b8a
PC
2492void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2493{
2494 if (addr != mr->addr) {
2495 mr->addr = addr;
2496 memory_region_readd_subregion(mr);
2497 }
2282e1af
AK
2498}
2499
a8170e5e 2500void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2501{
4703359e 2502 assert(mr->alias);
4703359e 2503
59023ef4 2504 if (offset == mr->alias_offset) {
4703359e
AK
2505 return;
2506 }
2507
59023ef4
JK
2508 memory_region_transaction_begin();
2509 mr->alias_offset = offset;
22bde714 2510 memory_region_update_pending |= mr->enabled;
59023ef4 2511 memory_region_transaction_commit();
4703359e
AK
2512}
2513
a2b257d6
IM
2514uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2515{
2516 return mr->align;
2517}
2518
e2177955
AK
2519static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2520{
2521 const AddrRange *addr = addr_;
2522 const FlatRange *fr = fr_;
2523
2524 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2525 return -1;
2526 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2527 return 1;
2528 }
2529 return 0;
2530}
2531
99e86347 2532static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2533{
99e86347 2534 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2535 sizeof(FlatRange), cmp_flatrange_addr);
2536}
2537
eed2bacf
IM
2538bool memory_region_is_mapped(MemoryRegion *mr)
2539{
2540 return mr->container ? true : false;
2541}
2542
c6742b14
PB
2543/* Same as memory_region_find, but it does not add a reference to the
2544 * returned region. It must be called from an RCU critical section.
2545 */
2546static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2547 hwaddr addr, uint64_t size)
e2177955 2548{
052e87b0 2549 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2550 MemoryRegion *root;
2551 AddressSpace *as;
2552 AddrRange range;
99e86347 2553 FlatView *view;
73034e9e
PB
2554 FlatRange *fr;
2555
2556 addr += mr->addr;
feca4ac1
PB
2557 for (root = mr; root->container; ) {
2558 root = root->container;
73034e9e
PB
2559 addr += root->addr;
2560 }
e2177955 2561
73034e9e 2562 as = memory_region_to_address_space(root);
eed2bacf
IM
2563 if (!as) {
2564 return ret;
2565 }
73034e9e 2566 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2567
16620684 2568 view = address_space_to_flatview(as);
99e86347 2569 fr = flatview_lookup(view, range);
e2177955 2570 if (!fr) {
c6742b14 2571 return ret;
e2177955
AK
2572 }
2573
99e86347 2574 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2575 --fr;
2576 }
2577
2578 ret.mr = fr->mr;
16620684 2579 ret.fv = view;
e2177955
AK
2580 range = addrrange_intersection(range, fr->addr);
2581 ret.offset_within_region = fr->offset_in_region;
2582 ret.offset_within_region += int128_get64(int128_sub(range.start,
2583 fr->addr.start));
052e87b0 2584 ret.size = range.size;
e2177955 2585 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2586 ret.readonly = fr->readonly;
c26763f8 2587 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB
2588 return ret;
2589}
2590
2591MemoryRegionSection memory_region_find(MemoryRegion *mr,
2592 hwaddr addr, uint64_t size)
2593{
2594 MemoryRegionSection ret;
694ea274 2595 RCU_READ_LOCK_GUARD();
c6742b14
PB
2596 ret = memory_region_find_rcu(mr, addr, size);
2597 if (ret.mr) {
2598 memory_region_ref(ret.mr);
2599 }
e2177955
AK
2600 return ret;
2601}
2602
c6742b14
PB
2603bool memory_region_present(MemoryRegion *container, hwaddr addr)
2604{
2605 MemoryRegion *mr;
2606
694ea274 2607 RCU_READ_LOCK_GUARD();
c6742b14 2608 mr = memory_region_find_rcu(container, addr, 1).mr;
c6742b14
PB
2609 return mr && mr != container;
2610}
2611
9c1f8f44 2612void memory_global_dirty_log_sync(void)
86e775c6 2613{
3ebb1817 2614 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK
2615}
2616
9458a9a1
PB
2617void memory_global_after_dirty_log_sync(void)
2618{
2619 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2620}
2621
19310760
JZ
2622static VMChangeStateEntry *vmstate_change;
2623
7664e80c
AK
2624void memory_global_dirty_log_start(void)
2625{
19310760
JZ
2626 if (vmstate_change) {
2627 qemu_del_vm_change_state_handler(vmstate_change);
2628 vmstate_change = NULL;
2629 }
2630
7664e80c 2631 global_dirty_log = true;
6f6a5ef3 2632
7376e582 2633 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3 2634
39adb536 2635 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2636 memory_region_transaction_begin();
2637 memory_region_update_pending = true;
2638 memory_region_transaction_commit();
7664e80c
AK
2639}
2640
19310760 2641static void memory_global_dirty_log_do_stop(void)
7664e80c 2642{
7664e80c 2643 global_dirty_log = false;
6f6a5ef3 2644
39adb536 2645 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2646 memory_region_transaction_begin();
2647 memory_region_update_pending = true;
2648 memory_region_transaction_commit();
2649
7376e582 2650 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2651}
2652
19310760
JZ
2653static void memory_vm_change_state_handler(void *opaque, int running,
2654 RunState state)
2655{
2656 if (running) {
2657 memory_global_dirty_log_do_stop();
2658
2659 if (vmstate_change) {
2660 qemu_del_vm_change_state_handler(vmstate_change);
2661 vmstate_change = NULL;
2662 }
2663 }
2664}
2665
2666void memory_global_dirty_log_stop(void)
2667{
2668 if (!runstate_is_running()) {
2669 if (vmstate_change) {
2670 return;
2671 }
2672 vmstate_change = qemu_add_vm_change_state_handler(
2673 memory_vm_change_state_handler, NULL);
2674 return;
2675 }
2676
2677 memory_global_dirty_log_do_stop();
2678}
2679
7664e80c
AK
2680static void listener_add_address_space(MemoryListener *listener,
2681 AddressSpace *as)
2682{
99e86347 2683 FlatView *view;
7664e80c
AK
2684 FlatRange *fr;
2685
680a4783
PB
2686 if (listener->begin) {
2687 listener->begin(listener);
2688 }
7664e80c 2689 if (global_dirty_log) {
975aefe0
AK
2690 if (listener->log_global_start) {
2691 listener->log_global_start(listener);
2692 }
7664e80c 2693 }
975aefe0 2694
856d7245 2695 view = address_space_get_flatview(as);
99e86347 2696 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH
2697 MemoryRegionSection section = section_from_flat_range(fr, view);
2698
975aefe0
AK
2699 if (listener->region_add) {
2700 listener->region_add(listener, &section);
2701 }
ae990e6c
DH
2702 if (fr->dirty_log_mask && listener->log_start) {
2703 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2704 }
7664e80c 2705 }
680a4783
PB
2706 if (listener->commit) {
2707 listener->commit(listener);
2708 }
856d7245 2709 flatview_unref(view);
7664e80c
AK
2710}
2711
d25836ca
PX
2712static void listener_del_address_space(MemoryListener *listener,
2713 AddressSpace *as)
2714{
2715 FlatView *view;
2716 FlatRange *fr;
2717
2718 if (listener->begin) {
2719 listener->begin(listener);
2720 }
2721 view = address_space_get_flatview(as);
2722 FOR_EACH_FLAT_RANGE(fr, view) {
2723 MemoryRegionSection section = section_from_flat_range(fr, view);
2724
2725 if (fr->dirty_log_mask && listener->log_stop) {
2726 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2727 }
2728 if (listener->region_del) {
2729 listener->region_del(listener, &section);
2730 }
2731 }
2732 if (listener->commit) {
2733 listener->commit(listener);
2734 }
2735 flatview_unref(view);
2736}
2737
d45fa784 2738void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2739{
72e22d2f
AK
2740 MemoryListener *other = NULL;
2741
d45fa784 2742 listener->address_space = as;
72e22d2f 2743 if (QTAILQ_EMPTY(&memory_listeners)
eae3eb3e 2744 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
72e22d2f
AK
2745 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2746 } else {
2747 QTAILQ_FOREACH(other, &memory_listeners, link) {
2748 if (listener->priority < other->priority) {
2749 break;
2750 }
2751 }
2752 QTAILQ_INSERT_BEFORE(other, listener, link);
2753 }
0d673e36 2754
9a54635d 2755 if (QTAILQ_EMPTY(&as->listeners)
eae3eb3e 2756 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
9a54635d
PB
2757 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2758 } else {
2759 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2760 if (listener->priority < other->priority) {
2761 break;
2762 }
2763 }
2764 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2765 }
2766
d45fa784 2767 listener_add_address_space(listener, as);
7664e80c
AK
2768}
2769
2770void memory_listener_unregister(MemoryListener *listener)
2771{
1d8280c1
PB
2772 if (!listener->address_space) {
2773 return;
2774 }
2775
d25836ca 2776 listener_del_address_space(listener, listener->address_space);
72e22d2f 2777 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2778 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2779 listener->address_space = NULL;
86e775c6 2780}
e2177955 2781
a2166410
GK
2782void address_space_remove_listeners(AddressSpace *as)
2783{
2784 while (!QTAILQ_EMPTY(&as->listeners)) {
2785 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2786 }
2787}
2788
7dca8043 2789void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2790{
ac95190e 2791 memory_region_ref(root);
8786db7c 2792 as->root = root;
67ace39b 2793 as->current_map = NULL;
4c19eb72
AK
2794 as->ioeventfd_nb = 0;
2795 as->ioeventfds = NULL;
9a54635d 2796 QTAILQ_INIT(&as->listeners);
0d673e36 2797 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2798 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2799 address_space_update_topology(as);
2800 address_space_update_ioeventfds(as);
1c0ffa58 2801}
658b2224 2802
374f2981 2803static void do_address_space_destroy(AddressSpace *as)
83f3c251 2804{
9a54635d 2805 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2806
856d7245 2807 flatview_unref(as->current_map);
7dca8043 2808 g_free(as->name);
4c19eb72 2809 g_free(as->ioeventfds);
ac95190e 2810 memory_region_unref(as->root);
83f3c251
AK
2811}
2812
374f2981
PB
2813void address_space_destroy(AddressSpace *as)
2814{
ac95190e
PB
2815 MemoryRegion *root = as->root;
2816
374f2981
PB
2817 /* Flush out anything from MemoryListeners listening in on this */
2818 memory_region_transaction_begin();
2819 as->root = NULL;
2820 memory_region_transaction_commit();
2821 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2822
2823 /* At this point, as->dispatch and as->current_map are dummy
2824 * entries that the guest should never use. Wait for the old
2825 * values to expire before freeing the data.
2826 */
ac95190e 2827 as->root = root;
374f2981
PB
2828 call_rcu(as, do_address_space_destroy, rcu);
2829}
2830
4e831901
PX
2831static const char *memory_region_type(MemoryRegion *mr)
2832{
2833 if (memory_region_is_ram_device(mr)) {
2834 return "ramd";
2835 } else if (memory_region_is_romd(mr)) {
2836 return "romd";
2837 } else if (memory_region_is_rom(mr)) {
2838 return "rom";
2839 } else if (memory_region_is_ram(mr)) {
2840 return "ram";
2841 } else {
2842 return "i/o";
2843 }
2844}
2845
314e2987
BS
2846typedef struct MemoryRegionList MemoryRegionList;
2847
2848struct MemoryRegionList {
2849 const MemoryRegion *mr;
a16878d2 2850 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2851};
2852
b58deb34 2853typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
314e2987 2854
4e831901
PX
2855#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2856 int128_sub((size), int128_one())) : 0)
2857#define MTREE_INDENT " "
2858
b6b71cb5 2859static void mtree_expand_owner(const char *label, Object *obj)
fc051ae6
AK
2860{
2861 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2862
b6b71cb5 2863 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
fc051ae6 2864 if (dev && dev->id) {
b6b71cb5 2865 qemu_printf(" id=%s", dev->id);
fc051ae6
AK
2866 } else {
2867 gchar *canonical_path = object_get_canonical_path(obj);
2868 if (canonical_path) {
b6b71cb5 2869 qemu_printf(" path=%s", canonical_path);
fc051ae6
AK
2870 g_free(canonical_path);
2871 } else {
b6b71cb5 2872 qemu_printf(" type=%s", object_get_typename(obj));
fc051ae6
AK
2873 }
2874 }
b6b71cb5 2875 qemu_printf("}");
fc051ae6
AK
2876}
2877
b6b71cb5 2878static void mtree_print_mr_owner(const MemoryRegion *mr)
fc051ae6
AK
2879{
2880 Object *owner = mr->owner;
2881 Object *parent = memory_region_owner((MemoryRegion *)mr);
2882
2883 if (!owner && !parent) {
b6b71cb5 2884 qemu_printf(" orphan");
fc051ae6
AK
2885 return;
2886 }
2887 if (owner) {
b6b71cb5 2888 mtree_expand_owner("owner", owner);
fc051ae6
AK
2889 }
2890 if (parent && parent != owner) {
b6b71cb5 2891 mtree_expand_owner("parent", parent);
fc051ae6
AK
2892 }
2893}
2894
b6b71cb5 2895static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
a8170e5e 2896 hwaddr base,
fc051ae6
AK
2897 MemoryRegionListHead *alias_print_queue,
2898 bool owner)
314e2987 2899{
9479c57a
JK
2900 MemoryRegionList *new_ml, *ml, *next_ml;
2901 MemoryRegionListHead submr_print_queue;
314e2987
BS
2902 const MemoryRegion *submr;
2903 unsigned int i;
b31f8412 2904 hwaddr cur_start, cur_end;
314e2987 2905
f8a9f720 2906 if (!mr) {
314e2987
BS
2907 return;
2908 }
2909
2910 for (i = 0; i < level; i++) {
b6b71cb5 2911 qemu_printf(MTREE_INDENT);
314e2987
BS
2912 }
2913
b31f8412
PX
2914 cur_start = base + mr->addr;
2915 cur_end = cur_start + MR_SIZE(mr->size);
2916
2917 /*
2918 * Try to detect overflow of memory region. This should never
2919 * happen normally. When it happens, we dump something to warn the
2920 * user who is observing this.
2921 */
2922 if (cur_start < base || cur_end < cur_start) {
b6b71cb5 2923 qemu_printf("[DETECTED OVERFLOW!] ");
b31f8412
PX
2924 }
2925
314e2987
BS
2926 if (mr->alias) {
2927 MemoryRegionList *ml;
2928 bool found = false;
2929
2930 /* check if the alias is already in the queue */
a16878d2 2931 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2932 if (ml->mr == mr->alias) {
314e2987
BS
2933 found = true;
2934 }
2935 }
2936
2937 if (!found) {
2938 ml = g_new(MemoryRegionList, 1);
2939 ml->mr = mr->alias;
a16878d2 2940 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2941 }
b6b71cb5
MA
2942 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2943 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2944 "-" TARGET_FMT_plx "%s",
2945 cur_start, cur_end,
2946 mr->priority,
2947 mr->nonvolatile ? "nv-" : "",
2948 memory_region_type((MemoryRegion *)mr),
2949 memory_region_name(mr),
2950 memory_region_name(mr->alias),
2951 mr->alias_offset,
2952 mr->alias_offset + MR_SIZE(mr->size),
2953 mr->enabled ? "" : " [disabled]");
fc051ae6 2954 if (owner) {
b6b71cb5 2955 mtree_print_mr_owner(mr);
fc051ae6 2956 }
314e2987 2957 } else {
b6b71cb5
MA
2958 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2959 " (prio %d, %s%s): %s%s",
2960 cur_start, cur_end,
2961 mr->priority,
2962 mr->nonvolatile ? "nv-" : "",
2963 memory_region_type((MemoryRegion *)mr),
2964 memory_region_name(mr),
2965 mr->enabled ? "" : " [disabled]");
fc051ae6 2966 if (owner) {
b6b71cb5 2967 mtree_print_mr_owner(mr);
fc051ae6 2968 }
314e2987 2969 }
b6b71cb5 2970 qemu_printf("\n");
9479c57a
JK
2971
2972 QTAILQ_INIT(&submr_print_queue);
2973
314e2987 2974 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2975 new_ml = g_new(MemoryRegionList, 1);
2976 new_ml->mr = submr;
a16878d2 2977 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2978 if (new_ml->mr->addr < ml->mr->addr ||
2979 (new_ml->mr->addr == ml->mr->addr &&
2980 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2981 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2982 new_ml = NULL;
2983 break;
2984 }
2985 }
2986 if (new_ml) {
a16878d2 2987 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2988 }
2989 }
2990
a16878d2 2991 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b6b71cb5 2992 mtree_print_mr(ml->mr, level + 1, cur_start,
fc051ae6 2993 alias_print_queue, owner);
9479c57a
JK
2994 }
2995
a16878d2 2996 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2997 g_free(ml);
314e2987
BS
2998 }
2999}
3000
5e8fd947 3001struct FlatViewInfo {
5e8fd947
AK
3002 int counter;
3003 bool dispatch_tree;
fc051ae6 3004 bool owner;
8072aae3 3005 AccelClass *ac;
5e8fd947
AK
3006};
3007
3008static void mtree_print_flatview(gpointer key, gpointer value,
3009 gpointer user_data)
57bb40c9 3010{
5e8fd947
AK
3011 FlatView *view = key;
3012 GArray *fv_address_spaces = value;
3013 struct FlatViewInfo *fvi = user_data;
57bb40c9
PX
3014 FlatRange *range = &view->ranges[0];
3015 MemoryRegion *mr;
3016 int n = view->nr;
5e8fd947
AK
3017 int i;
3018 AddressSpace *as;
3019
b6b71cb5 3020 qemu_printf("FlatView #%d\n", fvi->counter);
5e8fd947
AK
3021 ++fvi->counter;
3022
3023 for (i = 0; i < fv_address_spaces->len; ++i) {
3024 as = g_array_index(fv_address_spaces, AddressSpace*, i);
b6b71cb5
MA
3025 qemu_printf(" AS \"%s\", root: %s",
3026 as->name, memory_region_name(as->root));
5e8fd947 3027 if (as->root->alias) {
b6b71cb5 3028 qemu_printf(", alias %s", memory_region_name(as->root->alias));
5e8fd947 3029 }
b6b71cb5 3030 qemu_printf("\n");
5e8fd947
AK
3031 }
3032
b6b71cb5 3033 qemu_printf(" Root memory region: %s\n",
5e8fd947 3034 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
3035
3036 if (n <= 0) {
b6b71cb5 3037 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
3038 return;
3039 }
3040
3041 while (n--) {
3042 mr = range->mr;
377a07aa 3043 if (range->offset_in_region) {
b6b71cb5
MA
3044 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3045 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3046 int128_get64(range->addr.start),
3047 int128_get64(range->addr.start)
3048 + MR_SIZE(range->addr.size),
3049 mr->priority,
3050 range->nonvolatile ? "nv-" : "",
3051 range->readonly ? "rom" : memory_region_type(mr),
3052 memory_region_name(mr),
3053 range->offset_in_region);
377a07aa 3054 } else {
b6b71cb5
MA
3055 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3056 " (prio %d, %s%s): %s",
3057 int128_get64(range->addr.start),
3058 int128_get64(range->addr.start)
3059 + MR_SIZE(range->addr.size),
3060 mr->priority,
3061 range->nonvolatile ? "nv-" : "",
3062 range->readonly ? "rom" : memory_region_type(mr),
3063 memory_region_name(mr));
377a07aa 3064 }
fc051ae6 3065 if (fvi->owner) {
b6b71cb5 3066 mtree_print_mr_owner(mr);
fc051ae6 3067 }
8072aae3
AK
3068
3069 if (fvi->ac) {
3070 for (i = 0; i < fv_address_spaces->len; ++i) {
3071 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3072 if (fvi->ac->has_memory(current_machine, as,
3073 int128_get64(range->addr.start),
3074 MR_SIZE(range->addr.size) + 1)) {
53b62bec 3075 qemu_printf(" %s", fvi->ac->name);
8072aae3
AK
3076 }
3077 }
3078 }
b6b71cb5 3079 qemu_printf("\n");
57bb40c9
PX
3080 range++;
3081 }
3082
5e8fd947
AK
3083#if !defined(CONFIG_USER_ONLY)
3084 if (fvi->dispatch_tree && view->root) {
b6b71cb5 3085 mtree_print_dispatch(view->dispatch, view->root);
5e8fd947
AK
3086 }
3087#endif
3088
b6b71cb5 3089 qemu_printf("\n");
5e8fd947
AK
3090}
3091
3092static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3093 gpointer user_data)
3094{
3095 FlatView *view = key;
3096 GArray *fv_address_spaces = value;
3097
3098 g_array_unref(fv_address_spaces);
57bb40c9 3099 flatview_unref(view);
5e8fd947
AK
3100
3101 return true;
57bb40c9
PX
3102}
3103
b6b71cb5 3104void mtree_info(bool flatview, bool dispatch_tree, bool owner)
314e2987
BS
3105{
3106 MemoryRegionListHead ml_head;
3107 MemoryRegionList *ml, *ml2;
0d673e36 3108 AddressSpace *as;
314e2987 3109
57bb40c9 3110 if (flatview) {
5e8fd947
AK
3111 FlatView *view;
3112 struct FlatViewInfo fvi = {
5e8fd947 3113 .counter = 0,
fc051ae6
AK
3114 .dispatch_tree = dispatch_tree,
3115 .owner = owner,
5e8fd947
AK
3116 };
3117 GArray *fv_address_spaces;
3118 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
4f7f5893 3119 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
8072aae3
AK
3120
3121 if (ac->has_memory) {
3122 fvi.ac = ac;
8072aae3 3123 }
5e8fd947
AK
3124
3125 /* Gather all FVs in one table */
57bb40c9 3126 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3127 view = address_space_get_flatview(as);
3128
3129 fv_address_spaces = g_hash_table_lookup(views, view);
3130 if (!fv_address_spaces) {
3131 fv_address_spaces = g_array_new(false, false, sizeof(as));
3132 g_hash_table_insert(views, view, fv_address_spaces);
3133 }
3134
3135 g_array_append_val(fv_address_spaces, as);
57bb40c9 3136 }
5e8fd947
AK
3137
3138 /* Print */
3139 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3140
3141 /* Free */
3142 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3143 g_hash_table_unref(views);
3144
57bb40c9
PX
3145 return;
3146 }
3147
314e2987
BS
3148 QTAILQ_INIT(&ml_head);
3149
0d673e36 3150 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b6b71cb5
MA
3151 qemu_printf("address-space: %s\n", as->name);
3152 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3153 qemu_printf("\n");
b9f9be88
BS
3154 }
3155
314e2987 3156 /* print aliased regions */
a16878d2 3157 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
b6b71cb5
MA
3158 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3159 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3160 qemu_printf("\n");
314e2987
BS
3161 }
3162
a16878d2 3163 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3164 g_free(ml);
314e2987 3165 }
314e2987 3166}
b4fefef9 3167
b08199c6
PM
3168void memory_region_init_ram(MemoryRegion *mr,
3169 struct Object *owner,
3170 const char *name,
3171 uint64_t size,
3172 Error **errp)
3173{
3174 DeviceState *owner_dev;
3175 Error *err = NULL;
3176
3177 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3178 if (err) {
3179 error_propagate(errp, err);
3180 return;
3181 }
3182 /* This will assert if owner is neither NULL nor a DeviceState.
3183 * We only want the owner here for the purposes of defining a
3184 * unique name for migration. TODO: Ideally we should implement
3185 * a naming scheme for Objects which are not DeviceStates, in
3186 * which case we can relax this restriction.
3187 */
3188 owner_dev = DEVICE(owner);
3189 vmstate_register_ram(mr, owner_dev);
3190}
3191
3192void memory_region_init_rom(MemoryRegion *mr,
3193 struct Object *owner,
3194 const char *name,
3195 uint64_t size,
3196 Error **errp)
3197{
3198 DeviceState *owner_dev;
3199 Error *err = NULL;
3200
3201 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3202 if (err) {
3203 error_propagate(errp, err);
3204 return;
3205 }
3206 /* This will assert if owner is neither NULL nor a DeviceState.
3207 * We only want the owner here for the purposes of defining a
3208 * unique name for migration. TODO: Ideally we should implement
3209 * a naming scheme for Objects which are not DeviceStates, in
3210 * which case we can relax this restriction.
3211 */
3212 owner_dev = DEVICE(owner);
3213 vmstate_register_ram(mr, owner_dev);
3214}
3215
3216void memory_region_init_rom_device(MemoryRegion *mr,
3217 struct Object *owner,
3218 const MemoryRegionOps *ops,
3219 void *opaque,
3220 const char *name,
3221 uint64_t size,
3222 Error **errp)
3223{
3224 DeviceState *owner_dev;
3225 Error *err = NULL;
3226
3227 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3228 name, size, &err);
3229 if (err) {
3230 error_propagate(errp, err);
3231 return;
3232 }
3233 /* This will assert if owner is neither NULL nor a DeviceState.
3234 * We only want the owner here for the purposes of defining a
3235 * unique name for migration. TODO: Ideally we should implement
3236 * a naming scheme for Objects which are not DeviceStates, in
3237 * which case we can relax this restriction.
3238 */
3239 owner_dev = DEVICE(owner);
3240 vmstate_register_ram(mr, owner_dev);
3241}
3242
b4fefef9
PC
3243static const TypeInfo memory_region_info = {
3244 .parent = TYPE_OBJECT,
3245 .name = TYPE_MEMORY_REGION,
1b53ecd9 3246 .class_size = sizeof(MemoryRegionClass),
b4fefef9
PC
3247 .instance_size = sizeof(MemoryRegion),
3248 .instance_init = memory_region_initfn,
3249 .instance_finalize = memory_region_finalize,
3250};
3251
3df9d748
AK
3252static const TypeInfo iommu_memory_region_info = {
3253 .parent = TYPE_MEMORY_REGION,
3254 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3255 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3256 .instance_size = sizeof(IOMMUMemoryRegion),
3257 .instance_init = iommu_memory_region_initfn,
1221a474 3258 .abstract = true,
3df9d748
AK
3259};
3260
b4fefef9
PC
3261static void memory_register_types(void)
3262{
3263 type_register_static(&memory_region_info);
3df9d748 3264 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3265}
3266
3267type_init(memory_register_types)