projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| cf959c7d SR |
1 | /* |
| 2 | * (C) Copyright 2007 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #include <common.h> | |
| 25 | #include <ppc4xx.h> | |
| 26 | #include <asm/processor.h> | |
| 27 | #include <asm/io.h> | |
| 28 | ||
| 29 | static void wait_init_complete(void) | |
| 30 | { | |
| 31 | u32 val; | |
| 32 | ||
| 33 | do { | |
| 34 | mfsdram(mem_mcsts, val); | |
| 35 | } while (!(val & 0x80000000)); | |
| 36 | } | |
| 37 | ||
| 38 | /* | |
| 9973e3c6 | 39 | * phys_size_t initdram(int board_type) |
| cf959c7d SR |
40 | * |
| 41 | * As the name already indicates, this function is called very early | |
| 42 | * from start.S and configures the SDRAM with fixed values. This is needed, | |
| 43 | * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has | |
| 44 | * not enough free space to implement the complete I2C SPD DDR autodetection | |
| 45 | * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM | |
| 46 | * when booting from NAND flash. | |
| 9f798766 EB |
47 | * |
| 48 | * Note: | |
| 49 | * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed | |
| 50 | * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM | |
| 51 | * modules are still plugged in. So it is recommended to remove the DIMM | |
| 52 | * modules while using the NAND booting code with the fixed SDRAM setup! | |
| cf959c7d | 53 | */ |
| 9973e3c6 | 54 | phys_size_t initdram(int board_type) |
| cf959c7d SR |
55 | { |
| 56 | /* | |
| 57 | * Soft-reset SDRAM controller. | |
| 58 | */ | |
| 59 | mtsdr(sdr_srst, SDR0_SRST_DMC); | |
| 60 | mtsdr(sdr_srst, 0x00000000); | |
| 61 | ||
| 62 | /* | |
| 63 | * Disable memory controller. | |
| 64 | */ | |
| 65 | mtsdram(mem_cfg0, 0x00000000); | |
| 66 | ||
| 67 | /* | |
| 68 | * Setup some default | |
| 69 | */ | |
| 70 | mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ | |
| 71 | mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ | |
| 72 | mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ | |
| 73 | mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ | |
| 74 | mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ | |
| 75 | ||
| 76 | /* | |
| 77 | * Following for CAS Latency = 2.5 @ 133 MHz PLB | |
| 78 | */ | |
| 79 | mtsdram(mem_b0cr, 0x00082001); | |
| 80 | mtsdram(mem_tr0, 0x41094012); | |
| 81 | mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ | |
| 82 |