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Commit | Line | Data |
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887e2ec9 | 1 | /* |
46f37383 | 2 | * (C) Copyright 2006-2008 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
22 | #include <nand.h> | |
23 | ||
24 | #define CFG_NAND_READ_DELAY \ | |
25 | { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; } | |
26 | ||
42be56f5 SR |
27 | static int nand_ecc_pos[] = CFG_NAND_ECCPOS; |
28 | ||
887e2ec9 | 29 | extern void board_nand_init(struct nand_chip *nand); |
887e2ec9 | 30 | |
46f37383 SR |
31 | #if (CFG_NAND_PAGE_SIZE <= 512) |
32 | /* | |
33 | * NAND command for small page NAND devices (512) | |
34 | */ | |
42be56f5 | 35 | static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) |
887e2ec9 | 36 | { |
511d0c72 | 37 | struct nand_chip *this = mtd->priv; |
42be56f5 SR |
38 | int page_addr = page + block * CFG_NAND_PAGE_COUNT; |
39 | ||
40 | if (this->dev_ready) | |
41 | this->dev_ready(mtd); | |
42 | else | |
43 | CFG_NAND_READ_DELAY; | |
887e2ec9 SR |
44 | |
45 | /* Begin command latch cycle */ | |
46 | this->hwcontrol(mtd, NAND_CTL_SETCLE); | |
42be56f5 | 47 | this->write_byte(mtd, cmd); |
887e2ec9 SR |
48 | /* Set ALE and clear CLE to start address cycle */ |
49 | this->hwcontrol(mtd, NAND_CTL_CLRCLE); | |
50 | this->hwcontrol(mtd, NAND_CTL_SETALE); | |
51 | /* Column address */ | |
42be56f5 | 52 | this->write_byte(mtd, offs); /* A[7:0] */ |
887e2ec9 SR |
53 | this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ |
54 | this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ | |
55 | #ifdef CFG_NAND_4_ADDR_CYCLE | |
56 | /* One more address cycle for devices > 32MiB */ | |
57 | this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ | |
58 | #endif | |
59 | /* Latch in address */ | |
60 | this->hwcontrol(mtd, NAND_CTL_CLRALE); | |
61 | ||
62 | /* | |
63 | * Wait a while for the data to be ready | |
64 | */ | |
65 | if (this->dev_ready) | |
66 | this->dev_ready(mtd); | |
67 | else | |
68 | CFG_NAND_READ_DELAY; | |
69 | ||
42be56f5 SR |
70 | return 0; |
71 | } | |
46f37383 SR |
72 | #else |
73 | /* | |
74 | * NAND command for large page NAND devices (2k) | |
75 | */ | |
76 | static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) | |
77 | { | |
78 | struct nand_chip *this = mtd->priv; | |
79 | int page_offs = offs; | |
80 | int page_addr = page + block * CFG_NAND_PAGE_COUNT; | |
81 | ||
82 | if (this->dev_ready) | |
83 | this->dev_ready(mtd); | |
84 | else | |
85 | CFG_NAND_READ_DELAY; | |
86 | ||
87 | /* Emulate NAND_CMD_READOOB */ | |
88 | if (cmd == NAND_CMD_READOOB) { | |
89 | page_offs += CFG_NAND_PAGE_SIZE; | |
90 | cmd = NAND_CMD_READ0; | |
91 | } | |
92 | ||
93 | /* Begin command latch cycle */ | |
94 | this->hwcontrol(mtd, NAND_CTL_SETCLE); | |
95 | this->write_byte(mtd, cmd); | |
96 | /* Set ALE and clear CLE to start address cycle */ | |
97 | this->hwcontrol(mtd, NAND_CTL_CLRCLE); | |
98 | this->hwcontrol(mtd, NAND_CTL_SETALE); | |
99 | /* Column address */ | |
100 | this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */ | |
101 | this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */ | |
102 | /* Row address */ | |
103 | this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */ | |
104 | this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */ | |
105 | #ifdef CFG_NAND_5_ADDR_CYCLE | |
106 | /* One more address cycle for devices > 128MiB */ | |
107 | this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */ | |
108 | #endif | |
109 | /* Latch in address */ | |
110 | this->hwcontrol(mtd, NAND_CTL_CLRALE); | |
111 | ||
112 | /* Begin command latch cycle */ | |
113 | this->hwcontrol(mtd, NAND_CTL_SETCLE); | |
114 | /* Write out the start read command */ | |
115 | this->write_byte(mtd, NAND_CMD_READSTART); | |
116 | /* End command latch cycle */ | |
117 | this->hwcontrol(mtd, NAND_CTL_CLRCLE); | |
118 | ||
119 | /* | |
120 | * Wait a while for the data to be ready | |
121 | */ | |
122 | if (this->dev_ready) | |
123 | this->dev_ready(mtd); | |
124 | else | |
125 | CFG_NAND_READ_DELAY; | |
126 | ||
127 | return 0; | |
128 | } | |
129 | #endif | |
42be56f5 SR |
130 | |
131 | static int nand_is_bad_block(struct mtd_info *mtd, int block) | |
132 | { | |
133 | struct nand_chip *this = mtd->priv; | |
134 | ||
135 | nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); | |
136 | ||
887e2ec9 | 137 | /* |
10c7382b | 138 | * Read one byte |
887e2ec9 SR |
139 | */ |
140 | if (this->read_byte(mtd) != 0xff) | |
141 | return 1; | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) | |
147 | { | |
511d0c72 | 148 | struct nand_chip *this = mtd->priv; |
42be56f5 SR |
149 | u_char *ecc_calc; |
150 | u_char *ecc_code; | |
151 | u_char *oob_data; | |
887e2ec9 | 152 | int i; |
42be56f5 SR |
153 | int eccsize = CFG_NAND_ECCSIZE; |
154 | int eccbytes = CFG_NAND_ECCBYTES; | |
155 | int eccsteps = CFG_NAND_ECCSTEPS; | |
156 | uint8_t *p = dst; | |
157 | int stat; | |
887e2ec9 | 158 | |
42be56f5 | 159 | nand_command(mtd, block, page, 0, NAND_CMD_READ0); |
887e2ec9 | 160 | |
42be56f5 SR |
161 | /* No malloc available for now, just use some temporary locations |
162 | * in SDRAM | |
887e2ec9 | 163 | */ |
42be56f5 SR |
164 | ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000); |
165 | ecc_code = ecc_calc + 0x100; | |
166 | oob_data = ecc_calc + 0x200; | |
167 | ||
168 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
169 | this->enable_hwecc(mtd, NAND_ECC_READ); | |
170 | this->read_buf(mtd, p, eccsize); | |
171 | this->calculate_ecc(mtd, p, &ecc_calc[i]); | |
172 | } | |
173 | this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE); | |
174 | ||
175 | /* Pick the ECC bytes out of the oob data */ | |
176 | for (i = 0; i < CFG_NAND_ECCTOTAL; i++) | |
177 | ecc_code[i] = oob_data[nand_ecc_pos[i]]; | |
178 | ||
179 | eccsteps = CFG_NAND_ECCSTEPS; | |
180 | p = dst; | |
181 | ||
182 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
183 | /* No chance to do something with the possible error message | |
184 | * from correct_data(). We just hope that all possible errors | |
185 | * are corrected by this routine. | |
186 | */ | |
187 | stat = this->correct_data(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
188 | } | |
887e2ec9 SR |
189 | |
190 | return 0; | |
191 | } | |
192 | ||
193 | static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) | |
194 | { | |
195 | int block; | |
196 | int blockcopy_count; | |
197 | int page; | |
198 | ||
199 | /* | |
200 | * offs has to be aligned to a block address! | |
201 | */ | |
202 | block = offs / CFG_NAND_BLOCK_SIZE; | |
203 | blockcopy_count = 0; | |
204 | ||
205 | while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) { | |
206 | if (!nand_is_bad_block(mtd, block)) { | |
207 | /* | |
208 | * Skip bad blocks | |
209 | */ | |
210 | for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) { | |
211 | nand_read_page(mtd, block, page, dst); | |
212 | dst += CFG_NAND_PAGE_SIZE; | |
213 | } | |
214 | ||
215 | blockcopy_count++; | |
216 | } | |
217 | ||
218 | block++; | |
219 | } | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
224 | void nand_boot(void) | |
225 | { | |
226 | ulong mem_size; | |
227 | struct nand_chip nand_chip; | |
228 | nand_info_t nand_info; | |
229 | int ret; | |
230 | void (*uboot)(void); | |
231 | ||
232 | /* | |
233 | * Init sdram, so we have access to memory | |
234 | */ | |
235 | mem_size = initdram(0); | |
236 | ||
237 | /* | |
238 | * Init board specific nand support | |
239 | */ | |
240 | nand_info.priv = &nand_chip; | |
241 | nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE; | |
242 | nand_chip.dev_ready = NULL; /* preset to NULL */ | |
243 | board_nand_init(&nand_chip); | |
244 | ||
245 | /* | |
246 | * Load U-Boot image from NAND into RAM | |
247 | */ | |
d12ae808 | 248 | ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, |
887e2ec9 SR |
249 | (uchar *)CFG_NAND_U_BOOT_DST); |
250 | ||
251 | /* | |
252 | * Jump to U-Boot image | |
253 | */ | |
254 | uboot = (void (*)(void))CFG_NAND_U_BOOT_START; | |
255 | (*uboot)(); | |
256 | } |