[people/ms/u-boot.git] / nand_spl / nand_boot_fsl_elbc.c

/*
 * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
 *
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * Copyright (c) 2008 Freescale Semiconductor, Inc.
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/fsl_lbc.h>
#include <linux/mtd/nand.h>

#define WINDOW_SIZE 8192

static void nand_wait(void)
{
	fsl_lbc_t *regs = LBC_BASE_ADDR;

	for (;;) {
		uint32_t status = in_be32(&regs->ltesr);

		if (status == 1)
			return;

		if (status & 1) {
			puts("read failed (ltesr)\n");
			for (;;);
		}
	}
}

static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
	fsl_lbc_t *regs = LBC_BASE_ADDR;
	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
	const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
	const int block_shift = large ? 17 : 14;
	const int block_size = 1 << block_shift;
	const int page_size = large ? 2048 : 512;
	const int bad_marker = large ? page_size + 0 : page_size + 5;
	int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
	int pos = 0;

	if (offs & (block_size - 1)) {
		puts("bad offset\n");
		for (;;);
	}

	if (large) {
		fmr |= FMR_ECCM;
		__raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
			(NAND_CMD_READSTART << FCR_CMD1_SHIFT),
			&regs->fcr);
		__raw_writel(
			(FIR_OP_CW0 << FIR_OP0_SHIFT) |
			(FIR_OP_CA  << FIR_OP1_SHIFT) |
			(FIR_OP_PA  << FIR_OP2_SHIFT) |
			(FIR_OP_CW1 << FIR_OP3_SHIFT) |
			(FIR_OP_RBW << FIR_OP4_SHIFT),
			&regs->fir);
	} else {
		__raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, &regs->fcr);
		__raw_writel(
			(FIR_OP_CW0 << FIR_OP0_SHIFT) |
			(FIR_OP_CA  << FIR_OP1_SHIFT) |
			(FIR_OP_PA  << FIR_OP2_SHIFT) |
			(FIR_OP_RBW << FIR_OP3_SHIFT),
			&regs->fir);
	}

	__raw_writel(0, &regs->fbcr);

	while (pos < uboot_size) {
		int i = 0;
		__raw_writel(offs >> block_shift, &regs->fbar);

		do {
			int j;
			unsigned int page_offs = (offs & (block_size - 1)) << 1;

			__raw_writel(~0, &regs->ltesr);
			__raw_writel(0, &regs->lteatr);
			__raw_writel(page_offs, &regs->fpar);
			__raw_writel(fmr, &regs->fmr);
			sync();
			__raw_writel(0, &regs->lsor);
			nand_wait();

			page_offs %= WINDOW_SIZE;

			/*
			 * If either of the first two pages are marked bad,
			 * continue to the next block.
			 */
			if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
				puts("skipping\n");
				offs = (offs + block_size) & ~(block_size - 1);
				pos &= ~(block_size - 1);
				break;
			}

			for (j = 0; j < page_size; j++)
				dst[pos + j] = buf[page_offs + j];

			pos += page_size;
			offs += page_size;
		} while ((offs & (block_size - 1)) && (pos < uboot_size));
	}
}

/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	__attribute__((noreturn)) void (*uboot)(void);

	/*
	 * Load U-Boot image from NAND into RAM
	 */
	nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
	          (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);

	/*
	 * Jump to U-Boot image
	 */
	puts("transfering control\n");
	/*
	 * Clean d-cache and invalidate i-cache, to
	 * make sure that no stale data is executed.
	 */
	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
	uboot();
}
Commit	Line	Data
e4c09508 SW	1	/*
	2	* NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
	3	*
	4	* (C) Copyright 2006-2008
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
	7	* Copyright (c) 2008 Freescale Semiconductor, Inc.
	8	* Author: Scott Wood <scottwood@freescale.com>
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/io.h>
e4c09508 SW	28	#include <asm/fsl_lbc.h>
	29	#include <linux/mtd/nand.h>
	30
	31	#define WINDOW_SIZE 8192
	32
	33	static void nand_wait(void)
	34	{
f51cdaf1	35	fsl_lbc_t *regs = LBC_BASE_ADDR;
e4c09508 SW	36
	37	for (;;) {
	38	uint32_t status = in_be32(&regs->ltesr);
	39
	40	if (status == 1)
	41	return;
	42
	43	if (status & 1) {
	44	puts("read failed (ltesr)\n");
	45	for (;;);
	46	}
	47	}
	48	}
	49
	50	static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
	51	{
f51cdaf1	52	fsl_lbc_t *regs = LBC_BASE_ADDR;
6d0f6bcf	53	uchar buf = (uchar )CONFIG_SYS_NAND_BASE;
62974546 MM	54	const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
	55	const int block_shift = large ? 17 : 14;
	56	const int block_size = 1 << block_shift;
	57	const int page_size = large ? 2048 : 512;
	58	const int bad_marker = large ? page_size + 0 : page_size + 5;
e4c09508 SW	59	int fmr = (15 << FMR_CWTO_SHIFT) \| (2 << FMR_AL_SHIFT) \| 2;
	60	int pos = 0;
	61
	62	if (offs & (block_size - 1)) {
	63	puts("bad offset\n");
	64	for (;;);
	65	}
	66
	67	if (large) {
	68	fmr \|= FMR_ECCM;
7b8f6685 SW	69	__raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) \|
	70	(NAND_CMD_READSTART << FCR_CMD1_SHIFT),
	71	&regs->fcr);
	72	__raw_writel(
	73	(FIR_OP_CW0 << FIR_OP0_SHIFT) \|
	74	(FIR_OP_CA << FIR_OP1_SHIFT) \|
	75	(FIR_OP_PA << FIR_OP2_SHIFT) \|
	76	(FIR_OP_CW1 << FIR_OP3_SHIFT) \|
	77	(FIR_OP_RBW << FIR_OP4_SHIFT),
	78	&regs->fir);
e4c09508	79	} else {
7b8f6685 SW	80	__raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, &regs->fcr);
	81	__raw_writel(
	82	(FIR_OP_CW0 << FIR_OP0_SHIFT) \|
	83	(FIR_OP_CA << FIR_OP1_SHIFT) \|
	84	(FIR_OP_PA << FIR_OP2_SHIFT) \|
	85	(FIR_OP_RBW << FIR_OP3_SHIFT),
	86	&regs->fir);
e4c09508 SW	87	}
e4c09508 SW	88
7b8f6685	89	__raw_writel(0, &regs->fbcr);
e4c09508 SW	90
	91	while (pos < uboot_size) {
	92	int i = 0;
7b8f6685	93	__raw_writel(offs >> block_shift, &regs->fbar);
e4c09508 SW	94
	95	do {
	96	int j;
	97	unsigned int page_offs = (offs & (block_size - 1)) << 1;
	98
7b8f6685 SW	99	__raw_writel(~0, &regs->ltesr);
	100	__raw_writel(0, &regs->lteatr);
	101	__raw_writel(page_offs, &regs->fpar);
	102	__raw_writel(fmr, &regs->fmr);
	103	sync();
	104	__raw_writel(0, &regs->lsor);
e4c09508 SW	105	nand_wait();
	106
	107	page_offs %= WINDOW_SIZE;
	108
	109	/*
	110	* If either of the first two pages are marked bad,
	111	* continue to the next block.
	112	*/
	113	if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
	114	puts("skipping\n");
	115	offs = (offs + block_size) & ~(block_size - 1);
	116	pos &= ~(block_size - 1);
	117	break;
	118	}
	119
	120	for (j = 0; j < page_size; j++)
	121	dst[pos + j] = buf[page_offs + j];
	122
	123	pos += page_size;
	124	offs += page_size;
269610f6	125	} while ((offs & (block_size - 1)) && (pos < uboot_size));
e4c09508 SW	126	}
	127	}
	128
	129	/*
	130	* The main entry for NAND booting. It's necessary that SDRAM is already
	131	* configured and available since this code loads the main U-Boot image
	132	* from NAND into SDRAM and starts it from there.
	133	*/
	134	void nand_boot(void)
	135	{
	136	__attribute__((noreturn)) void (*uboot)(void);
	137
e4c09508 SW	138	/*
	139	* Load U-Boot image from NAND into RAM
	140	*/
6d0f6bcf JCPV	141	nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
6d0f6bcf JCPV	142	(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
e4c09508 SW	143
	144	/*
	145	* Jump to U-Boot image
	146	*/
	147	puts("transfering control\n");
c70564e6 DL	148	/*
	149	* Clean d-cache and invalidate i-cache, to
	150	* make sure that no stale data is executed.
	151	*/
	152	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
6d0f6bcf	153	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
e4c09508 SW	154	uboot();
e4c09508 SW	155	}