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c3452b50 AM |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * (C) Copyright 2019 | |
4 | * Alex Marginean, NXP | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <dm.h> | |
f7ae49fc | 9 | #include <log.h> |
336d4615 | 10 | #include <malloc.h> |
c3452b50 AM |
11 | #include <miiphy.h> |
12 | #include <dm/device-internal.h> | |
336d4615 | 13 | #include <dm/device_compat.h> |
33aad0b0 | 14 | #include <dm/of_extra.h> |
c3452b50 | 15 | #include <dm/uclass-internal.h> |
336d4615 | 16 | #include <linux/compat.h> |
a0e02c66 RQ |
17 | #include <linux/delay.h> |
18 | ||
19 | #define DEFAULT_GPIO_RESET_DELAY 10 /* in microseconds */ | |
c3452b50 AM |
20 | |
21 | void dm_mdio_probe_devices(void) | |
22 | { | |
23 | struct udevice *it; | |
24 | struct uclass *uc; | |
25 | ||
26 | uclass_get(UCLASS_MDIO, &uc); | |
27 | uclass_foreach_dev(it, uc) { | |
28 | device_probe(it); | |
29 | } | |
30 | } | |
31 | ||
32 | static int dm_mdio_post_bind(struct udevice *dev) | |
33 | { | |
6b3abc04 AM |
34 | const char *dt_name; |
35 | ||
36 | /* set a custom name for the MDIO device, if present in DT */ | |
f10643cf SG |
37 | if (dev_has_ofnode(dev)) { |
38 | dt_name = dev_read_string(dev, "device-name"); | |
6b3abc04 AM |
39 | if (dt_name) { |
40 | debug("renaming dev %s to %s\n", dev->name, dt_name); | |
41 | device_set_name(dev, dt_name); | |
42 | } | |
43 | } | |
44 | ||
c3452b50 AM |
45 | /* |
46 | * MDIO command doesn't like spaces in names, don't allow them to keep | |
47 | * it happy | |
48 | */ | |
49 | if (strchr(dev->name, ' ')) { | |
50 | debug("\nError: MDIO device name \"%s\" has a space!\n", | |
51 | dev->name); | |
52 | return -EINVAL; | |
53 | } | |
54 | ||
f54002d7 TH |
55 | #if CONFIG_IS_ENABLED(OF_REAL) |
56 | return dm_scan_fdt_dev(dev); | |
57 | #else | |
c3452b50 | 58 | return 0; |
f54002d7 | 59 | #endif |
c3452b50 AM |
60 | } |
61 | ||
351bfa6e MB |
62 | int dm_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) |
63 | { | |
64 | struct mdio_ops *ops = mdio_get_ops(mdio_dev); | |
65 | ||
66 | if (!ops->read) | |
67 | return -ENOSYS; | |
68 | ||
69 | return ops->read(mdio_dev, addr, devad, reg); | |
70 | } | |
71 | ||
72 | int dm_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, | |
73 | u16 val) | |
74 | { | |
75 | struct mdio_ops *ops = mdio_get_ops(mdio_dev); | |
76 | ||
77 | if (!ops->write) | |
78 | return -ENOSYS; | |
79 | ||
80 | return ops->write(mdio_dev, addr, devad, reg, val); | |
81 | } | |
82 | ||
83 | int dm_mdio_reset(struct udevice *mdio_dev) | |
84 | { | |
85 | struct mdio_ops *ops = mdio_get_ops(mdio_dev); | |
a0e02c66 RQ |
86 | struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); |
87 | struct mii_dev *mii_bus = pdata->mii_bus; | |
88 | ||
89 | if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&mii_bus->reset_gpiod)) { | |
90 | dm_gpio_set_value(&mii_bus->reset_gpiod, 1); | |
91 | udelay(mii_bus->reset_delay_us); | |
92 | dm_gpio_set_value(&mii_bus->reset_gpiod, 0); | |
93 | if (mii_bus->reset_post_delay_us > 0) | |
94 | udelay(mii_bus->reset_post_delay_us); | |
95 | } | |
351bfa6e MB |
96 | |
97 | if (!ops->reset) | |
98 | return 0; | |
99 | ||
100 | return ops->reset(mdio_dev); | |
101 | } | |
102 | ||
c3452b50 AM |
103 | /* |
104 | * Following read/write/reset functions are registered with legacy MII code. | |
105 | * These are called for PHY operations by upper layers and we further call the | |
106 | * DM MDIO driver functions. | |
107 | */ | |
108 | static int mdio_read(struct mii_dev *mii_bus, int addr, int devad, int reg) | |
109 | { | |
1776a24b | 110 | return dm_mdio_read(mii_bus->priv, addr, devad, reg); |
c3452b50 AM |
111 | } |
112 | ||
113 | static int mdio_write(struct mii_dev *mii_bus, int addr, int devad, int reg, | |
114 | u16 val) | |
115 | { | |
1776a24b | 116 | return dm_mdio_write(mii_bus->priv, addr, devad, reg, val); |
c3452b50 AM |
117 | } |
118 | ||
119 | static int mdio_reset(struct mii_dev *mii_bus) | |
120 | { | |
1776a24b | 121 | return dm_mdio_reset(mii_bus->priv); |
c3452b50 AM |
122 | } |
123 | ||
124 | static int dm_mdio_post_probe(struct udevice *dev) | |
125 | { | |
126 | struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev); | |
a0e02c66 RQ |
127 | struct mii_dev *mii_bus; |
128 | int ret; | |
c3452b50 | 129 | |
a0e02c66 RQ |
130 | mii_bus = mdio_alloc(); |
131 | if (!mii_bus) { | |
132 | dev_err(dev, "couldn't allocate mii_bus\n"); | |
133 | return -ENOMEM; | |
134 | } | |
135 | pdata->mii_bus = mii_bus; | |
c3452b50 AM |
136 | pdata->mii_bus->read = mdio_read; |
137 | pdata->mii_bus->write = mdio_write; | |
138 | pdata->mii_bus->reset = mdio_reset; | |
139 | pdata->mii_bus->priv = dev; | |
bf35c312 | 140 | strlcpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN); |
c3452b50 | 141 | |
a0e02c66 RQ |
142 | if (IS_ENABLED(CONFIG_DM_GPIO)) { |
143 | /* Get bus level PHY reset GPIO details */ | |
144 | mii_bus->reset_delay_us = dev_read_u32_default(dev, "reset-delay-us", | |
145 | DEFAULT_GPIO_RESET_DELAY); | |
146 | mii_bus->reset_post_delay_us = dev_read_u32_default(dev, | |
147 | "reset-post-delay-us", | |
148 | 0); | |
149 | ret = gpio_request_by_name(dev, "reset-gpios", 0, &mii_bus->reset_gpiod, | |
150 | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); | |
151 | if (ret && ret != -ENOENT) { | |
152 | dev_err(dev, "couldn't get reset-gpios: %d\n", ret); | |
153 | return ret; | |
154 | } | |
155 | } | |
156 | ||
c3452b50 AM |
157 | return mdio_register(pdata->mii_bus); |
158 | } | |
159 | ||
160 | static int dm_mdio_pre_remove(struct udevice *dev) | |
161 | { | |
162 | struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev); | |
c3452b50 | 163 | |
1776a24b | 164 | dm_mdio_reset(dev); |
c3452b50 AM |
165 | mdio_unregister(pdata->mii_bus); |
166 | mdio_free(pdata->mii_bus); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
00b1bad9 MB |
171 | struct phy_device *dm_phy_find_by_ofnode(ofnode phynode) |
172 | { | |
173 | struct mdio_perdev_priv *pdata; | |
174 | struct udevice *mdiodev; | |
175 | u32 phy_addr; | |
176 | ||
177 | if (ofnode_read_u32(phynode, "reg", &phy_addr)) | |
178 | return NULL; | |
179 | ||
180 | if (uclass_get_device_by_ofnode(UCLASS_MDIO, | |
181 | ofnode_get_parent(phynode), | |
182 | &mdiodev)) | |
183 | return NULL; | |
184 | ||
185 | if (device_probe(mdiodev)) | |
186 | return NULL; | |
187 | ||
188 | pdata = dev_get_uclass_priv(mdiodev); | |
189 | ||
190 | return phy_find_by_mask(pdata->mii_bus, BIT(phy_addr)); | |
191 | } | |
192 | ||
a5d32c37 | 193 | struct phy_device *dm_mdio_phy_connect(struct udevice *mdiodev, int phyaddr, |
c3452b50 AM |
194 | struct udevice *ethdev, |
195 | phy_interface_t interface) | |
196 | { | |
a5d32c37 | 197 | struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdiodev); |
c3452b50 | 198 | |
a5d32c37 AM |
199 | if (device_probe(mdiodev)) |
200 | return NULL; | |
c3452b50 | 201 | |
a5d32c37 | 202 | return phy_connect(pdata->mii_bus, phyaddr, ethdev, interface); |
c3452b50 AM |
203 | } |
204 | ||
2f624559 AM |
205 | static struct phy_device *dm_eth_connect_phy_handle(struct udevice *ethdev, |
206 | phy_interface_t interface) | |
207 | { | |
208 | u32 phy_addr; | |
209 | struct udevice *mdiodev; | |
210 | struct phy_device *phy; | |
f27bc8af | 211 | ofnode phynode; |
2f624559 | 212 | |
b51b1a84 | 213 | if (IS_ENABLED(CONFIG_PHY_FIXED) && |
f27bc8af VO |
214 | ofnode_phy_is_fixed_link(dev_ofnode(ethdev), &phynode)) { |
215 | phy = phy_connect(NULL, 0, ethdev, interface); | |
bdf31927 RV |
216 | goto out; |
217 | } | |
218 | ||
f3dd213e MB |
219 | phynode = dev_get_phy_node(ethdev); |
220 | if (!ofnode_valid(phynode)) { | |
0851bd1e | 221 | dev_dbg(ethdev, "can't find PHY node\n"); |
2f624559 AM |
222 | return NULL; |
223 | } | |
224 | ||
225 | /* | |
226 | * reading 'reg' directly should be fine. This is a PHY node, the | |
227 | * address is always size 1 and requires no translation | |
228 | */ | |
f3dd213e | 229 | if (ofnode_read_u32(phynode, "reg", &phy_addr)) { |
2f624559 AM |
230 | dev_dbg(ethdev, "missing reg property in phy node\n"); |
231 | return NULL; | |
232 | } | |
233 | ||
234 | if (uclass_get_device_by_ofnode(UCLASS_MDIO, | |
f3dd213e | 235 | ofnode_get_parent(phynode), |
2f624559 | 236 | &mdiodev)) { |
0851bd1e | 237 | dev_dbg(ethdev, "can't find MDIO bus for node %s\n", |
f3dd213e | 238 | ofnode_get_name(ofnode_get_parent(phynode))); |
2f624559 AM |
239 | return NULL; |
240 | } | |
241 | ||
242 | phy = dm_mdio_phy_connect(mdiodev, phy_addr, ethdev, interface); | |
243 | ||
bdf31927 | 244 | out: |
2f624559 | 245 | if (phy) |
f3dd213e | 246 | phy->node = phynode; |
2f624559 AM |
247 | |
248 | return phy; | |
249 | } | |
250 | ||
251 | /* Connect to a PHY linked in eth DT node */ | |
252 | struct phy_device *dm_eth_phy_connect(struct udevice *ethdev) | |
253 | { | |
2f624559 AM |
254 | phy_interface_t interface; |
255 | struct phy_device *phy; | |
2f624559 | 256 | |
f10643cf | 257 | if (!dev_has_ofnode(ethdev)) { |
2f624559 AM |
258 | debug("%s: supplied eth dev has no DT node!\n", ethdev->name); |
259 | return NULL; | |
260 | } | |
261 | ||
123ca114 | 262 | interface = dev_read_phy_mode(ethdev); |
ffb0f6f4 MB |
263 | if (interface == PHY_INTERFACE_MODE_NA) |
264 | dev_dbg(ethdev, "can't find interface mode, default to NA\n"); | |
2f624559 AM |
265 | |
266 | phy = dm_eth_connect_phy_handle(ethdev, interface); | |
267 | ||
268 | if (!phy) | |
269 | return NULL; | |
270 | ||
271 | phy->interface = interface; | |
272 | ||
273 | return phy; | |
274 | } | |
275 | ||
c3452b50 AM |
276 | UCLASS_DRIVER(mdio) = { |
277 | .id = UCLASS_MDIO, | |
278 | .name = "mdio", | |
279 | .post_bind = dm_mdio_post_bind, | |
280 | .post_probe = dm_mdio_post_probe, | |
281 | .pre_remove = dm_mdio_pre_remove, | |
41575d8e | 282 | .per_device_auto = sizeof(struct mdio_perdev_priv), |
c3452b50 | 283 | }; |