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6a18e85b GKH |
1 | From 78f4e932f7760d965fb1569025d1576ab77557c5 Mon Sep 17 00:00:00 2001 |
2 | From: Borislav Petkov <bp@suse.de> | |
3 | Date: Thu, 13 Jun 2019 15:49:02 +0200 | |
4 | Subject: x86/microcode, cpuhotplug: Add a microcode loader CPU hotplug callback | |
5 | ||
6 | From: Borislav Petkov <bp@suse.de> | |
7 | ||
8 | commit 78f4e932f7760d965fb1569025d1576ab77557c5 upstream. | |
9 | ||
10 | Adric Blake reported the following warning during suspend-resume: | |
11 | ||
12 | Enabling non-boot CPUs ... | |
13 | x86: Booting SMP configuration: | |
14 | smpboot: Booting Node 0 Processor 1 APIC 0x2 | |
15 | unchecked MSR access error: WRMSR to 0x10f (tried to write 0x0000000000000000) \ | |
16 | at rIP: 0xffffffff8d267924 (native_write_msr+0x4/0x20) | |
17 | Call Trace: | |
18 | intel_set_tfa | |
19 | intel_pmu_cpu_starting | |
20 | ? x86_pmu_dead_cpu | |
21 | x86_pmu_starting_cpu | |
22 | cpuhp_invoke_callback | |
23 | ? _raw_spin_lock_irqsave | |
24 | notify_cpu_starting | |
25 | start_secondary | |
26 | secondary_startup_64 | |
27 | microcode: sig=0x806ea, pf=0x80, revision=0x96 | |
28 | microcode: updated to revision 0xb4, date = 2019-04-01 | |
29 | CPU1 is up | |
30 | ||
31 | The MSR in question is MSR_TFA_RTM_FORCE_ABORT and that MSR is emulated | |
32 | by microcode. The log above shows that the microcode loader callback | |
33 | happens after the PMU restoration, leading to the conjecture that | |
34 | because the microcode hasn't been updated yet, that MSR is not present | |
35 | yet, leading to the #GP. | |
36 | ||
37 | Add a microcode loader-specific hotplug vector which comes before | |
38 | the PERF vectors and thus executes earlier and makes sure the MSR is | |
39 | present. | |
40 | ||
41 | Fixes: 400816f60c54 ("perf/x86/intel: Implement support for TSX Force Abort") | |
42 | Reported-by: Adric Blake <promarbler14@gmail.com> | |
43 | Signed-off-by: Borislav Petkov <bp@suse.de> | |
44 | Reviewed-by: Thomas Gleixner <tglx@linutronix.de> | |
45 | Cc: Peter Zijlstra <peterz@infradead.org> | |
46 | Cc: <stable@vger.kernel.org> | |
47 | Cc: x86@kernel.org | |
48 | Link: https://bugzilla.kernel.org/show_bug.cgi?id=203637 | |
49 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
50 | ||
51 | --- | |
52 | arch/x86/kernel/cpu/microcode/core.c | 2 +- | |
53 | include/linux/cpuhotplug.h | 1 + | |
54 | 2 files changed, 2 insertions(+), 1 deletion(-) | |
55 | ||
56 | --- a/arch/x86/kernel/cpu/microcode/core.c | |
57 | +++ b/arch/x86/kernel/cpu/microcode/core.c | |
58 | @@ -873,7 +873,7 @@ int __init microcode_init(void) | |
59 | goto out_ucode_group; | |
60 | ||
61 | register_syscore_ops(&mc_syscore_ops); | |
62 | - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", | |
63 | + cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:online", | |
64 | mc_cpu_online, mc_cpu_down_prep); | |
65 | ||
66 | pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); | |
67 | --- a/include/linux/cpuhotplug.h | |
68 | +++ b/include/linux/cpuhotplug.h | |
69 | @@ -101,6 +101,7 @@ enum cpuhp_state { | |
70 | CPUHP_AP_IRQ_BCM2836_STARTING, | |
71 | CPUHP_AP_IRQ_MIPS_GIC_STARTING, | |
72 | CPUHP_AP_ARM_MVEBU_COHERENCY, | |
73 | + CPUHP_AP_MICROCODE_LOADER, | |
74 | CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING, | |
75 | CPUHP_AP_PERF_X86_STARTING, | |
76 | CPUHP_AP_PERF_X86_AMD_IBS_STARTING, |