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ad5bb451
WD		 1/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26/*
27 * Ethernet test
28 *
29 * The Serial Communication Controllers (SCC) listed in ctlr_list array below
30 * are tested in the loopback ethernet mode.
31 * The controllers are configured accordingly and several packets
32 * are transmitted. The configurable test parameters are:
33 * MIN_PACKET_LENGTH - minimum size of packet to transmit
34 * MAX_PACKET_LENGTH - maximum size of packet to transmit
35 * TEST_NUM - number of tests
36 */
37
ad5bb451 38#include <post.h>
6d0f6bcf 39#if CONFIG_POST & CONFIG_SYS_POST_ETHER
ad5bb451
WD		 40#if defined(CONFIG_8xx)
41#include <commproc.h>
42#elif defined(CONFIG_MPC8260)
43#include <asm/cpm_8260.h>
44#else
45#error "Apparently a bad configuration, please fix."
46#endif
47
48#include <command.h>
49#include <net.h>
50#include <serial.h>
51
52DECLARE_GLOBAL_DATA_PTR;
53
54#define MIN_PACKET_LENGTH 64
55#define MAX_PACKET_LENGTH 256
56#define TEST_NUM 1
57
58#define CTLR_SCC 0
59
60extern void spi_init_f (void);
61extern void spi_init_r (void);
62
63/* The list of controllers to test */
64#if defined(CONFIG_MPC823)
65static int ctlr_list[][2] = { {CTLR_SCC, 1} };
66#else
67static int ctlr_list[][2] = { };
68#endif
69
70#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
71
72static struct {
73 void (*init) (int index);
74 void (*halt) (int index);
75 int (*send) (int index, volatile void *packet, int length);
76 int (*recv) (int index, void *packet, int length);
77} ctlr_proc[1];
78
79static char *ctlr_name[1] = { "SCC" };
80
81/* Ethernet Transmit and Receive Buffers */
82#define DBUF_LENGTH 1520
83
84#define TX_BUF_CNT 2
85
86#define TOUT_LOOP 100
87
88static char txbuf[DBUF_LENGTH];
89
90static uint rxIdx; /* index of the current RX buffer */
91static uint txIdx; /* index of the current TX buffer */
92
93/*
94 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
95 * immr->udata_bd address on Dual-Port RAM
96 * Provide for Double Buffering
97 */
98
99typedef volatile struct CommonBufferDescriptor {
100 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
101 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
102} RTXBD;
103
104static RTXBD *rtx;
105
106 /*
107 * SCC callbacks
108 */
109
110static void scc_init (int scc_index)
111{
112 bd_t *bd = gd->bd;
113
114 static int proff[] =
115 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
116 static unsigned int cpm_cr[] =
117 { CPM_CR_CH_SCC1, CPM_CR_CH_SCC2, CPM_CR_CH_SCC3,
118CPM_CR_CH_SCC4 };
119
120 int i;
121 scc_enet_t *pram_ptr;
122
6d0f6bcf 123 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ad5bb451
WD		 124
125 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
126 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
127
128#if defined(CONFIG_FADS)
129#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
130 /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
131 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
132 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
133 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
134#else
135 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
136 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
137 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
138#endif
139#endif
140
141 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
142
143 rxIdx = 0;
144 txIdx = 0;
145
6d0f6bcf 146#ifdef CONFIG_SYS_ALLOC_DPRAM
ad5bb451
WD		 147 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
148 dpram_alloc_align (sizeof (RTXBD), 8));
149#else
150 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
151#endif
152
153#if 0
154
155#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
156 /* Configure port A pins for Txd and Rxd.
157 */
158 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
159 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
160 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
161#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
162 /* Configure port B pins for Txd and Rxd.
163 */
164 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
165 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
166 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
167#else
168#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
169#endif
170
171#if defined(PC_ENET_LBK)
172 /* Configure port C pins to disable External Loopback
173 */
174 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
175 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
176 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
177 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
178#endif /* PC_ENET_LBK */
179
180 /* Configure port C pins to enable CLSN and RENA.
181 */
182 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
183 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
184 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
185
186 /* Configure port A for TCLK and RCLK.
187 */
188 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
189 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
190
191 /*
192 * Configure Serial Interface clock routing -- see section 16.7.5.3
193 * First, clear all SCC bits to zero, then set the ones we want.
194 */
195
196 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
197 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
198#else
199 /*
200 * SCC2 receive clock is BRG2
201 * SCC2 transmit clock is BRG3
202 */
203 immr->im_cpm.cp_brgc2 = 0x0001000C;
204 immr->im_cpm.cp_brgc3 = 0x0001000C;
205
206 immr->im_cpm.cp_sicr &= ~0x00003F00;
207 immr->im_cpm.cp_sicr |= 0x00000a00;
208#endif /* 0 */
209
210
211 /*
212 * Initialize SDCR -- see section 16.9.23.7
213 * SDMA configuration register
214 */
215 immr->im_siu_conf.sc_sdcr = 0x01;
216
217
218 /*
219 * Setup SCC Ethernet Parameter RAM
220 */
221
222 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
223 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
224
225 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
226
227 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
228 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
229
230 /*
231 * Setup Receiver Buffer Descriptors (13.14.24.18)
232 * Settings:
233 * Empty, Wrap
234 */
235
236 for (i = 0; i < PKTBUFSRX; i++) {
237 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
238 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
239 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
240 }
241
242 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
243
244 /*
245 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
246 * Settings:
247 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
248 */
249
250 for (i = 0; i < TX_BUF_CNT; i++) {
251 rtx->txbd[i].cbd_sc =
252 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
253 rtx->txbd[i].cbd_datlen = 0; /* Reset */
254 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
255 }
256
257 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
258
259 /*
260 * Enter Command: Initialize Rx Params for SCC
261 */
262
263 do { /* Spin until ready to issue command */
264 __asm__ ("eieio");
265 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
266 /* Issue command */
267 immr->im_cpm.cp_cpcr =
268 ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
269 CPM_CR_FLG);
270 do { /* Spin until command processed */
271 __asm__ ("eieio");
272 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
273
274 /*
275 * Ethernet Specific Parameter RAM
276 * see table 13-16, pg. 660,
277 * pg. 681 (example with suggested settings)
278 */
279
280 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
281 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
282 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
283 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
284 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
285 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
286
287 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
288 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
289 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
290
291 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
292 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
293
294 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
295 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
296 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
297 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
298
299#define ea bd->bi_enetaddr
300 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
301 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
302 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
303#undef ea
304
305 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
306 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
307 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
308 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
309 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
310 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
311 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
312 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
313
314 /*
315 * Enter Command: Initialize Tx Params for SCC
316 */
317
318 do { /* Spin until ready to issue command */
319 __asm__ ("eieio");
320 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
321 /* Issue command */
322 immr->im_cpm.cp_cpcr =
323 ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
324 CPM_CR_FLG);
325 do { /* Spin until command processed */
326 __asm__ ("eieio");
327 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
328
329 /*
330 * Mask all Events in SCCM - we use polling mode
331 */
332 immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
333
334 /*
335 * Clear Events in SCCE -- Clear bits by writing 1's
336 */
337
338 immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
339
340
341 /*
342 * Initialize GSMR High 32-Bits
343 * Settings: Normal Mode
344 */
345
346 immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
347
348 /*
349 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
350 * Settings:
351 * TCI = Invert
352 * TPL = 48 bits
353 * TPP = Repeating 10's
354 * LOOP = Loopback
355 * MODE = Ethernet
356 */
357
358 immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
359 SCC_GSMRL_TPL_48 |
360 SCC_GSMRL_TPP_10 |
361 SCC_GSMRL_DIAG_LOOP |
362 SCC_GSMRL_MODE_ENET);
363
364 /*
365 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
366 */
367
368 immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
369
370 /*
371 * Initialize the PSMR
372 * Settings:
373 * CRC = 32-Bit CCITT
374 * NIB = Begin searching for SFD 22 bits after RENA
375 * LPB = Loopback Enable (Needed when FDE is set)
376 */
377 immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
378 SCC_PSMR_NIB22 | SCC_PSMR_LPB;
379
380#if 0
381 /*
382 * Configure Ethernet TENA Signal
383 */
384
385#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
386 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
387 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
388#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
389 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
390 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
391#else
392#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
393#endif
394
395#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
396 /*
397 * Port C is used to control the PHY,MC68160.
398 */
399 immr->im_ioport.iop_pcdir |=
400 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
401
402 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
403 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
404 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
405#endif /* MPC860ADS */
406
407#if defined(CONFIG_AMX860)
408 /*
409 * Port B is used to control the PHY,MC68160.
410 */
411 immr->im_cpm.cp_pbdir |=
412 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
413
414 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
415 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
416
417 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
418 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
419#endif /* AMX860 */
420
421#endif /* 0 */
422
423#ifdef CONFIG_RPXCLASSIC
424 *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
425 *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
426#endif
427
428#ifdef CONFIG_RPXLITE
429 *((uchar *) BCSR0) |= BCSR0_ETHEN;
430#endif
431
432#ifdef CONFIG_MBX
433 board_ether_init ();
434#endif
435
436 /*
437 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
438 */
439
440 immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
441 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
442
443 /*
444 * Work around transmit problem with first eth packet
445 */
446#if defined (CONFIG_FADS)
447 udelay (10000); /* wait 10 ms */
448#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
449 udelay (100000); /* wait 100 ms */
450#endif
451}
452
453static void scc_halt (int scc_index)
454{
6d0f6bcf 455 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ad5bb451
WD		 456
457 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
458 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
459 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
460}
461
462static int scc_send (int index, volatile void *packet, int length)
463{
464 int i, j = 0;
465
466 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
467 udelay (1); /* will also trigger Wd if needed */
468 j++;
469 }
470 if (j >= TOUT_LOOP)
471 printf ("TX not ready\n");
472 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
473 rtx->txbd[txIdx].cbd_datlen = length;
474 rtx->txbd[txIdx].cbd_sc |=
475 (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
476 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
477 udelay (1); /* will also trigger Wd if needed */
478 j++;
479 }
480 if (j >= TOUT_LOOP)
481 printf ("TX timeout\n");
482 i = (rtx->txbd[txIdx].
483 cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
484 return i;
485}
486
487static int scc_recv (int index, void *packet, int max_length)
488{
489 int length = -1;
490
491 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
492 goto Done; /* nothing received */
493 }
494
495 if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
496 length = rtx->rxbd[rxIdx].cbd_datlen - 4;
497 memcpy (packet,
498 (void *) (NetRxPackets[rxIdx]),
499 length < max_length ? length : max_length);
500 }
501
502 /* Give the buffer back to the SCC. */
503 rtx->rxbd[rxIdx].cbd_datlen = 0;
504
505 /* wrap around buffer index when necessary */
506 if ((rxIdx + 1) >= PKTBUFSRX) {
507 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
508 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
509 rxIdx = 0;
510 } else {
511 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
512 rxIdx++;
513 }
514
515Done:
516 return length;
517}
518
519 /*
520 * Test routines
521 */
522
523static void packet_fill (char *packet, int length)
524{
525 char c = (char) length;
526 int i;
527
528 packet[0] = 0xFF;
529 packet[1] = 0xFF;
530 packet[2] = 0xFF;
531 packet[3] = 0xFF;
532 packet[4] = 0xFF;
533 packet[5] = 0xFF;
534
535 for (i = 6; i < length; i++) {
536 packet[i] = c++;
537 }
538}
539
540static int packet_check (char *packet, int length)
541{
542 char c = (char) length;
543 int i;
544
545 for (i = 6; i < length; i++) {
546 if (packet[i] != c++)
547 return -1;
548 }
549
550 return 0;
551}
552
553static int test_ctlr (int ctlr, int index)
554{
555 int res = -1;
556 char packet_send[MAX_PACKET_LENGTH];
557 char packet_recv[MAX_PACKET_LENGTH];
558 int length;
559 int i;
560 int l;
561
562 ctlr_proc[ctlr].init (index);
563
564 for (i = 0; i < TEST_NUM; i++) {
565 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
566 packet_fill (packet_send, l);
567
568 ctlr_proc[ctlr].send (index, packet_send, l);
569
570 length = ctlr_proc[ctlr].recv (index, packet_recv,
571 MAX_PACKET_LENGTH);
572
573 if (length != l || packet_check (packet_recv, length) < 0) {
574 goto Done;
575 }
576 }
577 }
578
579 res = 0;
580
581Done:
582
583 ctlr_proc[ctlr].halt (index);
584
585 /*
586 * SCC2 Ethernet parameter RAM space overlaps
587 * the SPI parameter RAM space. So we need to restore
588 * the SPI configuration after SCC2 ethernet test.
589 */
590#if defined(CONFIG_SPI)
591 if (ctlr == CTLR_SCC && index == 1) {
592 spi_init_f ();
593 spi_init_r ();
594 }
595#endif
596
597 if (res != 0) {
598 post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
599 index + 1);
600 }
601
602 return res;
603}
604
605int ether_post_test (int flags)
606{
607 int res = 0;
608 int i;
609
610 ctlr_proc[CTLR_SCC].init = scc_init;
611 ctlr_proc[CTLR_SCC].halt = scc_halt;
612 ctlr_proc[CTLR_SCC].send = scc_send;
613 ctlr_proc[CTLR_SCC].recv = scc_recv;
614
615 for (i = 0; i < CTRL_LIST_SIZE; i++) {
616 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
617 res = -1;
618 }
619 }
620
621#if !defined(CONFIG_8xx_CONS_NONE)
622 serial_reinit_all ();
623#endif
624 return res;
625}
626
6d0f6bcf 627#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
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