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ad5bb451 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
ad5bb451 WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | ||
10 | /* Memory test | |
11 | * | |
12 | * General observations: | |
13 | * o The recommended test sequence is to test the data lines: if they are | |
14 | * broken, nothing else will work properly. Then test the address | |
15 | * lines. Finally, test the cells in the memory now that the test | |
16 | * program knows that the address and data lines work properly. | |
17 | * This sequence also helps isolate and identify what is faulty. | |
18 | * | |
19 | * o For the address line test, it is a good idea to use the base | |
20 | * address of the lowest memory location, which causes a '1' bit to | |
21 | * walk through a field of zeros on the address lines and the highest | |
22 | * memory location, which causes a '0' bit to walk through a field of | |
23 | * '1's on the address line. | |
24 | * | |
25 | * o Floating buses can fool memory tests if the test routine writes | |
26 | * a value and then reads it back immediately. The problem is, the | |
27 | * write will charge the residual capacitance on the data bus so the | |
28 | * bus retains its state briefely. When the test program reads the | |
29 | * value back immediately, the capacitance of the bus can allow it | |
30 | * to read back what was written, even though the memory circuitry | |
31 | * is broken. To avoid this, the test program should write a test | |
32 | * pattern to the target location, write a different pattern elsewhere | |
33 | * to charge the residual capacitance in a differnt manner, then read | |
34 | * the target location back. | |
35 | * | |
36 | * o Always read the target location EXACTLY ONCE and save it in a local | |
37 | * variable. The problem with reading the target location more than | |
38 | * once is that the second and subsequent reads may work properly, | |
39 | * resulting in a failed test that tells the poor technician that | |
40 | * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which | |
41 | * doesn't help him one bit and causes puzzled phone calls. Been there, | |
42 | * done that. | |
43 | * | |
44 | * Data line test: | |
45 | * --------------- | |
46 | * This tests data lines for shorts and opens by forcing adjacent data | |
47 | * to opposite states. Because the data lines could be routed in an | |
48 | * arbitrary manner the must ensure test patterns ensure that every case | |
49 | * is tested. By using the following series of binary patterns every | |
50 | * combination of adjacent bits is test regardless of routing. | |
51 | * | |
52 | * ...101010101010101010101010 | |
53 | * ...110011001100110011001100 | |
54 | * ...111100001111000011110000 | |
55 | * ...111111110000000011111111 | |
56 | * | |
57 | * Carrying this out, gives us six hex patterns as follows: | |
58 | * | |
59 | * 0xaaaaaaaaaaaaaaaa | |
60 | * 0xcccccccccccccccc | |
61 | * 0xf0f0f0f0f0f0f0f0 | |
62 | * 0xff00ff00ff00ff00 | |
63 | * 0xffff0000ffff0000 | |
64 | * 0xffffffff00000000 | |
65 | * | |
66 | * To test for short and opens to other signals on our boards, we | |
67 | * simply test with the 1's complemnt of the paterns as well, resulting | |
68 | * in twelve patterns total. | |
69 | * | |
70 | * After writing a test pattern. a special pattern 0x0123456789ABCDEF is | |
71 | * written to a different address in case the data lines are floating. | |
72 | * Thus, if a byte lane fails, you will see part of the special | |
73 | * pattern in that byte lane when the test runs. For example, if the | |
74 | * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa | |
75 | * (for the 'a' test pattern). | |
76 | * | |
77 | * Address line test: | |
78 | * ------------------ | |
79 | * This function performs a test to verify that all the address lines | |
80 | * hooked up to the RAM work properly. If there is an address line | |
81 | * fault, it usually shows up as two different locations in the address | |
82 | * map (related by the faulty address line) mapping to one physical | |
83 | * memory storage location. The artifact that shows up is writing to | |
84 | * the first location "changes" the second location. | |
85 | * | |
86 | * To test all address lines, we start with the given base address and | |
87 | * xor the address with a '1' bit to flip one address line. For each | |
88 | * test, we shift the '1' bit left to test the next address line. | |
89 | * | |
90 | * In the actual code, we start with address sizeof(ulong) since our | |
91 | * test pattern we use is a ulong and thus, if we tried to test lower | |
92 | * order address bits, it wouldn't work because our pattern would | |
93 | * overwrite itself. | |
94 | * | |
95 | * Example for a 4 bit address space with the base at 0000: | |
96 | * 0000 <- base | |
97 | * 0001 <- test 1 | |
98 | * 0010 <- test 2 | |
99 | * 0100 <- test 3 | |
100 | * 1000 <- test 4 | |
101 | * Example for a 4 bit address space with the base at 0010: | |
102 | * 0010 <- base | |
103 | * 0011 <- test 1 | |
104 | * 0000 <- (below the base address, skipped) | |
105 | * 0110 <- test 2 | |
106 | * 1010 <- test 3 | |
107 | * | |
108 | * The test locations are successively tested to make sure that they are | |
109 | * not "mirrored" onto the base address due to a faulty address line. | |
110 | * Note that the base and each test location are related by one address | |
111 | * line flipped. Note that the base address need not be all zeros. | |
112 | * | |
113 | * Memory tests 1-4: | |
114 | * ----------------- | |
115 | * These tests verify RAM using sequential writes and reads | |
116 | * to/from RAM. There are several test cases that use different patterns to | |
117 | * verify RAM. Each test case fills a region of RAM with one pattern and | |
118 | * then reads the region back and compares its contents with the pattern. | |
119 | * The following patterns are used: | |
120 | * | |
121 | * 1a) zero pattern (0x00000000) | |
122 | * 1b) negative pattern (0xffffffff) | |
123 | * 1c) checkerboard pattern (0x55555555) | |
124 | * 1d) checkerboard pattern (0xaaaaaaaa) | |
125 | * 2) bit-flip pattern ((1 << (offset % 32)) | |
126 | * 3) address pattern (offset) | |
127 | * 4) address pattern (~offset) | |
128 | * | |
129 | * Being run in normal mode, the test verifies only small 4Kb | |
130 | * regions of RAM around each 1Mb boundary. For example, for 64Mb | |
131 | * RAM the following areas are verified: 0x00000000-0x00000800, | |
132 | * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- | |
133 | * 0x04000000. If the test is run in slow-test mode, it verifies | |
134 | * the whole RAM. | |
135 | */ | |
136 | ||
ad5bb451 WD |
137 | #include <post.h> |
138 | #include <watchdog.h> | |
139 | ||
8d3fcb5e | 140 | #if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS) |
ad5bb451 WD |
141 | |
142 | DECLARE_GLOBAL_DATA_PTR; | |
143 | ||
144 | /* | |
145 | * Define INJECT_*_ERRORS for testing error detection in the presence of | |
146 | * _good_ hardware. | |
147 | */ | |
148 | #undef INJECT_DATA_ERRORS | |
149 | #undef INJECT_ADDRESS_ERRORS | |
150 | ||
151 | #ifdef INJECT_DATA_ERRORS | |
152 | #warning "Injecting data line errors for testing purposes" | |
153 | #endif | |
154 | ||
155 | #ifdef INJECT_ADDRESS_ERRORS | |
156 | #warning "Injecting address line errors for testing purposes" | |
157 | #endif | |
158 | ||
159 | ||
160 | /* | |
161 | * This function performs a double word move from the data at | |
162 | * the source pointer to the location at the destination pointer. | |
163 | * This is helpful for testing memory on processors which have a 64 bit | |
164 | * wide data bus. | |
165 | * | |
166 | * On those PowerPC with FPU, use assembly and a floating point move: | |
167 | * this does a 64 bit move. | |
168 | * | |
169 | * For other processors, let the compiler generate the best code it can. | |
170 | */ | |
44b4dbed | 171 | static void move64(const unsigned long long *src, unsigned long long *dest) |
ad5bb451 | 172 | { |
ad5bb451 | 173 | *dest = *src; |
ad5bb451 WD |
174 | } |
175 | ||
176 | /* | |
177 | * This is 64 bit wide test patterns. Note that they reside in ROM | |
178 | * (which presumably works) and the tests write them to RAM which may | |
179 | * not work. | |
180 | * | |
181 | * The "otherpattern" is written to drive the data bus to values other | |
182 | * than the test pattern. This is for detecting floating bus lines. | |
183 | * | |
184 | */ | |
185 | const static unsigned long long pattern[] = { | |
186 | 0xaaaaaaaaaaaaaaaaULL, | |
187 | 0xccccccccccccccccULL, | |
188 | 0xf0f0f0f0f0f0f0f0ULL, | |
189 | 0xff00ff00ff00ff00ULL, | |
190 | 0xffff0000ffff0000ULL, | |
191 | 0xffffffff00000000ULL, | |
192 | 0x00000000ffffffffULL, | |
193 | 0x0000ffff0000ffffULL, | |
194 | 0x00ff00ff00ff00ffULL, | |
195 | 0x0f0f0f0f0f0f0f0fULL, | |
196 | 0x3333333333333333ULL, | |
197 | 0x5555555555555555ULL | |
198 | }; | |
199 | const unsigned long long otherpattern = 0x0123456789abcdefULL; | |
200 | ||
201 | ||
202 | static int memory_post_dataline(unsigned long long * pmem) | |
203 | { | |
204 | unsigned long long temp64 = 0; | |
d2397817 | 205 | int num_patterns = ARRAY_SIZE(pattern); |
ad5bb451 WD |
206 | int i; |
207 | unsigned int hi, lo, pathi, patlo; | |
208 | int ret = 0; | |
209 | ||
210 | for ( i = 0; i < num_patterns; i++) { | |
44b4dbed | 211 | move64(&(pattern[i]), pmem++); |
ad5bb451 WD |
212 | /* |
213 | * Put a different pattern on the data lines: otherwise they | |
214 | * may float long enough to read back what we wrote. | |
215 | */ | |
44b4dbed | 216 | move64(&otherpattern, pmem--); |
ad5bb451 WD |
217 | move64(pmem, &temp64); |
218 | ||
219 | #ifdef INJECT_DATA_ERRORS | |
220 | temp64 ^= 0x00008000; | |
221 | #endif | |
222 | ||
223 | if (temp64 != pattern[i]){ | |
224 | pathi = (pattern[i]>>32) & 0xffffffff; | |
225 | patlo = pattern[i] & 0xffffffff; | |
226 | ||
227 | hi = (temp64>>32) & 0xffffffff; | |
228 | lo = temp64 & 0xffffffff; | |
229 | ||
e2ee3014 | 230 | post_log("Memory (data line) error at %08x, " |
ad5bb451 WD |
231 | "wrote %08x%08x, read %08x%08x !\n", |
232 | pmem, pathi, patlo, hi, lo); | |
233 | ret = -1; | |
234 | } | |
235 | } | |
236 | return ret; | |
237 | } | |
238 | ||
239 | static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) | |
240 | { | |
241 | ulong *target; | |
242 | ulong *end; | |
243 | ulong readback; | |
244 | ulong xor; | |
245 | int ret = 0; | |
246 | ||
247 | end = (ulong *)((ulong)base + size); /* pointer arith! */ | |
248 | xor = 0; | |
249 | for(xor = sizeof(ulong); xor > 0; xor <<= 1) { | |
250 | target = (ulong *)((ulong)testaddr ^ xor); | |
251 | if((target >= base) && (target < end)) { | |
252 | *testaddr = ~*target; | |
253 | readback = *target; | |
254 | ||
255 | #ifdef INJECT_ADDRESS_ERRORS | |
256 | if(xor == 0x00008000) { | |
257 | readback = *testaddr; | |
258 | } | |
259 | #endif | |
260 | if(readback == *testaddr) { | |
ca51d057 | 261 | post_log("Memory (address line) error at %08x<->%08x, " |
53677ef1 | 262 | "XOR value %08x !\n", |
ad5bb451 WD |
263 | testaddr, target, xor); |
264 | ret = -1; | |
265 | } | |
266 | } | |
267 | } | |
268 | return ret; | |
269 | } | |
270 | ||
ca51d057 | 271 | static int memory_post_test1(unsigned long start, |
ad5bb451 WD |
272 | unsigned long size, |
273 | unsigned long val) | |
274 | { | |
275 | unsigned long i; | |
276 | ulong *mem = (ulong *) start; | |
277 | ulong readback; | |
278 | int ret = 0; | |
279 | ||
280 | for (i = 0; i < size / sizeof (ulong); i++) { | |
281 | mem[i] = val; | |
282 | if (i % 1024 == 0) | |
ca51d057 | 283 | WATCHDOG_RESET(); |
ad5bb451 WD |
284 | } |
285 | ||
ca51d057 | 286 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
287 | readback = mem[i]; |
288 | if (readback != val) { | |
ca51d057 | 289 | post_log("Memory error at %08x, " |
ad5bb451 WD |
290 | "wrote %08x, read %08x !\n", |
291 | mem + i, val, readback); | |
292 | ||
293 | ret = -1; | |
294 | break; | |
295 | } | |
296 | if (i % 1024 == 0) | |
ca51d057 | 297 | WATCHDOG_RESET(); |
ad5bb451 WD |
298 | } |
299 | ||
300 | return ret; | |
301 | } | |
302 | ||
ca51d057 | 303 | static int memory_post_test2(unsigned long start, unsigned long size) |
ad5bb451 WD |
304 | { |
305 | unsigned long i; | |
306 | ulong *mem = (ulong *) start; | |
307 | ulong readback; | |
308 | int ret = 0; | |
309 | ||
310 | for (i = 0; i < size / sizeof (ulong); i++) { | |
311 | mem[i] = 1 << (i % 32); | |
312 | if (i % 1024 == 0) | |
ca51d057 | 313 | WATCHDOG_RESET(); |
ad5bb451 WD |
314 | } |
315 | ||
ca51d057 | 316 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
317 | readback = mem[i]; |
318 | if (readback != (1 << (i % 32))) { | |
ca51d057 | 319 | post_log("Memory error at %08x, " |
ad5bb451 WD |
320 | "wrote %08x, read %08x !\n", |
321 | mem + i, 1 << (i % 32), readback); | |
322 | ||
323 | ret = -1; | |
324 | break; | |
325 | } | |
326 | if (i % 1024 == 0) | |
ca51d057 | 327 | WATCHDOG_RESET(); |
ad5bb451 WD |
328 | } |
329 | ||
330 | return ret; | |
331 | } | |
332 | ||
ca51d057 | 333 | static int memory_post_test3(unsigned long start, unsigned long size) |
ad5bb451 WD |
334 | { |
335 | unsigned long i; | |
336 | ulong *mem = (ulong *) start; | |
337 | ulong readback; | |
338 | int ret = 0; | |
339 | ||
340 | for (i = 0; i < size / sizeof (ulong); i++) { | |
341 | mem[i] = i; | |
342 | if (i % 1024 == 0) | |
ca51d057 | 343 | WATCHDOG_RESET(); |
ad5bb451 WD |
344 | } |
345 | ||
ca51d057 | 346 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
347 | readback = mem[i]; |
348 | if (readback != i) { | |
ca51d057 | 349 | post_log("Memory error at %08x, " |
ad5bb451 WD |
350 | "wrote %08x, read %08x !\n", |
351 | mem + i, i, readback); | |
352 | ||
353 | ret = -1; | |
354 | break; | |
355 | } | |
356 | if (i % 1024 == 0) | |
ca51d057 | 357 | WATCHDOG_RESET(); |
ad5bb451 WD |
358 | } |
359 | ||
360 | return ret; | |
361 | } | |
362 | ||
ca51d057 | 363 | static int memory_post_test4(unsigned long start, unsigned long size) |
ad5bb451 WD |
364 | { |
365 | unsigned long i; | |
366 | ulong *mem = (ulong *) start; | |
367 | ulong readback; | |
368 | int ret = 0; | |
369 | ||
370 | for (i = 0; i < size / sizeof (ulong); i++) { | |
371 | mem[i] = ~i; | |
372 | if (i % 1024 == 0) | |
ca51d057 | 373 | WATCHDOG_RESET(); |
ad5bb451 WD |
374 | } |
375 | ||
ca51d057 | 376 | for (i = 0; i < size / sizeof (ulong) && !ret; i++) { |
ad5bb451 WD |
377 | readback = mem[i]; |
378 | if (readback != ~i) { | |
ca51d057 | 379 | post_log("Memory error at %08x, " |
ad5bb451 WD |
380 | "wrote %08x, read %08x !\n", |
381 | mem + i, ~i, readback); | |
382 | ||
383 | ret = -1; | |
384 | break; | |
385 | } | |
386 | if (i % 1024 == 0) | |
ca51d057 | 387 | WATCHDOG_RESET(); |
ad5bb451 WD |
388 | } |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
8d3fcb5e | 393 | static int memory_post_test_lines(unsigned long start, unsigned long size) |
ad5bb451 WD |
394 | { |
395 | int ret = 0; | |
396 | ||
8d3fcb5e | 397 | ret = memory_post_dataline((unsigned long long *)start); |
ca51d057 VL |
398 | WATCHDOG_RESET(); |
399 | if (!ret) | |
400 | ret = memory_post_addrline((ulong *)start, (ulong *)start, | |
8d3fcb5e | 401 | size); |
ca51d057 VL |
402 | WATCHDOG_RESET(); |
403 | if (!ret) | |
8d3fcb5e VL |
404 | ret = memory_post_addrline((ulong *)(start+size-8), |
405 | (ulong *)start, size); | |
ca51d057 | 406 | WATCHDOG_RESET(); |
8d3fcb5e VL |
407 | |
408 | return ret; | |
409 | } | |
410 | ||
411 | static int memory_post_test_patterns(unsigned long start, unsigned long size) | |
412 | { | |
413 | int ret = 0; | |
414 | ||
415 | ret = memory_post_test1(start, size, 0x00000000); | |
ca51d057 VL |
416 | WATCHDOG_RESET(); |
417 | if (!ret) | |
418 | ret = memory_post_test1(start, size, 0xffffffff); | |
419 | WATCHDOG_RESET(); | |
420 | if (!ret) | |
421 | ret = memory_post_test1(start, size, 0x55555555); | |
422 | WATCHDOG_RESET(); | |
423 | if (!ret) | |
424 | ret = memory_post_test1(start, size, 0xaaaaaaaa); | |
425 | WATCHDOG_RESET(); | |
426 | if (!ret) | |
427 | ret = memory_post_test2(start, size); | |
428 | WATCHDOG_RESET(); | |
429 | if (!ret) | |
430 | ret = memory_post_test3(start, size); | |
431 | WATCHDOG_RESET(); | |
432 | if (!ret) | |
433 | ret = memory_post_test4(start, size); | |
434 | WATCHDOG_RESET(); | |
ad5bb451 WD |
435 | |
436 | return ret; | |
437 | } | |
438 | ||
8d3fcb5e VL |
439 | static int memory_post_test_regions(unsigned long start, unsigned long size) |
440 | { | |
441 | unsigned long i; | |
442 | int ret = 0; | |
443 | ||
444 | for (i = 0; i < (size >> 20) && (!ret); i++) { | |
445 | if (!ret) | |
7b5d61b5 | 446 | ret = memory_post_test_patterns(start + (i << 20), |
8d3fcb5e | 447 | 0x800); |
7b5d61b5 HS |
448 | if (!ret) |
449 | ret = memory_post_test_patterns(start + (i << 20) + | |
450 | 0xff800, 0x800); | |
8d3fcb5e VL |
451 | } |
452 | ||
453 | return ret; | |
454 | } | |
455 | ||
456 | static int memory_post_tests(unsigned long start, unsigned long size) | |
457 | { | |
458 | int ret = 0; | |
459 | ||
460 | ret = memory_post_test_lines(start, size); | |
461 | if (!ret) | |
462 | ret = memory_post_test_patterns(start, size); | |
463 | ||
464 | return ret; | |
465 | } | |
466 | ||
4204298d HS |
467 | /* |
468 | * !! this is only valid, if you have contiguous memory banks !! | |
469 | */ | |
28417030 YS |
470 | __attribute__((weak)) |
471 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) | |
ad5bb451 | 472 | { |
ad5bb451 | 473 | bd_t *bd = gd->bd; |
4204298d | 474 | |
28417030 | 475 | *vstart = CONFIG_SYS_SDRAM_BASE; |
4204298d HS |
476 | *size = (gd->ram_size >= 256 << 20 ? |
477 | 256 << 20 : gd->ram_size) - (1 << 20); | |
ad5bb451 | 478 | |
9c02defc | 479 | /* Limit area to be tested with the board info struct */ |
28417030 YS |
480 | if ((*vstart) + (*size) > (ulong)bd) |
481 | *size = (ulong)bd - *vstart; | |
482 | ||
483 | return 0; | |
484 | } | |
ad5bb451 | 485 | |
28417030 YS |
486 | __attribute__((weak)) |
487 | int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) | |
488 | { | |
489 | return 1; | |
490 | } | |
ad5bb451 | 491 | |
28417030 YS |
492 | __attribute__((weak)) |
493 | int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) | |
494 | { | |
495 | return 0; | |
496 | } | |
ad5bb451 | 497 | |
28417030 YS |
498 | __attribute__((weak)) |
499 | void arch_memory_failure_handle(void) | |
500 | { | |
501 | return; | |
502 | } | |
503 | ||
8d3fcb5e VL |
504 | int memory_regions_post_test(int flags) |
505 | { | |
506 | int ret = 0; | |
507 | phys_addr_t phys_offset = 0; | |
508 | u32 memsize, vstart; | |
509 | ||
510 | arch_memory_test_prepare(&vstart, &memsize, &phys_offset); | |
511 | ||
512 | ret = memory_post_test_lines(vstart, memsize); | |
513 | if (!ret) | |
514 | ret = memory_post_test_regions(vstart, memsize); | |
515 | ||
516 | return ret; | |
517 | } | |
518 | ||
28417030 YS |
519 | int memory_post_test(int flags) |
520 | { | |
521 | int ret = 0; | |
522 | phys_addr_t phys_offset = 0; | |
523 | u32 memsize, vstart; | |
524 | ||
525 | arch_memory_test_prepare(&vstart, &memsize, &phys_offset); | |
526 | ||
527 | do { | |
528 | if (flags & POST_SLOWTEST) { | |
529 | ret = memory_post_tests(vstart, memsize); | |
530 | } else { /* POST_NORMAL */ | |
8d3fcb5e | 531 | ret = memory_post_test_regions(vstart, memsize); |
ad5bb451 | 532 | } |
28417030 YS |
533 | } while (!ret && |
534 | !arch_memory_test_advance(&vstart, &memsize, &phys_offset)); | |
535 | ||
536 | arch_memory_test_cleanup(&vstart, &memsize, &phys_offset); | |
537 | if (ret) | |
538 | arch_memory_failure_handle(); | |
ad5bb451 WD |
539 | |
540 | return ret; | |
541 | } | |
542 | ||
8d3fcb5e | 543 | #endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */ |