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ad5bb451 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
26 | /* | |
27 | * CPU test | |
28 | * Ternary instructions instr rA,rS,UIMM | |
29 | * | |
30 | * Logic instructions: ori, oris, xori, xoris | |
31 | * | |
32 | * The test contains a pre-built table of instructions, operands and | |
33 | * expected results. For each table entry, the test will cyclically use | |
34 | * different sets of operand registers and result registers. | |
35 | */ | |
36 | ||
ad5bb451 WD |
37 | #include <post.h> |
38 | #include "cpu_asm.h" | |
39 | ||
6d0f6bcf | 40 | #if CONFIG_POST & CONFIG_SYS_POST_CPU |
ad5bb451 WD |
41 | |
42 | extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); | |
43 | extern ulong cpu_post_makecr (long v); | |
44 | ||
45 | static struct cpu_post_threei_s | |
46 | { | |
47 | ulong cmd; | |
48 | ulong op1; | |
49 | ushort op2; | |
50 | ulong res; | |
51 | } cpu_post_threei_table[] = | |
52 | { | |
53 | { | |
53677ef1 | 54 | OP_ORI, |
ad5bb451 WD |
55 | 0x80000000, |
56 | 0xffff, | |
57 | 0x8000ffff | |
58 | }, | |
59 | { | |
53677ef1 | 60 | OP_ORIS, |
ad5bb451 WD |
61 | 0x00008000, |
62 | 0xffff, | |
63 | 0xffff8000 | |
64 | }, | |
65 | { | |
53677ef1 | 66 | OP_XORI, |
ad5bb451 WD |
67 | 0x8000ffff, |
68 | 0xffff, | |
69 | 0x80000000 | |
70 | }, | |
71 | { | |
53677ef1 | 72 | OP_XORIS, |
ad5bb451 WD |
73 | 0x00008000, |
74 | 0xffff, | |
75 | 0xffff8000 | |
76 | }, | |
77 | }; | |
78 | static unsigned int cpu_post_threei_size = | |
79 | sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s); | |
80 | ||
81 | int cpu_post_test_threei (void) | |
82 | { | |
83 | int ret = 0; | |
84 | unsigned int i, reg; | |
85 | int flag = disable_interrupts(); | |
86 | ||
87 | for (i = 0; i < cpu_post_threei_size && ret == 0; i++) | |
88 | { | |
89 | struct cpu_post_threei_s *test = cpu_post_threei_table + i; | |
90 | ||
91 | for (reg = 0; reg < 32 && ret == 0; reg++) | |
92 | { | |
93 | unsigned int reg0 = (reg + 0) % 32; | |
94 | unsigned int reg1 = (reg + 1) % 32; | |
95 | unsigned int stk = reg < 16 ? 31 : 15; | |
53677ef1 | 96 | unsigned long code[] = |
ad5bb451 WD |
97 | { |
98 | ASM_STW(stk, 1, -4), | |
99 | ASM_ADDI(stk, 1, -16), | |
100 | ASM_STW(3, stk, 8), | |
101 | ASM_STW(reg0, stk, 4), | |
102 | ASM_STW(reg1, stk, 0), | |
103 | ASM_LWZ(reg0, stk, 8), | |
104 | ASM_11IX(test->cmd, reg1, reg0, test->op2), | |
105 | ASM_STW(reg1, stk, 8), | |
106 | ASM_LWZ(reg1, stk, 0), | |
107 | ASM_LWZ(reg0, stk, 4), | |
108 | ASM_LWZ(3, stk, 8), | |
109 | ASM_ADDI(1, stk, 16), | |
110 | ASM_LWZ(stk, 1, -4), | |
111 | ASM_BLR, | |
112 | }; | |
113 | ulong res; | |
114 | ulong cr; | |
115 | ||
53677ef1 | 116 | cr = 0; |
ad5bb451 WD |
117 | cpu_post_exec_21 (code, & cr, & res, test->op1); |
118 | ||
119 | ret = res == test->res && cr == 0 ? 0 : -1; | |
120 | ||
121 | if (ret != 0) | |
122 | { | |
123 | post_log ("Error at threei test %d !\n", i); | |
124 | } | |
125 | } | |
126 | } | |
127 | ||
128 | if (flag) | |
53677ef1 | 129 | enable_interrupts(); |
ad5bb451 WD |
130 | |
131 | return ret; | |
132 | } | |
133 | ||
134 | #endif |