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07c04875 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
26 | /* | |
27 | * SPR test | |
28 | * | |
29 | * The test checks the contents of Special Purpose Registers (SPR) listed | |
30 | * in the spr_test_list array below. | |
31 | * Each SPR value is read using mfspr instruction, some bits are masked | |
32 | * according to the table and the resulting value is compared to the | |
33 | * corresponding table value. | |
34 | */ | |
35 | ||
36 | #ifdef CONFIG_POST | |
37 | ||
38 | #include <post.h> | |
39 | ||
40 | #if CONFIG_POST & CFG_POST_SPR | |
41 | ||
42 | static struct | |
43 | { | |
44 | int number; | |
45 | char * name; | |
46 | unsigned long mask; | |
47 | unsigned long value; | |
48 | } spr_test_list [] = { | |
49 | /* Standard Special-Purpose Registers */ | |
50 | ||
8bde7f77 WD |
51 | {1, "XER", 0x00000000, 0x00000000}, |
52 | {8, "LR", 0x00000000, 0x00000000}, | |
53 | {9, "CTR", 0x00000000, 0x00000000}, | |
54 | {18, "DSISR", 0x00000000, 0x00000000}, | |
55 | {19, "DAR", 0x00000000, 0x00000000}, | |
56 | {22, "DEC", 0x00000000, 0x00000000}, | |
57 | {26, "SRR0", 0x00000000, 0x00000000}, | |
58 | {27, "SRR1", 0x00000000, 0x00000000}, | |
59 | {272, "SPRG0", 0x00000000, 0x00000000}, | |
60 | {273, "SPRG1", 0x00000000, 0x00000000}, | |
61 | {274, "SPRG2", 0x00000000, 0x00000000}, | |
62 | {275, "SPRG3", 0x00000000, 0x00000000}, | |
63 | {287, "PVR", 0xFFFF0000, 0x00500000}, | |
07c04875 WD |
64 | |
65 | /* Additional Special-Purpose Registers */ | |
66 | ||
8bde7f77 WD |
67 | {144, "CMPA", 0x00000000, 0x00000000}, |
68 | {145, "CMPB", 0x00000000, 0x00000000}, | |
69 | {146, "CMPC", 0x00000000, 0x00000000}, | |
70 | {147, "CMPD", 0x00000000, 0x00000000}, | |
71 | {148, "ICR", 0xFFFFFFFF, 0x00000000}, | |
72 | {149, "DER", 0x00000000, 0x00000000}, | |
73 | {150, "COUNTA", 0xFFFFFFFF, 0x00000000}, | |
74 | {151, "COUNTB", 0xFFFFFFFF, 0x00000000}, | |
75 | {152, "CMPE", 0x00000000, 0x00000000}, | |
76 | {153, "CMPF", 0x00000000, 0x00000000}, | |
77 | {154, "CMPG", 0x00000000, 0x00000000}, | |
78 | {155, "CMPH", 0x00000000, 0x00000000}, | |
79 | {156, "LCTRL1", 0xFFFFFFFF, 0x00000000}, | |
80 | {157, "LCTRL2", 0xFFFFFFFF, 0x00000000}, | |
81 | {158, "ICTRL", 0xFFFFFFFF, 0x00000007}, | |
82 | {159, "BAR", 0x00000000, 0x00000000}, | |
83 | {630, "DPDR", 0x00000000, 0x00000000}, | |
84 | {631, "DPIR", 0x00000000, 0x00000000}, | |
85 | {638, "IMMR", 0xFFFF0000, CFG_IMMR }, | |
86 | {560, "IC_CST", 0x8E380000, 0x00000000}, | |
87 | {561, "IC_ADR", 0x00000000, 0x00000000}, | |
88 | {562, "IC_DAT", 0x00000000, 0x00000000}, | |
89 | {568, "DC_CST", 0xEF380000, 0x00000000}, | |
90 | {569, "DC_ADR", 0x00000000, 0x00000000}, | |
91 | {570, "DC_DAT", 0x00000000, 0x00000000}, | |
92 | {784, "MI_CTR", 0xFFFFFFFF, 0x00000000}, | |
93 | {786, "MI_AP", 0x00000000, 0x00000000}, | |
94 | {787, "MI_EPN", 0x00000000, 0x00000000}, | |
95 | {789, "MI_TWC", 0xFFFFFE02, 0x00000000}, | |
96 | {790, "MI_RPN", 0x00000000, 0x00000000}, | |
97 | {816, "MI_DBCAM", 0x00000000, 0x00000000}, | |
98 | {817, "MI_DBRAM0", 0x00000000, 0x00000000}, | |
99 | {818, "MI_DBRAM1", 0x00000000, 0x00000000}, | |
100 | {792, "MD_CTR", 0xFFFFFFFF, 0x04000000}, | |
101 | {793, "M_CASID", 0xFFFFFFF0, 0x00000000}, | |
102 | {794, "MD_AP", 0x00000000, 0x00000000}, | |
103 | {795, "MD_EPN", 0x00000000, 0x00000000}, | |
104 | {796, "M_TWB", 0x00000003, 0x00000000}, | |
105 | {797, "MD_TWC", 0x00000003, 0x00000000}, | |
106 | {798, "MD_RPN", 0x00000000, 0x00000000}, | |
107 | {799, "M_TW", 0x00000000, 0x00000000}, | |
108 | {824, "MD_DBCAM", 0x00000000, 0x00000000}, | |
109 | {825, "MD_DBRAM0", 0x00000000, 0x00000000}, | |
110 | {826, "MD_DBRAM1", 0x00000000, 0x00000000}, | |
07c04875 WD |
111 | }; |
112 | ||
113 | static int spr_test_list_size = | |
114 | sizeof (spr_test_list) / sizeof (spr_test_list[0]); | |
115 | ||
116 | int spr_post_test (int flags) | |
117 | { | |
118 | int ret = 0; | |
119 | int ic = icache_status (); | |
120 | int i; | |
121 | ||
122 | unsigned long code[] = { | |
123 | 0x7c6002a6, /* mfspr r3,SPR */ | |
124 | 0x4e800020 /* blr */ | |
125 | }; | |
126 | unsigned long (*get_spr) (void) = (void *) code; | |
127 | ||
128 | if (ic) | |
129 | icache_disable (); | |
130 | ||
131 | for (i = 0; i < spr_test_list_size; i++) { | |
132 | int num = spr_test_list[i].number; | |
133 | ||
134 | /* mfspr r3,num */ | |
135 | code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); | |
136 | ||
137 | if ((get_spr () & spr_test_list[i].mask) != | |
138 | (spr_test_list[i].value & spr_test_list[i].mask)) { | |
139 | post_log ("The value of %s special register " | |
140 | "is incorrect: 0x%08X\n", | |
141 | spr_test_list[i].name, get_spr ()); | |
142 | ret = -1; | |
143 | } | |
144 | } | |
145 | ||
146 | if (ic) | |
147 | icache_enable (); | |
148 | ||
149 | return ret; | |
150 | } | |
151 | #endif /* CONFIG_POST & CFG_POST_SPR */ | |
152 | #endif /* CONFIG_POST */ |