projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| ecf3b270 SL |
1 | From 75ff580829aa8e444771f1e162e0d46a3e5452cd Mon Sep 17 00:00:00 2001 |
| 2 | From: Vladimir Murzin <vladimir.murzin@arm.com> | |
| 3 | Date: Wed, 20 Feb 2019 11:43:05 +0000 | |
| 4 | Subject: arm64: Relax GIC version check during early boot | |
| 5 | ||
| 6 | [ Upstream commit 74698f6971f25d045301139413578865fc2bd8f9 ] | |
| 7 | ||
| 8 | Updates to the GIC architecture allow ID_AA64PFR0_EL1.GIC to have | |
| 9 | values other than 0 or 1. At the moment, Linux is quite strict in the | |
| 10 | way it handles this field at early boot stage (cpufeature is fine) and | |
| 11 | will refuse to use the system register CPU interface if it doesn't | |
| 12 | find the value 1. | |
| 13 | ||
| 14 | Fixes: 021f653791ad17e03f98aaa7fb933816ae16f161 ("irqchip: gic-v3: Initial support for GICv3") | |
| 15 | Reported-by: Chase Conklin <Chase.Conklin@arm.com> | |
| 16 | Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> | |
| 17 | Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> | |
| 18 | Signed-off-by: Will Deacon <will.deacon@arm.com> | |
| 19 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
| 20 | --- | |
| 21 | arch/arm64/kernel/head.S | 3 +-- | |
| 22 | 1 file changed, 1 insertion(+), 2 deletions(-) | |
| 23 | ||
| 24 | diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S | |
| 25 | index ec393275ba04..1371542de0d3 100644 | |
| 26 | --- a/arch/arm64/kernel/head.S | |
| 27 | +++ b/arch/arm64/kernel/head.S | |
| 28 | @@ -442,8 +442,7 @@ set_hcr: | |
| 29 | /* GICv3 system register access */ | |
| 30 | mrs x0, id_aa64pfr0_el1 | |
| 31 | ubfx x0, x0, #24, #4 | |
| 32 | - cmp x0, #1 | |
| 33 | - b.ne 3f | |
| 34 | + cbz x0, 3f | |
| 35 | ||
| 36 | mrs_s x0, SYS_ICC_SRE_EL2 | |
| 37 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 | |
| 38 | -- | |
| 39 | 2.19.1 | |
| 40 |