]>
Commit | Line | Data |
---|---|---|
1f91e7a4 GKH |
1 | From foo@baz Tue 14 May 2019 08:29:35 PM CEST |
2 | From: Tim Chen <tim.c.chen@linux.intel.com> | |
3 | Date: Sun, 25 Nov 2018 19:33:35 +0100 | |
4 | Subject: x86/speculation: Reorganize speculation control MSRs update | |
5 | ||
6 | From: Tim Chen <tim.c.chen@linux.intel.com> | |
7 | ||
8 | commit 01daf56875ee0cd50ed496a09b20eb369b45dfa5 upstream. | |
9 | ||
10 | The logic to detect whether there's a change in the previous and next | |
11 | task's flag relevant to update speculation control MSRs is spread out | |
12 | across multiple functions. | |
13 | ||
14 | Consolidate all checks needed for updating speculation control MSRs into | |
15 | the new __speculation_ctrl_update() helper function. | |
16 | ||
17 | This makes it easy to pick the right speculation control MSR and the bits | |
18 | in MSR_IA32_SPEC_CTRL that need updating based on TIF flags changes. | |
19 | ||
20 | Originally-by: Thomas Lendacky <Thomas.Lendacky@amd.com> | |
21 | Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> | |
22 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | |
23 | Reviewed-by: Ingo Molnar <mingo@kernel.org> | |
24 | Cc: Peter Zijlstra <peterz@infradead.org> | |
25 | Cc: Andy Lutomirski <luto@kernel.org> | |
26 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
27 | Cc: Jiri Kosina <jkosina@suse.cz> | |
28 | Cc: Tom Lendacky <thomas.lendacky@amd.com> | |
29 | Cc: Josh Poimboeuf <jpoimboe@redhat.com> | |
30 | Cc: Andrea Arcangeli <aarcange@redhat.com> | |
31 | Cc: David Woodhouse <dwmw@amazon.co.uk> | |
32 | Cc: Andi Kleen <ak@linux.intel.com> | |
33 | Cc: Dave Hansen <dave.hansen@intel.com> | |
34 | Cc: Casey Schaufler <casey.schaufler@intel.com> | |
35 | Cc: Asit Mallick <asit.k.mallick@intel.com> | |
36 | Cc: Arjan van de Ven <arjan@linux.intel.com> | |
37 | Cc: Jon Masters <jcm@redhat.com> | |
38 | Cc: Waiman Long <longman9394@gmail.com> | |
39 | Cc: Greg KH <gregkh@linuxfoundation.org> | |
40 | Cc: Dave Stewart <david.c.stewart@intel.com> | |
41 | Cc: Kees Cook <keescook@chromium.org> | |
42 | Link: https://lkml.kernel.org/r/20181125185004.151077005@linutronix.de | |
43 | Signed-off-by: Ben Hutchings <ben@decadent.org.uk> | |
44 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
45 | --- | |
46 | arch/x86/kernel/process.c | 42 +++++++++++++++++++++++++++--------------- | |
47 | 1 file changed, 27 insertions(+), 15 deletions(-) | |
48 | ||
49 | --- a/arch/x86/kernel/process.c | |
50 | +++ b/arch/x86/kernel/process.c | |
51 | @@ -317,27 +317,40 @@ static __always_inline void amd_set_ssb_ | |
52 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
53 | } | |
54 | ||
55 | -static __always_inline void spec_ctrl_update_msr(unsigned long tifn) | |
56 | +/* | |
57 | + * Update the MSRs managing speculation control, during context switch. | |
58 | + * | |
59 | + * tifp: Previous task's thread flags | |
60 | + * tifn: Next task's thread flags | |
61 | + */ | |
62 | +static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
63 | + unsigned long tifn) | |
64 | { | |
65 | - u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn); | |
66 | + u64 msr = x86_spec_ctrl_base; | |
67 | + bool updmsr = false; | |
68 | ||
69 | - wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
70 | -} | |
71 | + /* If TIF_SSBD is different, select the proper mitigation method */ | |
72 | + if ((tifp ^ tifn) & _TIF_SSBD) { | |
73 | + if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
74 | + amd_set_ssb_virt_state(tifn); | |
75 | + } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { | |
76 | + amd_set_core_ssb_state(tifn); | |
77 | + } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || | |
78 | + static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
79 | + msr |= ssbd_tif_to_spec_ctrl(tifn); | |
80 | + updmsr = true; | |
81 | + } | |
82 | + } | |
83 | ||
84 | -static __always_inline void __speculation_ctrl_update(unsigned long tifn) | |
85 | -{ | |
86 | - if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
87 | - amd_set_ssb_virt_state(tifn); | |
88 | - else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
89 | - amd_set_core_ssb_state(tifn); | |
90 | - else | |
91 | - spec_ctrl_update_msr(tifn); | |
92 | + if (updmsr) | |
93 | + wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
94 | } | |
95 | ||
96 | void speculation_ctrl_update(unsigned long tif) | |
97 | { | |
98 | + /* Forced update. Make sure all relevant TIF flags are different */ | |
99 | preempt_disable(); | |
100 | - __speculation_ctrl_update(tif); | |
101 | + __speculation_ctrl_update(~tif, tif); | |
102 | preempt_enable(); | |
103 | } | |
104 | ||
105 | @@ -370,8 +383,7 @@ void __switch_to_xtra(struct task_struct | |
106 | if ((tifp ^ tifn) & _TIF_NOTSC) | |
107 | cr4_toggle_bits(X86_CR4_TSD); | |
108 | ||
109 | - if ((tifp ^ tifn) & _TIF_SSBD) | |
110 | - __speculation_ctrl_update(tifn); | |
111 | + __speculation_ctrl_update(tifp, tifn); | |
112 | } | |
113 | ||
114 | /* |