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6fa88700 GKH |
1 | From 902db28e44ba5d2f93b5b51d79d11a8905b0a503 Mon Sep 17 00:00:00 2001 |
2 | From: Ashok Raj <ashok.raj@intel.com> | |
3 | Date: Wed, 28 Feb 2018 11:28:41 +0100 | |
4 | Subject: [PATCH 08/76] x86/microcode/intel: Check microcode revision before | |
5 | updating sibling threads | |
6 | ||
7 | commit c182d2b7d0ca48e0d6ff16f7d883161238c447ed upstream. | |
8 | ||
9 | After updating microcode on one of the threads of a core, the other | |
10 | thread sibling automatically gets the update since the microcode | |
11 | resources on a hyperthreaded core are shared between the two threads. | |
12 | ||
13 | Check the microcode revision on the CPU before performing a microcode | |
14 | update and thus save us the WRMSR 0x79 because it is a particularly | |
15 | expensive operation. | |
16 | ||
17 | [ Borislav: Massage changelog and coding style. ] | |
18 | ||
19 | Signed-off-by: Ashok Raj <ashok.raj@intel.com> | |
20 | Signed-off-by: Borislav Petkov <bp@suse.de> | |
21 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | |
22 | Tested-by: Tom Lendacky <thomas.lendacky@amd.com> | |
23 | Tested-by: Ashok Raj <ashok.raj@intel.com> | |
24 | Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com> | |
25 | Link: http://lkml.kernel.org/r/1519352533-15992-2-git-send-email-ashok.raj@intel.com | |
26 | Link: https://lkml.kernel.org/r/20180228102846.13447-3-bp@alien8.de | |
27 | [bwh: Backported to 4.9: return 0 in this case] | |
28 | Signed-off-by: Ben Hutchings <ben@decadent.org.uk> | |
29 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
30 | --- | |
31 | arch/x86/kernel/cpu/microcode/intel.c | 27 ++++++++++++++++++++++++--- | |
32 | 1 file changed, 24 insertions(+), 3 deletions(-) | |
33 | ||
34 | diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c | |
35 | index af8fc3bc706b..8faa5fa208d6 100644 | |
36 | --- a/arch/x86/kernel/cpu/microcode/intel.c | |
37 | +++ b/arch/x86/kernel/cpu/microcode/intel.c | |
38 | @@ -617,6 +617,17 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | |
39 | if (!mc) | |
40 | return 0; | |
41 | ||
42 | + /* | |
43 | + * Save us the MSR write below - which is a particular expensive | |
44 | + * operation - when the other hyperthread has updated the microcode | |
45 | + * already. | |
46 | + */ | |
47 | + rev = intel_get_microcode_revision(); | |
48 | + if (rev >= mc->hdr.rev) { | |
49 | + uci->cpu_sig.rev = rev; | |
50 | + return 0; | |
51 | + } | |
52 | + | |
53 | /* write microcode via MSR 0x79 */ | |
54 | native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); | |
55 | ||
56 | @@ -891,7 +902,7 @@ static int apply_microcode_intel(int cpu) | |
57 | { | |
58 | struct microcode_intel *mc; | |
59 | struct ucode_cpu_info *uci; | |
60 | - struct cpuinfo_x86 *c; | |
61 | + struct cpuinfo_x86 *c = &cpu_data(cpu); | |
62 | static int prev_rev; | |
63 | u32 rev; | |
64 | ||
65 | @@ -912,6 +923,18 @@ static int apply_microcode_intel(int cpu) | |
66 | if (!get_matching_mc(mc, cpu)) | |
67 | return 0; | |
68 | ||
69 | + /* | |
70 | + * Save us the MSR write below - which is a particular expensive | |
71 | + * operation - when the other hyperthread has updated the microcode | |
72 | + * already. | |
73 | + */ | |
74 | + rev = intel_get_microcode_revision(); | |
75 | + if (rev >= mc->hdr.rev) { | |
76 | + uci->cpu_sig.rev = rev; | |
77 | + c->microcode = rev; | |
78 | + return 0; | |
79 | + } | |
80 | + | |
81 | /* write microcode via MSR 0x79 */ | |
82 | wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); | |
83 | ||
84 | @@ -932,8 +955,6 @@ static int apply_microcode_intel(int cpu) | |
85 | prev_rev = rev; | |
86 | } | |
87 | ||
88 | - c = &cpu_data(cpu); | |
89 | - | |
90 | uci->cpu_sig.rev = rev; | |
91 | c->microcode = rev; | |
92 | ||
93 | -- | |
94 | 2.21.0 | |
95 |