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[thirdparty/kernel/stable-queue.git] / releases / 2.6.20.14 / iop13xx-fix-i-o-address-translation.patch
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bb4b1d3a
CW		 1From stable-bounces@linux.kernel.org Wed May 2 11:45:25 2007
2From: Dan Williams <dan.j.williams@intel.com>
3To: stable@kernel.org
4Date: Wed, 02 May 2007 11:43:19 -0700
5Message-ID: <20070502184319.10289.25924.stgit@dwillia2-linux.ch.intel.com>
6Cc: rmk@arm.linux.org.uk
7Subject: iop13xx: fix i/o address translation
8
9PCI devices were being programmed with an incorrect base address value.
10This patch moves I/O space into a 16-bit addressable region and corrects
11the i/o offset.
12
13Much thanks to Martin Michlmayr for tracking this issue and testing
14debug patches.
15
16Cc: Martin Michlmayr <tbm@cyrius.com>
17Cc: Russell King <rmk+kernel@arm.linux.org.uk>
18Signed-off-by: Dan Williams <dan.j.williams@intel.com>
19Signed-off-by: Chris Wright <chrisw@sous-sol.org>
86a234e6 20Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
bb4b1d3a
CW		 21---
22
23 arch/arm/mach-iop13xx/pci.c | 8 ++++----
24 include/asm-arm/arch-iop13xx/iop13xx.h | 22 +++++++++++++---------
25 2 files changed, 17 insertions(+), 13 deletions(-)
26
74c4ce79
CW		 27--- linux-2.6.20.13.orig/arch/arm/mach-iop13xx/pci.c
28+++ linux-2.6.20.13/arch/arm/mach-iop13xx/pci.c
bb4b1d3a
CW		 29@@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci
30 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
31 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
32
33- res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
34+ res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
35 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
36 res[0].name = "IQ81340 ATUX PCI I/O Space";
37 res[0].flags = IORESOURCE_IO;
38@@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci
39 res[1].name = "IQ81340 ATUX PCI Memory Space";
40 res[1].flags = IORESOURCE_MEM;
41 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
42- sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
43+ sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
44 break;
45 case IOP13XX_INIT_ATU_ATUE:
46 /* Note: the function number field in the PCSR is ro */
47@@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci
48
49 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
50
51- res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
52+ res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
53 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
54 res[0].name = "IQ81340 ATUE PCI I/O Space";
55 res[0].flags = IORESOURCE_IO;
56@@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci
57 res[1].name = "IQ81340 ATUE PCI Memory Space";
58 res[1].flags = IORESOURCE_MEM;
59 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
60- sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
61+ sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
62 sys->map_irq = iop13xx_pcie_map_irq;
63 break;
64 default:
74c4ce79
CW		 65--- linux-2.6.20.13.orig/include/asm-arm/arch-iop13xx/iop13xx.h
66+++ linux-2.6.20.13/include/asm-arm/arch-iop13xx/iop13xx.h
bb4b1d3a
CW		 67@@ -55,19 +55,24 @@ static inline int iop13xx_cpu_id(void)
68 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
69
70 /* PCI MAP
71- * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
72- * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
73-*/
74+ * bus range cpu phys cpu virt note
75+ * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
76+ * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
77+ * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
78+ *
79+ * IO MAP
80+ * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
81+ * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
82+ */
83 #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
84 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
85 #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
86-#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
87+#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
88+#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
89 #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
90 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
91 #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
92 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
93-#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
94- IOP13XX_PCIX_LOWER_IO_BA)
95 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
96 (IOP13XX_PCIX_LOWER_IO_PA\
97 - IOP13XX_PCIX_LOWER_IO_VA))
98@@ -93,15 +98,14 @@ static inline int iop13xx_cpu_id(void)
99 #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
100 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
101 #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
102-#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
103+#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
104+#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
105 #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
106 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
107 #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
108 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
109 #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
110 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
111-#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
112- IOP13XX_PCIE_LOWER_IO_BA)
113 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
114 (IOP13XX_PCIE_LOWER_IO_PA\
115 - IOP13XX_PCIE_LOWER_IO_VA))
Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git