projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| ca940317 GKH |
1 | From 8ae06d223f8203c72104e5c0c4ee49a000aedb42 Mon Sep 17 00:00:00 2001 |
| 2 | From: Shaohua Li <shaohua.li@intel.com> | |
| 3 | Date: Fri, 5 Mar 2010 08:59:32 +0800 | |
| 4 | Subject: x86-32, resume: do a global tlb flush in S4 resume | |
| 5 | ||
| 6 | From: Shaohua Li <shaohua.li@intel.com> | |
| 7 | ||
| 8 | commit 8ae06d223f8203c72104e5c0c4ee49a000aedb42 upstream. | |
| 9 | ||
| 10 | Colin King reported a strange oops in S4 resume code path (see below). The test | |
| 11 | system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. | |
| 12 | The oops always happen a virtual address 0xc03ff000, which is mapped to the | |
| 13 | last 4k of first 4M memory. Doing a global tlb flush fixes the issue. | |
| 14 | ||
| 15 | EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 | |
| 16 | EIP is at copy_loop+0xe/0x15 | |
| 17 | EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c | |
| 18 | ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 | |
| 19 | DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 | |
| 20 | ... | |
| 21 | ... | |
| 22 | CR2: 00000000c03ff000 | |
| 23 | ||
| 24 | Tested-by: Colin Ian King <colin.king@canonical.com> | |
| 25 | Signed-off-by: Shaohua Li <shaohua.li@intel.com> | |
| 26 | LKML-Reference: <20100305005932.GA22675@sli10-desk.sh.intel.com> | |
| 27 | Acked-by: Rafael J. Wysocki <rjw@sisk.pl> | |
| 28 | Signed-off-by: H. Peter Anvin <hpa@zytor.com> | |
| 29 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
| 30 | ||
| 31 | --- | |
| 32 | arch/x86/power/hibernate_asm_32.S | 15 +++++++-------- | |
| 33 | 1 file changed, 7 insertions(+), 8 deletions(-) | |
| 34 | ||
| 35 | --- a/arch/x86/power/hibernate_asm_32.S | |
| 36 | +++ b/arch/x86/power/hibernate_asm_32.S | |
| 37 | @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) | |
| 38 | ret | |
| 39 | ||
| 40 | ENTRY(restore_image) | |
| 41 | + movl mmu_cr4_features, %ecx | |
| 42 | movl resume_pg_dir, %eax | |
| 43 | subl $__PAGE_OFFSET, %eax | |
| 44 | movl %eax, %cr3 | |
| 45 | ||
| 46 | + jecxz 1f # cr4 Pentium and higher, skip if zero | |
| 47 | + andl $~(X86_CR4_PGE), %ecx | |
| 48 | + movl %ecx, %cr4; # turn off PGE | |
| 49 | + movl %cr3, %eax; # flush TLB | |
| 50 | + movl %eax, %cr3 | |
| 51 | +1: | |
| 52 | movl restore_pblist, %edx | |
| 53 | .p2align 4,,7 | |
| 54 | ||
| 55 | @@ -54,16 +61,8 @@ done: | |
| 56 | movl $swapper_pg_dir, %eax | |
| 57 | subl $__PAGE_OFFSET, %eax | |
| 58 | movl %eax, %cr3 | |
| 59 | - /* Flush TLB, including "global" things (vmalloc) */ | |
| 60 | movl mmu_cr4_features, %ecx | |
| 61 | jecxz 1f # cr4 Pentium and higher, skip if zero | |
| 62 | - movl %ecx, %edx | |
| 63 | - andl $~(X86_CR4_PGE), %edx | |
| 64 | - movl %edx, %cr4; # turn off PGE | |
| 65 | -1: | |
| 66 | - movl %cr3, %eax; # flush TLB | |
| 67 | - movl %eax, %cr3 | |
| 68 | - jecxz 1f # cr4 Pentium and higher, skip if zero | |
| 69 | movl %ecx, %cr4; # turn PGE back on | |
| 70 | 1: | |
| 71 |