projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 7381a876 GKH |
1 | From 897de50e08937663912c86fb12ad7f708af2386c Mon Sep 17 00:00:00 2001 |
| 2 | From: Borislav Petkov <borislav.petkov@amd.com> | |
| 3 | Date: Fri, 22 Jan 2010 16:01:06 +0100 | |
| 4 | Subject: x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches | |
| 5 | ||
| 6 | From: Borislav Petkov <borislav.petkov@amd.com> | |
| 7 | ||
| 8 | commit 897de50e08937663912c86fb12ad7f708af2386c upstream. | |
| 9 | ||
| 10 | The cache_disable_[01] attribute in | |
| 11 | ||
| 12 | /sys/devices/system/cpu/cpu?/cache/index[0-3]/ | |
| 13 | ||
| 14 | is enabled on all cache levels although only L3 supports it. Add it only | |
| 15 | to the cache level that actually supports it. | |
| 16 | ||
| 17 | Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> | |
| 18 | LKML-Reference: <1264172467-25155-5-git-send-email-bp@amd64.org> | |
| 19 | Signed-off-by: H. Peter Anvin <hpa@zytor.com> | |
| 20 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
| 21 | ||
| 22 | --- | |
| 23 | arch/x86/kernel/cpu/intel_cacheinfo.c | 35 +++++++++++++++++++++++++--------- | |
| 24 | 1 file changed, 26 insertions(+), 9 deletions(-) | |
| 25 | ||
| 26 | --- a/arch/x86/kernel/cpu/intel_cacheinfo.c | |
| 27 | +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |
| 28 | @@ -829,16 +829,24 @@ static struct _cache_attr cache_disable_ | |
| 29 | static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, | |
| 30 | show_cache_disable_1, store_cache_disable_1); | |
| 31 | ||
| 32 | +#define DEFAULT_SYSFS_CACHE_ATTRS \ | |
| 33 | + &type.attr, \ | |
| 34 | + &level.attr, \ | |
| 35 | + &coherency_line_size.attr, \ | |
| 36 | + &physical_line_partition.attr, \ | |
| 37 | + &ways_of_associativity.attr, \ | |
| 38 | + &number_of_sets.attr, \ | |
| 39 | + &size.attr, \ | |
| 40 | + &shared_cpu_map.attr, \ | |
| 41 | + &shared_cpu_list.attr | |
| 42 | + | |
| 43 | static struct attribute *default_attrs[] = { | |
| 44 | - &type.attr, | |
| 45 | - &level.attr, | |
| 46 | - &coherency_line_size.attr, | |
| 47 | - &physical_line_partition.attr, | |
| 48 | - &ways_of_associativity.attr, | |
| 49 | - &number_of_sets.attr, | |
| 50 | - &size.attr, | |
| 51 | - &shared_cpu_map.attr, | |
| 52 | - &shared_cpu_list.attr, | |
| 53 | + DEFAULT_SYSFS_CACHE_ATTRS, | |
| 54 | + NULL | |
| 55 | +}; | |
| 56 | + | |
| 57 | +static struct attribute *default_l3_attrs[] = { | |
| 58 | + DEFAULT_SYSFS_CACHE_ATTRS, | |
| 59 | &cache_disable_0.attr, | |
| 60 | &cache_disable_1.attr, | |
| 61 | NULL | |
| 62 | @@ -931,6 +939,7 @@ static int __cpuinit cache_add_dev(struc | |
| 63 | unsigned int cpu = sys_dev->id; | |
| 64 | unsigned long i, j; | |
| 65 | struct _index_kobject *this_object; | |
| 66 | + struct _cpuid4_info *this_leaf; | |
| 67 | int retval; | |
| 68 | ||
| 69 | retval = cpuid4_cache_sysfs_init(cpu); | |
| 70 | @@ -949,6 +958,14 @@ static int __cpuinit cache_add_dev(struc | |
| 71 | this_object = INDEX_KOBJECT_PTR(cpu, i); | |
| 72 | this_object->cpu = cpu; | |
| 73 | this_object->index = i; | |
| 74 | + | |
| 75 | + this_leaf = CPUID4_INFO_IDX(cpu, i); | |
| 76 | + | |
| 77 | + if (this_leaf->can_disable) | |
| 78 | + ktype_cache.default_attrs = default_l3_attrs; | |
| 79 | + else | |
| 80 | + ktype_cache.default_attrs = default_attrs; | |
| 81 | + | |
| 82 | retval = kobject_init_and_add(&(this_object->kobj), | |
| 83 | &ktype_cache, | |
| 84 | per_cpu(cache_kobject, cpu), |