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Commit | Line | Data |
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45426b3c GKH |
1 | From 499a00e92dd9a75395081f595e681629eb1eebad Mon Sep 17 00:00:00 2001 |
2 | From: Darrick J. Wong <djwong@us.ibm.com> | |
3 | Date: Thu, 24 Jun 2010 14:26:47 -0700 | |
4 | Subject: x86, Calgary: Increase max PHB number | |
5 | ||
6 | From: Darrick J. Wong <djwong@us.ibm.com> | |
7 | ||
8 | commit 499a00e92dd9a75395081f595e681629eb1eebad upstream. | |
9 | ||
10 | Newer systems (x3950M2) can have 48 PHBs per chassis and 8 | |
11 | chassis, so bump the limits up and provide an explanation | |
12 | of the requirements for each class. | |
13 | ||
14 | Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> | |
15 | Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> | |
16 | Cc: Corinna Schultz <cschultz@linux.vnet.ibm.com> | |
17 | LKML-Reference: <20100624212647.GI15515@tux1.beaverton.ibm.com> | |
18 | [ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ] | |
19 | Signed-off-by: Ingo Molnar <mingo@elte.hu> | |
20 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
21 | ||
22 | --- | |
23 | arch/x86/kernel/pci-calgary_64.c | 15 ++++++++++----- | |
24 | 1 file changed, 10 insertions(+), 5 deletions(-) | |
25 | ||
26 | --- a/arch/x86/kernel/pci-calgary_64.c | |
27 | +++ b/arch/x86/kernel/pci-calgary_64.c | |
28 | @@ -102,11 +102,16 @@ int use_calgary __read_mostly = 0; | |
29 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
30 | #define PMR_HARDSTOP 0x20000000 | |
31 | ||
32 | -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
33 | -#define MAX_NUM_CHASSIS 8 /* max number of chassis */ | |
34 | -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ | |
35 | -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
36 | -#define PHBS_PER_CALGARY 4 | |
37 | +/* | |
38 | + * The maximum PHB bus number. | |
39 | + * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384 | |
40 | + * x3950M2: 4 chassis, 48 PHBs per chassis = 192 | |
41 | + * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 | |
42 | + * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 | |
43 | + */ | |
44 | +#define MAX_PHB_BUS_NUM 384 | |
45 | + | |
46 | +#define PHBS_PER_CALGARY 4 | |
47 | ||
48 | /* register offsets in Calgary's internal register space */ | |
49 | static const unsigned long tar_offsets[] = { |