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Commit | Line | Data |
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45426b3c GKH |
1 | From d596043d71ff0d7b3d0bead19b1d68c55f003093 Mon Sep 17 00:00:00 2001 |
2 | From: Darrick J. Wong <djwong@us.ibm.com> | |
3 | Date: Wed, 30 Jun 2010 17:45:19 -0700 | |
4 | Subject: x86, Calgary: Limit the max PHB number to 256 | |
5 | ||
6 | From: Darrick J. Wong <djwong@us.ibm.com> | |
7 | ||
8 | commit d596043d71ff0d7b3d0bead19b1d68c55f003093 upstream. | |
9 | ||
10 | The x3950 family can have as many as 256 PCI buses in a single system, so | |
11 | change the limits to the maximum. Since there can only be 256 PCI buses in one | |
12 | domain, we no longer need the BUG_ON check. | |
13 | ||
14 | Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> | |
15 | LKML-Reference: <20100701004519.GQ15515@tux1.beaverton.ibm.com> | |
16 | Signed-off-by: H. Peter Anvin <hpa@zytor.com> | |
17 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
18 | ||
19 | --- | |
20 | arch/x86/kernel/pci-calgary_64.c | 4 +--- | |
21 | 1 file changed, 1 insertion(+), 3 deletions(-) | |
22 | ||
23 | --- a/arch/x86/kernel/pci-calgary_64.c | |
24 | +++ b/arch/x86/kernel/pci-calgary_64.c | |
25 | @@ -109,7 +109,7 @@ int use_calgary __read_mostly = 0; | |
26 | * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 | |
27 | * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 | |
28 | */ | |
29 | -#define MAX_PHB_BUS_NUM 384 | |
30 | +#define MAX_PHB_BUS_NUM 256 | |
31 | ||
32 | #define PHBS_PER_CALGARY 4 | |
33 | ||
34 | @@ -1058,8 +1058,6 @@ static int __init calgary_init_one(struc | |
35 | struct iommu_table *tbl; | |
36 | int ret; | |
37 | ||
38 | - BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); | |
39 | - | |
40 | bbar = busno_to_bbar(dev->bus->number); | |
41 | ret = calgary_setup_tar(dev, bbar); | |
42 | if (ret) |