]>
Commit | Line | Data |
---|---|---|
01803d42 GKH |
1 | From 3fdbf004c1706480a7c7fac3c9d836fa6df20d7d Mon Sep 17 00:00:00 2001 |
2 | From: Andreas Herrmann <andreas.herrmann3@amd.com> | |
3 | Date: Thu, 30 Sep 2010 14:32:35 +0200 | |
4 | Subject: x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs | |
5 | ||
6 | From: Andreas Herrmann <andreas.herrmann3@amd.com> | |
7 | ||
8 | commit 3fdbf004c1706480a7c7fac3c9d836fa6df20d7d upstream. | |
9 | ||
10 | Instead of adapting the CPU family check in amd_special_default_mtrr() | |
11 | for each new CPU family assume that all new AMD CPUs support the | |
12 | necessary bits in SYS_CFG MSR. | |
13 | ||
14 | Tom2Enabled is architectural (defined in APM Vol.2). | |
15 | Tom2ForceMemTypeWB is defined in all BKDGs starting with K8 NPT. | |
16 | In pre K8-NPT BKDG this bit is reserved (read as zero). | |
17 | ||
18 | W/o this adaption Linux would unnecessarily complain about bad MTRR | |
19 | settings on every new AMD CPU family, e.g. | |
20 | ||
21 | [ 0.000000] WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 4863MB of RAM. | |
22 | ||
23 | Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> | |
24 | LKML-Reference: <20100930123235.GB20545@loge.amd.com> | |
25 | Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> | |
26 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
27 | ||
28 | --- | |
29 | arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- | |
30 | 1 file changed, 1 insertion(+), 1 deletion(-) | |
31 | ||
32 | --- a/arch/x86/kernel/cpu/mtrr/cleanup.c | |
33 | +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c | |
34 | @@ -827,7 +827,7 @@ int __init amd_special_default_mtrr(void | |
35 | ||
36 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
37 | return 0; | |
38 | - if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) | |
39 | + if (boot_cpu_data.x86 < 0xf) | |
40 | return 0; | |
41 | /* In case some hypervisor doesn't pass SYSCFG through: */ | |
42 | if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) |