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bcd4f083 GKH |
1 | From 3e57f1626b5febe5cc99aa6870377deef3ae03cc Mon Sep 17 00:00:00 2001 |
2 | From: Jarkko Nikula <jhnikula@gmail.com> | |
3 | Date: Mon, 11 Oct 2010 14:18:45 -0700 | |
4 | Subject: omap: dma: Fix buffering disable bit setting for omap24xx | |
5 | ||
6 | From: Jarkko Nikula <jhnikula@gmail.com> | |
7 | ||
8 | commit 3e57f1626b5febe5cc99aa6870377deef3ae03cc upstream. | |
9 | ||
10 | An errata workaround for omap24xx is not setting the buffering disable bit | |
11 | 25 what is the purpose but channel enable bit 7 instead. | |
12 | ||
13 | Background for this fix is the DMA stalling issue with ASoC omap-mcbsp | |
14 | driver. Peter Ujfalusi <peter.ujfalusi@nokia.com> has found an issue in | |
15 | recording that the DMA stall could happen if there were a buffer overrun | |
16 | detected by ALSA and the DMA was stopped and restarted due that. This | |
17 | problem is known to occur on both OMAP2420 and OMAP3. It can recover on | |
18 | OMAP3 after dma free, dma request and reconfiguration cycle. However, on | |
19 | OMAP2420 it seems that only way to recover is a reset. | |
20 | ||
21 | Problem was not visible before the commit c12abc0. That commit changed that | |
22 | the McBSP transmitter/receiver is released from reset only when needed. That | |
23 | is, only enabled McBSP transmitter without transmission was able to prevent | |
24 | this DMA stall problem in receiving side and underlying problem did not show | |
25 | up until now. McBSP transmitter itself seems to no be reason since DMA | |
26 | stall does not recover by enabling the transmission after stall. | |
27 | ||
28 | Debugging showed that there were a DMA write active during DMA stop time and | |
29 | it never completed even when restarting the DMA. Experimenting showed that | |
30 | the DMA buffering disable bit could be used to avoid stalling when using | |
31 | source synchronized transfers. However that could have performance hit and | |
32 | OMAP3 TRM states that buffering disable is not allowed for destination | |
33 | synchronized transfers so subsequent patch will implement a method to | |
34 | complete DMA writes when stopping. | |
35 | ||
36 | This patch is based on assumtion that complete lock-up on OMAP2420 is | |
37 | different but related problem. I don't have access to OMAP2420 errata but | |
38 | I believe this old workaround here is put for a reason but unfortunately | |
39 | a wrong bit was typed and problem showed up only now. | |
40 | ||
41 | Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> | |
42 | Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> | |
43 | Acked-by: Manjunath Kondaiah G <manjugk@ti.com> | |
44 | Signed-off-by: Tony Lindgren <tony@atomide.com> | |
45 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
46 | ||
47 | --- | |
48 | arch/arm/plat-omap/dma.c | 14 ++++++++++---- | |
49 | arch/arm/plat-omap/include/plat/dma.h | 1 + | |
50 | 2 files changed, 11 insertions(+), 4 deletions(-) | |
51 | ||
52 | --- a/arch/arm/plat-omap/dma.c | |
53 | +++ b/arch/arm/plat-omap/dma.c | |
54 | @@ -996,11 +996,17 @@ void omap_start_dma(int lch) | |
55 | l = dma_read(CCR(lch)); | |
56 | ||
57 | /* | |
58 | - * Errata: On ES2.0 BUFFERING disable must be set. | |
59 | - * This will always fail on ES1.0 | |
60 | + * Errata: Inter Frame DMA buffering issue (All OMAP2420 and | |
61 | + * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and | |
62 | + * bursting is enabled. This might result in data gets stalled in | |
63 | + * FIFO at the end of the block. | |
64 | + * Workaround: DMA channels must have BUFFERING_DISABLED bit set to | |
65 | + * guarantee no data will stay in the DMA FIFO in case inter frame | |
66 | + * buffering occurs. | |
67 | */ | |
68 | - if (cpu_is_omap24xx()) | |
69 | - l |= OMAP_DMA_CCR_EN; | |
70 | + if (cpu_is_omap2420() || | |
71 | + (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0))) | |
72 | + l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
73 | ||
74 | l |= OMAP_DMA_CCR_EN; | |
75 | dma_write(l, CCR(lch)); | |
76 | --- a/arch/arm/plat-omap/include/plat/dma.h | |
77 | +++ b/arch/arm/plat-omap/include/plat/dma.h | |
78 | @@ -335,6 +335,7 @@ | |
79 | #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) | |
80 | ||
81 | #define OMAP_DMA_CCR_EN (1 << 7) | |
82 | +#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) | |
83 | ||
84 | #define OMAP_DMA_DATA_TYPE_S8 0x00 | |
85 | #define OMAP_DMA_DATA_TYPE_S16 0x01 |