projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| cd2508b4 GKH |
1 | From 3bcf603f6d5d18bd9d076dc280de71f48add4101 Mon Sep 17 00:00:00 2001 |
| 2 | From: Jesse Barnes <jbarnes@virtuousgeek.org> | |
| 3 | Date: Wed, 27 Jul 2011 11:51:40 -0700 | |
| 4 | Subject: drm/i915: apply timing generator bug workaround on CPT and PPT | |
| 5 | ||
| 6 | From: Jesse Barnes <jbarnes@virtuousgeek.org> | |
| 7 | ||
| 8 | commit 3bcf603f6d5d18bd9d076dc280de71f48add4101 upstream. | |
| 9 | ||
| 10 | On CougarPoint and PantherPoint PCH chips, the timing generator may fail | |
| 11 | to start after DP training completes. This is due to a bug in the | |
| 12 | FDI autotraining detect logic (which will stall the timing generator and | |
| 13 | re-enable it once training completes), so disable it to avoid silent DP | |
| 14 | mode setting failures. | |
| 15 | ||
| 16 | Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> | |
| 17 | Signed-off-by: Keith Packard <keithp@keithp.com> | |
| 18 | Signed-off-by: Timo Aaltonen <timo.aaltonen@canonical.com> | |
| 19 | ||
| 20 | --- | |
| 21 | drivers/gpu/drm/i915/i915_reg.h | 5 +++++ | |
| 22 | drivers/gpu/drm/i915/intel_display.c | 4 ++++ | |
| 23 | 2 files changed, 9 insertions(+) | |
| 24 | ||
| 25 | --- a/drivers/gpu/drm/i915/i915_reg.h | |
| 26 | +++ b/drivers/gpu/drm/i915/i915_reg.h | |
| 27 | @@ -3113,6 +3113,11 @@ | |
| 28 | #define TRANS_6BPC (2<<5) | |
| 29 | #define TRANS_12BPC (3<<5) | |
| 30 | ||
| 31 | +#define _TRANSA_CHICKEN2 0xf0064 | |
| 32 | +#define _TRANSB_CHICKEN2 0xf1064 | |
| 33 | +#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) | |
| 34 | +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) | |
| 35 | + | |
| 36 | #define SOUTH_CHICKEN2 0xc2004 | |
| 37 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) | |
| 38 | ||
| 39 | --- a/drivers/gpu/drm/i915/intel_display.c | |
| 40 | +++ b/drivers/gpu/drm/i915/intel_display.c | |
| 41 | @@ -7584,6 +7584,7 @@ static void ibx_init_clock_gating(struct | |
| 42 | static void cpt_init_clock_gating(struct drm_device *dev) | |
| 43 | { | |
| 44 | struct drm_i915_private *dev_priv = dev->dev_private; | |
| 45 | + int pipe; | |
| 46 | ||
| 47 | /* | |
| 48 | * On Ibex Peak and Cougar Point, we need to disable clock | |
| 49 | @@ -7593,6 +7594,9 @@ static void cpt_init_clock_gating(struct | |
| 50 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
| 51 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
| 52 | DPLS_EDP_PPS_FIX_DIS); | |
| 53 | + /* Without this, mode sets may fail silently on FDI */ | |
| 54 | + for_each_pipe(pipe) | |
| 55 | + I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
| 56 | } | |
| 57 | ||
| 58 | static void ironlake_teardown_rc6(struct drm_device *dev) |