projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| db1faad6 GKH |
1 | From 98fb2cc115b4ef1ea0a2d87a170c183bd395dd6c Mon Sep 17 00:00:00 2001 |
| 2 | From: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | |
| 3 | Date: Mon, 24 Oct 2011 18:13:40 +0530 | |
| 4 | Subject: ath9k_hw: Update AR9485 initvals to fix system hang issue | |
| 5 | ||
| 6 | From: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | |
| 7 | ||
| 8 | commit 98fb2cc115b4ef1ea0a2d87a170c183bd395dd6c upstream. | |
| 9 | ||
| 10 | This patch fixes system hang when resuming from S3 state | |
| 11 | and lower rate sens failure issue. | |
| 12 | ||
| 13 | Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | |
| 14 | Signed-off-by: John W. Linville <linville@tuxdriver.com> | |
| 15 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
| 16 | ||
| 17 | --- | |
| 18 | drivers/net/wireless/ath/ath9k/ar9485_initvals.h | 10 +++++----- | |
| 19 | 1 file changed, 5 insertions(+), 5 deletions(-) | |
| 20 | ||
| 21 | --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h | |
| 22 | +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h | |
| 23 | @@ -521,7 +521,7 @@ static const u32 ar9485_1_1_radio_postam | |
| 24 | {0x000160ac, 0x24611800}, | |
| 25 | {0x000160b0, 0x03284f3e}, | |
| 26 | {0x0001610c, 0x00170000}, | |
| 27 | - {0x00016140, 0x10804008}, | |
| 28 | + {0x00016140, 0x50804008}, | |
| 29 | }; | |
| 30 | ||
| 31 | static const u32 ar9485_1_1_mac_postamble[][5] = { | |
| 32 | @@ -603,7 +603,7 @@ static const u32 ar9485_1_1_radio_core[] | |
| 33 | ||
| 34 | static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { | |
| 35 | /* Addr allmodes */ | |
| 36 | - {0x00018c00, 0x10052e5e}, | |
| 37 | + {0x00018c00, 0x18052e5e}, | |
| 38 | {0x00018c04, 0x000801d8}, | |
| 39 | {0x00018c08, 0x0000080c}, | |
| 40 | }; | |
| 41 | @@ -776,7 +776,7 @@ static const u32 ar9485_modes_green_ob_d | |
| 42 | ||
| 43 | static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { | |
| 44 | /* Addr allmodes */ | |
| 45 | - {0x00018c00, 0x10013e5e}, | |
| 46 | + {0x00018c00, 0x18013e5e}, | |
| 47 | {0x00018c04, 0x000801d8}, | |
| 48 | {0x00018c08, 0x0000080c}, | |
| 49 | }; | |
| 50 | @@ -882,7 +882,7 @@ static const u32 ar9485_fast_clock_1_1_b | |
| 51 | ||
| 52 | static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { | |
| 53 | /* Addr allmodes */ | |
| 54 | - {0x00018c00, 0x10012e5e}, | |
| 55 | + {0x00018c00, 0x18012e5e}, | |
| 56 | {0x00018c04, 0x000801d8}, | |
| 57 | {0x00018c08, 0x0000080c}, | |
| 58 | }; | |
| 59 | @@ -1021,7 +1021,7 @@ static const u32 ar9485_common_rx_gain_1 | |
| 60 | ||
| 61 | static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { | |
| 62 | /* Addr allmodes */ | |
| 63 | - {0x00018c00, 0x10053e5e}, | |
| 64 | + {0x00018c00, 0x18053e5e}, | |
| 65 | {0x00018c04, 0x000801d8}, | |
| 66 | {0x00018c08, 0x0000080c}, | |
| 67 | }; |