projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 14818f4b GKH |
1 | From 6571534b600b8ca1936ff5630b9e0947f21faf16 Mon Sep 17 00:00:00 2001 |
| 2 | From: Paul Fertser <fercerpav@gmail.com> | |
| 3 | Date: Mon, 10 Oct 2011 11:19:23 +0400 | |
| 4 | Subject: plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desired | |
| 5 | ||
| 6 | From: Paul Fertser <fercerpav@gmail.com> | |
| 7 | ||
| 8 | commit 6571534b600b8ca1936ff5630b9e0947f21faf16 upstream. | |
| 9 | ||
| 10 | To configure pads during the initialisation a set of special constants | |
| 11 | is used, e.g. | |
| 12 | #define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) | |
| 13 | ||
| 14 | The problem is that no pull-up/down is getting activated unless both | |
| 15 | PAD_CTL_PUE (pull-up enable) and PAD_CTL_PKE (pull/keeper module | |
| 16 | enable) set. This is clearly stated in the i.MX25 datasheet and is | |
| 17 | confirmed by the measurements on hardware. This leads to some rather | |
| 18 | hard to understand bugs such as misdetecting an absent ethernet PHY (a | |
| 19 | real bug i had), unstable data transfer etc. This might affect mx25, | |
| 20 | mx35, mx50, mx51 and mx53 SoCs. | |
| 21 | ||
| 22 | It's reasonable to expect that if the pullup value is specified, the | |
| 23 | intention was to have it actually active, so we implicitly add the | |
| 24 | needed bits. | |
| 25 | ||
| 26 | Signed-off-by: Paul Fertser <fercerpav@gmail.com> | |
| 27 | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> | |
| 28 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
| 29 | ||
| 30 | --- | |
| 31 | arch/arm/plat-mxc/include/mach/iomux-v3.h | 10 +++++----- | |
| 32 | 1 file changed, 5 insertions(+), 5 deletions(-) | |
| 33 | ||
| 34 | --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h | |
| 35 | +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h | |
| 36 | @@ -89,11 +89,11 @@ typedef u64 iomux_v3_cfg_t; | |
| 37 | #define PAD_CTL_HYS (1 << 8) | |
| 38 | ||
| 39 | #define PAD_CTL_PKE (1 << 7) | |
| 40 | -#define PAD_CTL_PUE (1 << 6) | |
| 41 | -#define PAD_CTL_PUS_100K_DOWN (0 << 4) | |
| 42 | -#define PAD_CTL_PUS_47K_UP (1 << 4) | |
| 43 | -#define PAD_CTL_PUS_100K_UP (2 << 4) | |
| 44 | -#define PAD_CTL_PUS_22K_UP (3 << 4) | |
| 45 | +#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) | |
| 46 | +#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) | |
| 47 | +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) | |
| 48 | +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) | |
| 49 | +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) | |
| 50 | ||
| 51 | #define PAD_CTL_ODE (1 << 3) | |
| 52 |