projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c598465 GKH |
1 | From f64964796dedca340608fb1075ab6baad5625851 Mon Sep 17 00:00:00 2001 |
| 2 | From: Alex Deucher <alexander.deucher@amd.com> | |
| 3 | Date: Mon, 28 Nov 2011 14:49:26 -0500 | |
| 4 | Subject: drm/radeon/kms: add some loop timeouts in pageflip code | |
| 5 | ||
| 6 | From: Alex Deucher <alexander.deucher@amd.com> | |
| 7 | ||
| 8 | commit f64964796dedca340608fb1075ab6baad5625851 upstream. | |
| 9 | ||
| 10 | Avoid infinite loops waiting for surface updates if a GPU | |
| 11 | reset happens while waiting for a page flip. | |
| 12 | ||
| 13 | See: | |
| 14 | https://bugs.freedesktop.org/show_bug.cgi?id=43191 | |
| 15 | ||
| 16 | Signed-off-by: Alex Deucher <alexander.deucher@amd.com> | |
| 17 | Reviewed-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> | |
| 18 | Tested-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk> | |
| 19 | Signed-off-by: Dave Airlie <airlied@redhat.com> | |
| 20 | Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> | |
| 21 | ||
| 22 | --- | |
| 23 | drivers/gpu/drm/radeon/evergreen.c | 7 ++++++- | |
| 24 | drivers/gpu/drm/radeon/r100.c | 7 ++++++- | |
| 25 | drivers/gpu/drm/radeon/rs600.c | 7 ++++++- | |
| 26 | drivers/gpu/drm/radeon/rv770.c | 7 ++++++- | |
| 27 | 4 files changed, 24 insertions(+), 4 deletions(-) | |
| 28 | ||
| 29 | --- a/drivers/gpu/drm/radeon/evergreen.c | |
| 30 | +++ b/drivers/gpu/drm/radeon/evergreen.c | |
| 31 | @@ -82,6 +82,7 @@ u32 evergreen_page_flip(struct radeon_de | |
| 32 | { | |
| 33 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
| 34 | u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); | |
| 35 | + int i; | |
| 36 | ||
| 37 | /* Lock the graphics update lock */ | |
| 38 | tmp |= EVERGREEN_GRPH_UPDATE_LOCK; | |
| 39 | @@ -99,7 +100,11 @@ u32 evergreen_page_flip(struct radeon_de | |
| 40 | (u32)crtc_base); | |
| 41 | ||
| 42 | /* Wait for update_pending to go high. */ | |
| 43 | - while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)); | |
| 44 | + for (i = 0; i < rdev->usec_timeout; i++) { | |
| 45 | + if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) | |
| 46 | + break; | |
| 47 | + udelay(1); | |
| 48 | + } | |
| 49 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); | |
| 50 | ||
| 51 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
| 52 | --- a/drivers/gpu/drm/radeon/r100.c | |
| 53 | +++ b/drivers/gpu/drm/radeon/r100.c | |
| 54 | @@ -84,13 +84,18 @@ u32 r100_page_flip(struct radeon_device | |
| 55 | { | |
| 56 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
| 57 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; | |
| 58 | + int i; | |
| 59 | ||
| 60 | /* Lock the graphics update lock */ | |
| 61 | /* update the scanout addresses */ | |
| 62 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); | |
| 63 | ||
| 64 | /* Wait for update_pending to go high. */ | |
| 65 | - while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)); | |
| 66 | + for (i = 0; i < rdev->usec_timeout; i++) { | |
| 67 | + if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) | |
| 68 | + break; | |
| 69 | + udelay(1); | |
| 70 | + } | |
| 71 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); | |
| 72 | ||
| 73 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
| 74 | --- a/drivers/gpu/drm/radeon/rs600.c | |
| 75 | +++ b/drivers/gpu/drm/radeon/rs600.c | |
| 76 | @@ -62,6 +62,7 @@ u32 rs600_page_flip(struct radeon_device | |
| 77 | { | |
| 78 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
| 79 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); | |
| 80 | + int i; | |
| 81 | ||
| 82 | /* Lock the graphics update lock */ | |
| 83 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; | |
| 84 | @@ -74,7 +75,11 @@ u32 rs600_page_flip(struct radeon_device | |
| 85 | (u32)crtc_base); | |
| 86 | ||
| 87 | /* Wait for update_pending to go high. */ | |
| 88 | - while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); | |
| 89 | + for (i = 0; i < rdev->usec_timeout; i++) { | |
| 90 | + if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) | |
| 91 | + break; | |
| 92 | + udelay(1); | |
| 93 | + } | |
| 94 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); | |
| 95 | ||
| 96 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
| 97 | --- a/drivers/gpu/drm/radeon/rv770.c | |
| 98 | +++ b/drivers/gpu/drm/radeon/rv770.c | |
| 99 | @@ -47,6 +47,7 @@ u32 rv770_page_flip(struct radeon_device | |
| 100 | { | |
| 101 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
| 102 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); | |
| 103 | + int i; | |
| 104 | ||
| 105 | /* Lock the graphics update lock */ | |
| 106 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; | |
| 107 | @@ -66,7 +67,11 @@ u32 rv770_page_flip(struct radeon_device | |
| 108 | (u32)crtc_base); | |
| 109 | ||
| 110 | /* Wait for update_pending to go high. */ | |
| 111 | - while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); | |
| 112 | + for (i = 0; i < rdev->usec_timeout; i++) { | |
| 113 | + if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) | |
| 114 | + break; | |
| 115 | + udelay(1); | |
| 116 | + } | |
| 117 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); | |
| 118 | ||
| 119 | /* Unlock the lock, so double-buffering can take place inside vblank */ |