projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| f4176862 GKH |
1 | From 1b45adcd9a503428e6de6b39bc6892d86c9c1d41 Mon Sep 17 00:00:00 2001 |
| 2 | From: Peter Zijlstra <peterz@infradead.org> | |
| 3 | Date: Tue, 21 May 2013 13:05:37 +0200 | |
| 4 | Subject: perf/x86/amd: Rework AMD PMU init code | |
| 5 | ||
| 6 | From: Peter Zijlstra <peterz@infradead.org> | |
| 7 | ||
| 8 | commit 1b45adcd9a503428e6de6b39bc6892d86c9c1d41 upstream. | |
| 9 | ||
| 10 | Josh reported that his QEMU is a bad hardware emulator and trips a | |
| 11 | WARN in the AMD PMU init code. He requested the WARN be turned into a | |
| 12 | pr_err() or similar. | |
| 13 | ||
| 14 | While there, rework the code a little. | |
| 15 | ||
| 16 | Reported-by: Josh Boyer <jwboyer@redhat.com> | |
| 17 | Acked-by: Robert Richter <rric@kernel.org> | |
| 18 | Acked-by: Jacob Shin <jacob.shin@amd.com> | |
| 19 | Cc: Stephane Eranian <eranian@google.com> | |
| 20 | Signed-off-by: Peter Zijlstra <peterz@infradead.org> | |
| 21 | Link: http://lkml.kernel.org/r/20130521110537.GG26912@twins.programming.kicks-ass.net | |
| 22 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
| 23 | Cc: Guenter Roeck <linux@roeck-us.net> | |
| 24 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 25 | ||
| 26 | --- | |
| 27 | arch/x86/kernel/cpu/perf_event_amd.c | 34 +++++++++++++++++----------------- | |
| 28 | 1 file changed, 17 insertions(+), 17 deletions(-) | |
| 29 | ||
| 30 | --- a/arch/x86/kernel/cpu/perf_event_amd.c | |
| 31 | +++ b/arch/x86/kernel/cpu/perf_event_amd.c | |
| 32 | @@ -648,48 +648,48 @@ static __initconst const struct x86_pmu | |
| 33 | .cpu_dead = amd_pmu_cpu_dead, | |
| 34 | }; | |
| 35 | ||
| 36 | -static int setup_event_constraints(void) | |
| 37 | +static int __init amd_core_pmu_init(void) | |
| 38 | { | |
| 39 | - if (boot_cpu_data.x86 == 0x15) | |
| 40 | + if (!cpu_has_perfctr_core) | |
| 41 | + return 0; | |
| 42 | + | |
| 43 | + switch (boot_cpu_data.x86) { | |
| 44 | + case 0x15: | |
| 45 | + pr_cont("Fam15h "); | |
| 46 | x86_pmu.get_event_constraints = amd_get_event_constraints_f15h; | |
| 47 | - return 0; | |
| 48 | -} | |
| 49 | + break; | |
| 50 | ||
| 51 | -static int setup_perfctr_core(void) | |
| 52 | -{ | |
| 53 | - if (!cpu_has_perfctr_core) { | |
| 54 | - WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h, | |
| 55 | - KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!"); | |
| 56 | + default: | |
| 57 | + pr_err("core perfctr but no constraints; unknown hardware!\n"); | |
| 58 | return -ENODEV; | |
| 59 | } | |
| 60 | ||
| 61 | - WARN(x86_pmu.get_event_constraints == amd_get_event_constraints, | |
| 62 | - KERN_ERR "hw perf events core counters need constraints handler!"); | |
| 63 | - | |
| 64 | /* | |
| 65 | * If core performance counter extensions exists, we must use | |
| 66 | * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also | |
| 67 | - * x86_pmu_addr_offset(). | |
| 68 | + * amd_pmu_addr_offset(). | |
| 69 | */ | |
| 70 | x86_pmu.eventsel = MSR_F15H_PERF_CTL; | |
| 71 | x86_pmu.perfctr = MSR_F15H_PERF_CTR; | |
| 72 | x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE; | |
| 73 | ||
| 74 | - printk(KERN_INFO "perf: AMD core performance counters detected\n"); | |
| 75 | - | |
| 76 | + pr_cont("core perfctr, "); | |
| 77 | return 0; | |
| 78 | } | |
| 79 | ||
| 80 | __init int amd_pmu_init(void) | |
| 81 | { | |
| 82 | + int ret; | |
| 83 | + | |
| 84 | /* Performance-monitoring supported from K7 and later: */ | |
| 85 | if (boot_cpu_data.x86 < 6) | |
| 86 | return -ENODEV; | |
| 87 | ||
| 88 | x86_pmu = amd_pmu; | |
| 89 | ||
| 90 | - setup_event_constraints(); | |
| 91 | - setup_perfctr_core(); | |
| 92 | + ret = amd_core_pmu_init(); | |
| 93 | + if (ret) | |
| 94 | + return ret; | |
| 95 | ||
| 96 | /* Events are common for all AMDs */ | |
| 97 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, |