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Commit | Line | Data |
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9515b5a6 GKH |
1 | From 40ddbf5069bd4e11447c0088fc75318e0aac53f0 Mon Sep 17 00:00:00 2001 |
2 | From: Roger Quadros <rogerq@ti.com> | |
3 | Date: Mon, 25 Aug 2014 16:15:33 -0700 | |
4 | Subject: mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc() | |
5 | ||
6 | From: Roger Quadros <rogerq@ti.com> | |
7 | ||
8 | commit 40ddbf5069bd4e11447c0088fc75318e0aac53f0 upstream. | |
9 | ||
10 | commit 65b97cf6b8de introduced in v3.7 caused a regression | |
11 | by using a reversed CS_MASK thus causing omap_calculate_ecc to | |
12 | always fail. As the NAND base driver never checks for .calculate()'s | |
13 | return value, the zeroed ECC values are used as is without showing | |
14 | any error to the user. However, this won't work and the NAND device | |
15 | won't be guarded by any error code. | |
16 | ||
17 | Fix the issue by using the correct mask. | |
18 | ||
19 | Code was tested on omap3beagle using the following procedure | |
20 | - flash the primary bootloader (MLO) from the kernel to the first | |
21 | NAND partition using nandwrite. | |
22 | - boot the board from NAND. This utilizes OMAP ROM loader that | |
23 | relies on 1-bit Hamming code ECC. | |
24 | ||
25 | Fixes: 65b97cf6b8de (mtd: nand: omap2: handle nand on gpmc) | |
26 | ||
27 | Signed-off-by: Roger Quadros <rogerq@ti.com> | |
28 | Signed-off-by: Tony Lindgren <tony@atomide.com> | |
29 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
30 | ||
31 | --- | |
32 | drivers/mtd/nand/omap2.c | 2 +- | |
33 | 1 file changed, 1 insertion(+), 1 deletion(-) | |
34 | ||
35 | --- a/drivers/mtd/nand/omap2.c | |
36 | +++ b/drivers/mtd/nand/omap2.c | |
37 | @@ -931,7 +931,7 @@ static int omap_calculate_ecc(struct mtd | |
38 | u32 val; | |
39 | ||
40 | val = readl(info->reg.gpmc_ecc_config); | |
41 | - if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
42 | + if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) | |
43 | return -EINVAL; | |
44 | ||
45 | /* read ecc result */ |